125734281SStephen Warren/dts-v1/; 225734281SStephen Warren 325734281SStephen Warren#include "tegra210.dtsi" 425734281SStephen Warren 525734281SStephen Warren/ { 625734281SStephen Warren model = "NVIDIA P2371-2180"; 725734281SStephen Warren compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 825734281SStephen Warren 925734281SStephen Warren chosen { 1025734281SStephen Warren stdout-path = &uarta; 1125734281SStephen Warren }; 1225734281SStephen Warren 1325734281SStephen Warren aliases { 1425734281SStephen Warren i2c0 = "/i2c@0,7000d000"; 1525734281SStephen Warren sdhci0 = "/sdhci@0,700b0600"; 1625734281SStephen Warren sdhci1 = "/sdhci@0,700b0000"; 1725734281SStephen Warren usb0 = "/usb@0,7d000000"; 1825734281SStephen Warren }; 1925734281SStephen Warren 2025734281SStephen Warren memory { 2125734281SStephen Warren reg = <0x0 0x80000000 0x0 0xc0000000>; 2225734281SStephen Warren }; 2325734281SStephen Warren 24*019bc625SStephen Warren pcie-controller@0,01003000 { 25*019bc625SStephen Warren status = "okay"; 26*019bc625SStephen Warren 27*019bc625SStephen Warren pci@1,0 { 28*019bc625SStephen Warren status = "okay"; 29*019bc625SStephen Warren }; 30*019bc625SStephen Warren 31*019bc625SStephen Warren pci@2,0 { 32*019bc625SStephen Warren status = "okay"; 33*019bc625SStephen Warren }; 34*019bc625SStephen Warren }; 35*019bc625SStephen Warren 36*019bc625SStephen Warren padctl@0,7009f000 { 37*019bc625SStephen Warren pinctrl-0 = <&padctl_default>; 38*019bc625SStephen Warren pinctrl-names = "default"; 39*019bc625SStephen Warren 40*019bc625SStephen Warren padctl_default: pinmux { 41*019bc625SStephen Warren xusb { 42*019bc625SStephen Warren nvidia,lanes = "otg-1", "otg-2"; 43*019bc625SStephen Warren nvidia,function = "xusb"; 44*019bc625SStephen Warren nvidia,iddq = <0>; 45*019bc625SStephen Warren }; 46*019bc625SStephen Warren 47*019bc625SStephen Warren usb3 { 48*019bc625SStephen Warren nvidia,lanes = "pcie-5", "pcie-6"; 49*019bc625SStephen Warren nvidia,function = "usb3"; 50*019bc625SStephen Warren nvidia,iddq = <0>; 51*019bc625SStephen Warren }; 52*019bc625SStephen Warren 53*019bc625SStephen Warren pcie-x1 { 54*019bc625SStephen Warren nvidia,lanes = "pcie-0"; 55*019bc625SStephen Warren nvidia,function = "pcie-x1"; 56*019bc625SStephen Warren nvidia,iddq = <0>; 57*019bc625SStephen Warren }; 58*019bc625SStephen Warren 59*019bc625SStephen Warren pcie-x4 { 60*019bc625SStephen Warren nvidia,lanes = "pcie-1", "pcie-2", 61*019bc625SStephen Warren "pcie-3", "pcie-4"; 62*019bc625SStephen Warren nvidia,function = "pcie-x4"; 63*019bc625SStephen Warren nvidia,iddq = <0>; 64*019bc625SStephen Warren }; 65*019bc625SStephen Warren 66*019bc625SStephen Warren sata { 67*019bc625SStephen Warren nvidia,lanes = "sata-0"; 68*019bc625SStephen Warren nvidia,function = "sata"; 69*019bc625SStephen Warren nvidia,iddq = <0>; 70*019bc625SStephen Warren }; 71*019bc625SStephen Warren }; 72*019bc625SStephen Warren }; 73*019bc625SStephen Warren 7425734281SStephen Warren sdhci@0,700b0000 { 7525734281SStephen Warren status = "okay"; 7625734281SStephen Warren cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 7725734281SStephen Warren power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 7825734281SStephen Warren wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>; 7925734281SStephen Warren bus-width = <4>; 8025734281SStephen Warren }; 8125734281SStephen Warren 8225734281SStephen Warren sdhci@0,700b0600 { 8325734281SStephen Warren status = "okay"; 8425734281SStephen Warren bus-width = <8>; 8525734281SStephen Warren }; 8625734281SStephen Warren 8725734281SStephen Warren i2c@0,7000d000 { 8825734281SStephen Warren status = "okay"; 8925734281SStephen Warren clock-frequency = <400000>; 9025734281SStephen Warren }; 9125734281SStephen Warren 9225734281SStephen Warren usb@0,7d000000 { 9325734281SStephen Warren status = "okay"; 9425734281SStephen Warren dr_mode = "otg"; 9525734281SStephen Warren nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; 9625734281SStephen Warren }; 9725734281SStephen Warren 9825734281SStephen Warren clocks { 9925734281SStephen Warren compatible = "simple-bus"; 10025734281SStephen Warren #address-cells = <1>; 10125734281SStephen Warren #size-cells = <0>; 10225734281SStephen Warren 10325734281SStephen Warren clk32k_in: clock@0 { 10425734281SStephen Warren compatible = "fixed-clock"; 10525734281SStephen Warren reg = <0>; 10625734281SStephen Warren #clock-cells = <0>; 10725734281SStephen Warren clock-frequency = <32768>; 10825734281SStephen Warren }; 10925734281SStephen Warren }; 11025734281SStephen Warren}; 111