1#include <dt-bindings/clock/tegra20-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4 5#include "skeleton.dtsi" 6 7/ { 8 compatible = "nvidia,tegra20"; 9 interrupt-parent = <&intc>; 10 11 host1x { 12 compatible = "nvidia,tegra20-host1x", "simple-bus"; 13 reg = <0x50000000 0x00024000>; 14 interrupts = <0 65 0x04 /* mpcore syncpt */ 15 0 67 0x04>; /* mpcore general */ 16 status = "disabled"; 17 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 ranges = <0x54000000 0x54000000 0x04000000>; 22 23 /* video-encoding/decoding */ 24 mpe { 25 reg = <0x54040000 0x00040000>; 26 interrupts = <0 68 0x04>; 27 status = "disabled"; 28 }; 29 30 /* video input */ 31 vi { 32 reg = <0x54080000 0x00040000>; 33 interrupts = <0 69 0x04>; 34 status = "disabled"; 35 }; 36 37 /* EPP */ 38 epp { 39 reg = <0x540c0000 0x00040000>; 40 interrupts = <0 70 0x04>; 41 status = "disabled"; 42 }; 43 44 /* ISP */ 45 isp { 46 reg = <0x54100000 0x00040000>; 47 interrupts = <0 71 0x04>; 48 status = "disabled"; 49 }; 50 51 /* 2D engine */ 52 gr2d { 53 reg = <0x54140000 0x00040000>; 54 interrupts = <0 72 0x04>; 55 status = "disabled"; 56 }; 57 58 /* 3D engine */ 59 gr3d { 60 reg = <0x54180000 0x00040000>; 61 status = "disabled"; 62 }; 63 64 /* display controllers */ 65 dc@54200000 { 66 compatible = "nvidia,tegra20-dc"; 67 reg = <0x54200000 0x00040000>; 68 interrupts = <0 73 0x04>; 69 status = "disabled"; 70 71 rgb { 72 status = "disabled"; 73 }; 74 }; 75 76 dc@54240000 { 77 compatible = "nvidia,tegra20-dc"; 78 reg = <0x54240000 0x00040000>; 79 interrupts = <0 74 0x04>; 80 status = "disabled"; 81 82 rgb { 83 status = "disabled"; 84 }; 85 }; 86 87 /* outputs */ 88 hdmi { 89 compatible = "nvidia,tegra20-hdmi"; 90 reg = <0x54280000 0x00040000>; 91 interrupts = <0 75 0x04>; 92 status = "disabled"; 93 }; 94 95 tvo { 96 compatible = "nvidia,tegra20-tvo"; 97 reg = <0x542c0000 0x00040000>; 98 interrupts = <0 76 0x04>; 99 status = "disabled"; 100 }; 101 102 dsi { 103 compatible = "nvidia,tegra20-dsi"; 104 reg = <0x54300000 0x00040000>; 105 status = "disabled"; 106 }; 107 }; 108 109 intc: interrupt-controller@50041000 { 110 compatible = "nvidia,tegra20-gic"; 111 interrupt-controller; 112 #interrupt-cells = <1>; 113 reg = < 0x50041000 0x1000 >, 114 < 0x50040100 0x0100 >; 115 }; 116 117 tegra_car: clock@60006000 { 118 compatible = "nvidia,tegra20-car"; 119 reg = <0x60006000 0x1000>; 120 #clock-cells = <1>; 121 }; 122 123 apbdma: dma { 124 compatible = "nvidia,tegra20-apbdma"; 125 reg = <0x6000a000 0x1200>; 126 interrupts = <0 104 0x04 127 0 105 0x04 128 0 106 0x04 129 0 107 0x04 130 0 108 0x04 131 0 109 0x04 132 0 110 0x04 133 0 111 0x04 134 0 112 0x04 135 0 113 0x04 136 0 114 0x04 137 0 115 0x04 138 0 116 0x04 139 0 117 0x04 140 0 118 0x04 141 0 119 0x04>; 142 }; 143 144 gpio: gpio@6000d000 { 145 compatible = "nvidia,tegra20-gpio"; 146 reg = <0x6000d000 0x1000>; 147 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 154 #gpio-cells = <2>; 155 gpio-controller; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 }; 159 160 pinmux: pinmux@70000000 { 161 compatible = "nvidia,tegra20-pinmux"; 162 reg = < 0x70000014 0x10 /* Tri-state registers */ 163 0x70000080 0x20 /* Mux registers */ 164 0x700000a0 0x14 /* Pull-up/down registers */ 165 0x70000868 0xa8 >; /* Pad control registers */ 166 }; 167 168 das@70000c00 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "nvidia,tegra20-das"; 172 reg = <0x70000c00 0x80>; 173 }; 174 175 i2s@70002800 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "nvidia,tegra20-i2s"; 179 reg = <0x70002800 0x200>; 180 interrupts = < 45 >; 181 dma-channel = < 2 >; 182 }; 183 184 i2s@70002a00 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "nvidia,tegra20-i2s"; 188 reg = <0x70002a00 0x200>; 189 interrupts = < 35 >; 190 dma-channel = < 1 >; 191 }; 192 193 uarta: serial@70006000 { 194 compatible = "nvidia,tegra20-uart"; 195 reg = <0x70006000 0x40>; 196 reg-shift = <2>; 197 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 199 resets = <&tegra_car 6>; 200 reset-names = "serial"; 201 dmas = <&apbdma 8>, <&apbdma 8>; 202 dma-names = "rx", "tx"; 203 status = "disabled"; 204 }; 205 206 uartb: serial@70006040 { 207 compatible = "nvidia,tegra20-uart"; 208 reg = <0x70006040 0x40>; 209 reg-shift = <2>; 210 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 212 resets = <&tegra_car 7>; 213 reset-names = "serial"; 214 dmas = <&apbdma 9>, <&apbdma 9>; 215 dma-names = "rx", "tx"; 216 status = "disabled"; 217 }; 218 219 uartc: serial@70006200 { 220 compatible = "nvidia,tegra20-uart"; 221 reg = <0x70006200 0x100>; 222 reg-shift = <2>; 223 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 225 resets = <&tegra_car 55>; 226 reset-names = "serial"; 227 dmas = <&apbdma 10>, <&apbdma 10>; 228 dma-names = "rx", "tx"; 229 status = "disabled"; 230 }; 231 232 uartd: serial@70006300 { 233 compatible = "nvidia,tegra20-uart"; 234 reg = <0x70006300 0x100>; 235 reg-shift = <2>; 236 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 238 resets = <&tegra_car 65>; 239 reset-names = "serial"; 240 dmas = <&apbdma 19>, <&apbdma 19>; 241 dma-names = "rx", "tx"; 242 status = "disabled"; 243 }; 244 245 uarte: serial@70006400 { 246 compatible = "nvidia,tegra20-uart"; 247 reg = <0x70006400 0x100>; 248 reg-shift = <2>; 249 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 251 resets = <&tegra_car 66>; 252 reset-names = "serial"; 253 dmas = <&apbdma 20>, <&apbdma 20>; 254 dma-names = "rx", "tx"; 255 status = "disabled"; 256 }; 257 258 nand: nand-controller@70008000 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "nvidia,tegra20-nand"; 262 reg = <0x70008000 0x100>; 263 }; 264 265 pwm: pwm@7000a000 { 266 compatible = "nvidia,tegra20-pwm"; 267 reg = <0x7000a000 0x100>; 268 #pwm-cells = <2>; 269 }; 270 271 i2c@7000c000 { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 compatible = "nvidia,tegra20-i2c"; 275 reg = <0x7000C000 0x100>; 276 interrupts = < 70 >; 277 /* PERIPH_ID_I2C1, PLL_P_OUT3 */ 278 clocks = <&tegra_car 12>, <&tegra_car 124>; 279 }; 280 281 spi@7000c380 { 282 compatible = "nvidia,tegra20-sflash"; 283 reg = <0x7000c380 0x80>; 284 interrupts = <0 39 0x04>; 285 nvidia,dma-request-selector = <&apbdma 11>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 /* PERIPH_ID_SPI1, PLLP_OUT0 */ 290 clocks = <&tegra_car 43>; 291 }; 292 293 i2c@7000c400 { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 compatible = "nvidia,tegra20-i2c"; 297 reg = <0x7000C400 0x100>; 298 interrupts = < 116 >; 299 /* PERIPH_ID_I2C2, PLL_P_OUT3 */ 300 clocks = <&tegra_car 54>, <&tegra_car 124>; 301 }; 302 303 i2c@7000c500 { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 compatible = "nvidia,tegra20-i2c"; 307 reg = <0x7000C500 0x100>; 308 interrupts = < 124 >; 309 /* PERIPH_ID_I2C3, PLL_P_OUT3 */ 310 clocks = <&tegra_car 67>, <&tegra_car 124>; 311 }; 312 313 i2c@7000d000 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 compatible = "nvidia,tegra20-i2c-dvc"; 317 reg = <0x7000D000 0x200>; 318 interrupts = < 85 >; 319 /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ 320 clocks = <&tegra_car 47>, <&tegra_car 124>; 321 }; 322 323 kbc@7000e200 { 324 compatible = "nvidia,tegra20-kbc"; 325 reg = <0x7000e200 0x0078>; 326 }; 327 328 emc@7000f400 { 329 #address-cells = < 1 >; 330 #size-cells = < 0 >; 331 compatible = "nvidia,tegra20-emc"; 332 reg = <0x7000f400 0x200>; 333 }; 334 335 pcie-controller@80003000 { 336 compatible = "nvidia,tegra20-pcie"; 337 device_type = "pci"; 338 reg = <0x80003000 0x00000800 /* PADS registers */ 339 0x80003800 0x00000200 /* AFI registers */ 340 0x90000000 0x10000000>; /* configuration space */ 341 reg-names = "pads", "afi", "cs"; 342 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 343 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 344 interrupt-names = "intr", "msi"; 345 346 #interrupt-cells = <1>; 347 interrupt-map-mask = <0 0 0 0>; 348 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 349 350 bus-range = <0x00 0xff>; 351 #address-cells = <3>; 352 #size-cells = <2>; 353 354 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 355 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 356 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 357 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ 358 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 359 360 clocks = <&tegra_car TEGRA20_CLK_PEX>, 361 <&tegra_car TEGRA20_CLK_AFI>, 362 <&tegra_car TEGRA20_CLK_PCIE_XCLK>, 363 <&tegra_car TEGRA20_CLK_PLL_E>; 364 clock-names = "pex", "afi", "pcie_xclk", "pll_e"; 365 status = "disabled"; 366 367 pci@1,0 { 368 device_type = "pci"; 369 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 370 reg = <0x000800 0 0 0 0>; 371 status = "disabled"; 372 373 #address-cells = <3>; 374 #size-cells = <2>; 375 ranges; 376 377 nvidia,num-lanes = <2>; 378 }; 379 380 pci@2,0 { 381 device_type = "pci"; 382 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 383 reg = <0x001000 0 0 0 0>; 384 status = "disabled"; 385 386 #address-cells = <3>; 387 #size-cells = <2>; 388 ranges; 389 390 nvidia,num-lanes = <2>; 391 }; 392 }; 393 394 usb@c5000000 { 395 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 396 reg = <0xc5000000 0x4000>; 397 interrupts = < 52 >; 398 phy_type = "utmi"; 399 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ 400 nvidia,has-legacy-mode; 401 }; 402 403 usb@c5004000 { 404 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 405 reg = <0xc5004000 0x4000>; 406 interrupts = < 53 >; 407 phy_type = "ulpi"; 408 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ 409 }; 410 411 usb@c5008000 { 412 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 413 reg = <0xc5008000 0x4000>; 414 interrupts = < 129 >; 415 phy_type = "utmi"; 416 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ 417 }; 418 419 sdhci@c8000000 { 420 compatible = "nvidia,tegra20-sdhci"; 421 reg = <0xc8000000 0x200>; 422 interrupts = <0 14 0x04>; 423 clocks = <&tegra_car 14>; 424 status = "disabled"; 425 }; 426 427 sdhci@c8000200 { 428 compatible = "nvidia,tegra20-sdhci"; 429 reg = <0xc8000200 0x200>; 430 interrupts = <0 15 0x04>; 431 clocks = <&tegra_car 9>; 432 status = "disabled"; 433 }; 434 435 sdhci@c8000400 { 436 compatible = "nvidia,tegra20-sdhci"; 437 reg = <0xc8000400 0x200>; 438 interrupts = <0 19 0x04>; 439 clocks = <&tegra_car 69>; 440 status = "disabled"; 441 }; 442 443 sdhci@c8000600 { 444 compatible = "nvidia,tegra20-sdhci"; 445 reg = <0xc8000600 0x200>; 446 interrupts = <0 31 0x04>; 447 clocks = <&tegra_car 15>; 448 status = "disabled"; 449 }; 450}; 451