1#include <dt-bindings/clock/tegra20-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5 6#include "skeleton.dtsi" 7 8/ { 9 compatible = "nvidia,tegra20"; 10 interrupt-parent = <&lic>; 11 12 host1x@50000000 { 13 u-boot,dm-pre-reloc; 14 compatible = "nvidia,tegra20-host1x", "simple-bus"; 15 reg = <0x50000000 0x00024000>; 16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 19 resets = <&tegra_car 28>; 20 reset-names = "host1x"; 21 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 ranges = <0x54000000 0x54000000 0x04000000>; 26 27 mpe@54040000 { 28 compatible = "nvidia,tegra20-mpe"; 29 reg = <0x54040000 0x00040000>; 30 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 31 clocks = <&tegra_car TEGRA20_CLK_MPE>; 32 resets = <&tegra_car 60>; 33 reset-names = "mpe"; 34 }; 35 36 vi@54080000 { 37 compatible = "nvidia,tegra20-vi"; 38 reg = <0x54080000 0x00040000>; 39 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 40 clocks = <&tegra_car TEGRA20_CLK_VI>; 41 resets = <&tegra_car 20>; 42 reset-names = "vi"; 43 }; 44 45 epp@540c0000 { 46 compatible = "nvidia,tegra20-epp"; 47 reg = <0x540c0000 0x00040000>; 48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 49 clocks = <&tegra_car TEGRA20_CLK_EPP>; 50 resets = <&tegra_car 19>; 51 reset-names = "epp"; 52 }; 53 54 isp@54100000 { 55 compatible = "nvidia,tegra20-isp"; 56 reg = <0x54100000 0x00040000>; 57 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&tegra_car TEGRA20_CLK_ISP>; 59 resets = <&tegra_car 23>; 60 reset-names = "isp"; 61 }; 62 63 gr2d@54140000 { 64 compatible = "nvidia,tegra20-gr2d"; 65 reg = <0x54140000 0x00040000>; 66 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 68 resets = <&tegra_car 21>; 69 reset-names = "2d"; 70 }; 71 72 gr3d@54180000 { 73 compatible = "nvidia,tegra20-gr3d"; 74 reg = <0x54180000 0x00040000>; 75 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 76 resets = <&tegra_car 24>; 77 reset-names = "3d"; 78 }; 79 80 dc@54200000 { 81 u-boot,dm-pre-reloc; 82 compatible = "nvidia,tegra20-dc"; 83 reg = <0x54200000 0x00040000>; 84 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 85 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 86 <&tegra_car TEGRA20_CLK_PLL_P>; 87 clock-names = "dc", "parent"; 88 resets = <&tegra_car 27>; 89 reset-names = "dc"; 90 91 nvidia,head = <0>; 92 93 rgb { 94 status = "disabled"; 95 }; 96 }; 97 98 dc@54240000 { 99 compatible = "nvidia,tegra20-dc"; 100 reg = <0x54240000 0x00040000>; 101 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 103 <&tegra_car TEGRA20_CLK_PLL_P>; 104 clock-names = "dc", "parent"; 105 resets = <&tegra_car 26>; 106 reset-names = "dc"; 107 108 nvidia,head = <1>; 109 110 rgb { 111 status = "disabled"; 112 }; 113 }; 114 115 hdmi@54280000 { 116 compatible = "nvidia,tegra20-hdmi"; 117 reg = <0x54280000 0x00040000>; 118 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 120 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 121 clock-names = "hdmi", "parent"; 122 resets = <&tegra_car 51>; 123 reset-names = "hdmi"; 124 status = "disabled"; 125 }; 126 127 tvo@542c0000 { 128 compatible = "nvidia,tegra20-tvo"; 129 reg = <0x542c0000 0x00040000>; 130 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA20_CLK_TVO>; 132 status = "disabled"; 133 }; 134 135 dsi@54300000 { 136 compatible = "nvidia,tegra20-dsi"; 137 reg = <0x54300000 0x00040000>; 138 clocks = <&tegra_car TEGRA20_CLK_DSI>; 139 resets = <&tegra_car 48>; 140 reset-names = "dsi"; 141 status = "disabled"; 142 }; 143 }; 144 145 timer@50040600 { 146 compatible = "arm,cortex-a9-twd-timer"; 147 interrupt-parent = <&intc>; 148 reg = <0x50040600 0x20>; 149 interrupts = <GIC_PPI 13 150 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 151 clocks = <&tegra_car TEGRA20_CLK_TWD>; 152 }; 153 154 intc: interrupt-controller@50041000 { 155 compatible = "arm,cortex-a9-gic"; 156 reg = <0x50041000 0x1000 157 0x50040100 0x0100>; 158 interrupt-controller; 159 #interrupt-cells = <3>; 160 interrupt-parent = <&intc>; 161 }; 162 163 cache-controller@50043000 { 164 compatible = "arm,pl310-cache"; 165 reg = <0x50043000 0x1000>; 166 arm,data-latency = <5 5 2>; 167 arm,tag-latency = <4 4 2>; 168 cache-unified; 169 cache-level = <2>; 170 }; 171 172 lic: interrupt-controller@60004000 { 173 compatible = "nvidia,tegra20-ictlr"; 174 reg = <0x60004000 0x100>, 175 <0x60004100 0x50>, 176 <0x60004200 0x50>, 177 <0x60004300 0x50>; 178 interrupt-controller; 179 #interrupt-cells = <3>; 180 interrupt-parent = <&intc>; 181 }; 182 183 timer@60005000 { 184 compatible = "nvidia,tegra20-timer"; 185 reg = <0x60005000 0x60>; 186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 191 }; 192 193 tegra_car: clock@60006000 { 194 compatible = "nvidia,tegra20-car"; 195 reg = <0x60006000 0x1000>; 196 #clock-cells = <1>; 197 #reset-cells = <1>; 198 }; 199 200 flow-controller@60007000 { 201 compatible = "nvidia,tegra20-flowctrl"; 202 reg = <0x60007000 0x1000>; 203 }; 204 205 apbdma: dma@6000a000 { 206 compatible = "nvidia,tegra20-apbdma"; 207 reg = <0x6000a000 0x1200>; 208 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 225 resets = <&tegra_car 34>; 226 reset-names = "dma"; 227 #dma-cells = <1>; 228 }; 229 230 ahb@6000c000 { 231 compatible = "nvidia,tegra20-ahb"; 232 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 233 }; 234 235 gpio: gpio@6000d000 { 236 compatible = "nvidia,tegra20-gpio"; 237 reg = <0x6000d000 0x1000>; 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 245 #gpio-cells = <2>; 246 gpio-controller; 247 #interrupt-cells = <2>; 248 interrupt-controller; 249 /* 250 gpio-ranges = <&pinmux 0 0 224>; 251 */ 252 }; 253 254 apbmisc@70000800 { 255 compatible = "nvidia,tegra20-apbmisc"; 256 reg = <0x70000800 0x64 /* Chip revision */ 257 0x70000008 0x04>; /* Strapping options */ 258 }; 259 260 pinmux: pinmux@70000014 { 261 compatible = "nvidia,tegra20-pinmux"; 262 reg = <0x70000014 0x10 /* Tri-state registers */ 263 0x70000080 0x20 /* Mux registers */ 264 0x700000a0 0x14 /* Pull-up/down registers */ 265 0x70000868 0xa8>; /* Pad control registers */ 266 }; 267 268 das@70000c00 { 269 compatible = "nvidia,tegra20-das"; 270 reg = <0x70000c00 0x80>; 271 }; 272 273 tegra_ac97: ac97@70002000 { 274 compatible = "nvidia,tegra20-ac97"; 275 reg = <0x70002000 0x200>; 276 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&tegra_car TEGRA20_CLK_AC97>; 278 resets = <&tegra_car 3>; 279 reset-names = "ac97"; 280 dmas = <&apbdma 12>, <&apbdma 12>; 281 dma-names = "rx", "tx"; 282 status = "disabled"; 283 }; 284 285 tegra_i2s1: i2s@70002800 { 286 compatible = "nvidia,tegra20-i2s"; 287 reg = <0x70002800 0x200>; 288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 290 resets = <&tegra_car 11>; 291 reset-names = "i2s"; 292 dmas = <&apbdma 2>, <&apbdma 2>; 293 dma-names = "rx", "tx"; 294 status = "disabled"; 295 }; 296 297 tegra_i2s2: i2s@70002a00 { 298 compatible = "nvidia,tegra20-i2s"; 299 reg = <0x70002a00 0x200>; 300 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 302 resets = <&tegra_car 18>; 303 reset-names = "i2s"; 304 dmas = <&apbdma 1>, <&apbdma 1>; 305 dma-names = "rx", "tx"; 306 status = "disabled"; 307 }; 308 309 /* 310 * There are two serial driver i.e. 8250 based simple serial 311 * driver and APB DMA based serial driver for higher baudrate 312 * and performace. To enable the 8250 based driver, the compatible 313 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 314 * driver, the compatible is "nvidia,tegra20-hsuart". 315 */ 316 uarta: serial@70006000 { 317 compatible = "nvidia,tegra20-uart"; 318 reg = <0x70006000 0x40>; 319 reg-shift = <2>; 320 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 322 resets = <&tegra_car 6>; 323 reset-names = "serial"; 324 dmas = <&apbdma 8>, <&apbdma 8>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 }; 328 329 uartb: serial@70006040 { 330 compatible = "nvidia,tegra20-uart"; 331 reg = <0x70006040 0x40>; 332 reg-shift = <2>; 333 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 335 resets = <&tegra_car 7>; 336 reset-names = "serial"; 337 dmas = <&apbdma 9>, <&apbdma 9>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 uartc: serial@70006200 { 343 compatible = "nvidia,tegra20-uart"; 344 reg = <0x70006200 0x100>; 345 reg-shift = <2>; 346 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 348 resets = <&tegra_car 55>; 349 reset-names = "serial"; 350 dmas = <&apbdma 10>, <&apbdma 10>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 uartd: serial@70006300 { 356 compatible = "nvidia,tegra20-uart"; 357 reg = <0x70006300 0x100>; 358 reg-shift = <2>; 359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 361 resets = <&tegra_car 65>; 362 reset-names = "serial"; 363 dmas = <&apbdma 19>, <&apbdma 19>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 uarte: serial@70006400 { 369 compatible = "nvidia,tegra20-uart"; 370 reg = <0x70006400 0x100>; 371 reg-shift = <2>; 372 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 374 resets = <&tegra_car 66>; 375 reset-names = "serial"; 376 dmas = <&apbdma 20>, <&apbdma 20>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 nand: nand-controller@70008000 { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 compatible = "nvidia,tegra20-nand"; 385 reg = <0x70008000 0x100>; 386 }; 387 388 pwm: pwm@7000a000 { 389 compatible = "nvidia,tegra20-pwm"; 390 reg = <0x7000a000 0x100>; 391 #pwm-cells = <2>; 392 clocks = <&tegra_car TEGRA20_CLK_PWM>; 393 resets = <&tegra_car 17>; 394 reset-names = "pwm"; 395 status = "disabled"; 396 }; 397 398 rtc@7000e000 { 399 compatible = "nvidia,tegra20-rtc"; 400 reg = <0x7000e000 0x100>; 401 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&tegra_car TEGRA20_CLK_RTC>; 403 }; 404 405 i2c@7000c000 { 406 compatible = "nvidia,tegra20-i2c"; 407 reg = <0x7000c000 0x100>; 408 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 412 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 413 clock-names = "div-clk", "fast-clk"; 414 resets = <&tegra_car 12>; 415 reset-names = "i2c"; 416 dmas = <&apbdma 21>, <&apbdma 21>; 417 dma-names = "rx", "tx"; 418 status = "disabled"; 419 }; 420 421 spi@7000c380 { 422 compatible = "nvidia,tegra20-sflash"; 423 reg = <0x7000c380 0x80>; 424 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&tegra_car TEGRA20_CLK_SPI>; 428 resets = <&tegra_car 43>; 429 reset-names = "spi"; 430 dmas = <&apbdma 11>, <&apbdma 11>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 i2c@7000c400 { 436 compatible = "nvidia,tegra20-i2c"; 437 reg = <0x7000c400 0x100>; 438 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 442 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 443 clock-names = "div-clk", "fast-clk"; 444 resets = <&tegra_car 54>; 445 reset-names = "i2c"; 446 dmas = <&apbdma 22>, <&apbdma 22>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 i2c@7000c500 { 452 compatible = "nvidia,tegra20-i2c"; 453 reg = <0x7000c500 0x100>; 454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 458 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 459 clock-names = "div-clk", "fast-clk"; 460 resets = <&tegra_car 67>; 461 reset-names = "i2c"; 462 dmas = <&apbdma 23>, <&apbdma 23>; 463 dma-names = "rx", "tx"; 464 status = "disabled"; 465 }; 466 467 i2c@7000d000 { 468 compatible = "nvidia,tegra20-i2c-dvc"; 469 reg = <0x7000d000 0x200>; 470 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 clocks = <&tegra_car TEGRA20_CLK_DVC>, 474 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 475 clock-names = "div-clk", "fast-clk"; 476 resets = <&tegra_car 47>; 477 reset-names = "i2c"; 478 dmas = <&apbdma 24>, <&apbdma 24>; 479 dma-names = "rx", "tx"; 480 status = "disabled"; 481 }; 482 483 spi@7000d400 { 484 compatible = "nvidia,tegra20-slink"; 485 reg = <0x7000d400 0x200>; 486 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 490 resets = <&tegra_car 41>; 491 reset-names = "spi"; 492 dmas = <&apbdma 15>, <&apbdma 15>; 493 dma-names = "rx", "tx"; 494 status = "disabled"; 495 }; 496 497 spi@7000d600 { 498 compatible = "nvidia,tegra20-slink"; 499 reg = <0x7000d600 0x200>; 500 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 504 resets = <&tegra_car 44>; 505 reset-names = "spi"; 506 dmas = <&apbdma 16>, <&apbdma 16>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 spi@7000d800 { 512 compatible = "nvidia,tegra20-slink"; 513 reg = <0x7000d800 0x200>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 518 resets = <&tegra_car 46>; 519 reset-names = "spi"; 520 dmas = <&apbdma 17>, <&apbdma 17>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 spi@7000da00 { 526 compatible = "nvidia,tegra20-slink"; 527 reg = <0x7000da00 0x200>; 528 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 532 resets = <&tegra_car 68>; 533 reset-names = "spi"; 534 dmas = <&apbdma 18>, <&apbdma 18>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 kbc@7000e200 { 540 compatible = "nvidia,tegra20-kbc"; 541 reg = <0x7000e200 0x100>; 542 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&tegra_car TEGRA20_CLK_KBC>; 544 resets = <&tegra_car 36>; 545 reset-names = "kbc"; 546 status = "disabled"; 547 }; 548 549 pmc@7000e400 { 550 compatible = "nvidia,tegra20-pmc"; 551 reg = <0x7000e400 0x400>; 552 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 553 clock-names = "pclk", "clk32k_in"; 554 }; 555 556 memory-controller@7000f000 { 557 compatible = "nvidia,tegra20-mc"; 558 reg = <0x7000f000 0x024 559 0x7000f03c 0x3c4>; 560 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 561 }; 562 563 iommu@7000f024 { 564 compatible = "nvidia,tegra20-gart"; 565 reg = <0x7000f024 0x00000018 /* controller registers */ 566 0x58000000 0x02000000>; /* GART aperture */ 567 }; 568 569 memory-controller@7000f400 { 570 compatible = "nvidia,tegra20-emc"; 571 reg = <0x7000f400 0x200>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 576 fuse@7000f800 { 577 compatible = "nvidia,tegra20-efuse"; 578 reg = <0x7000f800 0x400>; 579 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 580 clock-names = "fuse"; 581 resets = <&tegra_car 39>; 582 reset-names = "fuse"; 583 }; 584 585 pcie-controller@80003000 { 586 compatible = "nvidia,tegra20-pcie"; 587 device_type = "pci"; 588 reg = <0x80003000 0x00000800 /* PADS registers */ 589 0x80003800 0x00000200 /* AFI registers */ 590 0x90000000 0x10000000>; /* configuration space */ 591 reg-names = "pads", "afi", "cs"; 592 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 593 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 594 interrupt-names = "intr", "msi"; 595 596 #interrupt-cells = <1>; 597 interrupt-map-mask = <0 0 0 0>; 598 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 599 600 bus-range = <0x00 0xff>; 601 #address-cells = <3>; 602 #size-cells = <2>; 603 604 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 605 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 606 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 607 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ 608 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 609 610 clocks = <&tegra_car TEGRA20_CLK_PEX>, 611 <&tegra_car TEGRA20_CLK_AFI>, 612 <&tegra_car TEGRA20_CLK_PLL_E>; 613 clock-names = "pex", "afi", "pll_e"; 614 resets = <&tegra_car 70>, 615 <&tegra_car 72>, 616 <&tegra_car 74>; 617 reset-names = "pex", "afi", "pcie_x"; 618 status = "disabled"; 619 620 pci@1,0 { 621 device_type = "pci"; 622 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 623 reg = <0x000800 0 0 0 0>; 624 status = "disabled"; 625 626 #address-cells = <3>; 627 #size-cells = <2>; 628 ranges; 629 630 nvidia,num-lanes = <2>; 631 }; 632 633 pci@2,0 { 634 device_type = "pci"; 635 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 636 reg = <0x001000 0 0 0 0>; 637 status = "disabled"; 638 639 #address-cells = <3>; 640 #size-cells = <2>; 641 ranges; 642 643 nvidia,num-lanes = <2>; 644 }; 645 }; 646 647 usb@c5000000 { 648 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 649 reg = <0xc5000000 0x4000>; 650 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 651 phy_type = "utmi"; 652 nvidia,has-legacy-mode; 653 clocks = <&tegra_car TEGRA20_CLK_USBD>; 654 resets = <&tegra_car 22>; 655 reset-names = "usb"; 656 nvidia,needs-double-reset; 657 nvidia,phy = <&phy1>; 658 status = "disabled"; 659 }; 660 661 phy1: usb-phy@c5000000 { 662 compatible = "nvidia,tegra20-usb-phy"; 663 reg = <0xc5000000 0x4000 0xc5000000 0x4000>; 664 phy_type = "utmi"; 665 clocks = <&tegra_car TEGRA20_CLK_USBD>, 666 <&tegra_car TEGRA20_CLK_PLL_U>, 667 <&tegra_car TEGRA20_CLK_CLK_M>, 668 <&tegra_car TEGRA20_CLK_USBD>; 669 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 670 resets = <&tegra_car 22>, <&tegra_car 22>; 671 reset-names = "usb", "utmi-pads"; 672 nvidia,has-legacy-mode; 673 nvidia,hssync-start-delay = <9>; 674 nvidia,idle-wait-delay = <17>; 675 nvidia,elastic-limit = <16>; 676 nvidia,term-range-adj = <6>; 677 nvidia,xcvr-setup = <9>; 678 nvidia,xcvr-lsfslew = <1>; 679 nvidia,xcvr-lsrslew = <1>; 680 nvidia,has-utmi-pad-registers; 681 status = "disabled"; 682 }; 683 684 usb@c5004000 { 685 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 686 reg = <0xc5004000 0x4000>; 687 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 688 phy_type = "ulpi"; 689 clocks = <&tegra_car TEGRA20_CLK_USB2>; 690 resets = <&tegra_car 58>; 691 reset-names = "usb"; 692 nvidia,phy = <&phy2>; 693 status = "disabled"; 694 }; 695 696 phy2: usb-phy@c5004000 { 697 compatible = "nvidia,tegra20-usb-phy"; 698 reg = <0xc5004000 0x4000>; 699 phy_type = "ulpi"; 700 clocks = <&tegra_car TEGRA20_CLK_USB2>, 701 <&tegra_car TEGRA20_CLK_PLL_U>, 702 <&tegra_car TEGRA20_CLK_CDEV2>; 703 clock-names = "reg", "pll_u", "ulpi-link"; 704 resets = <&tegra_car 58>, <&tegra_car 22>; 705 reset-names = "usb", "utmi-pads"; 706 status = "disabled"; 707 }; 708 709 usb@c5008000 { 710 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 711 reg = <0xc5008000 0x4000>; 712 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 713 phy_type = "utmi"; 714 clocks = <&tegra_car TEGRA20_CLK_USB3>; 715 resets = <&tegra_car 59>; 716 reset-names = "usb"; 717 nvidia,phy = <&phy3>; 718 status = "disabled"; 719 }; 720 721 phy3: usb-phy@c5008000 { 722 compatible = "nvidia,tegra20-usb-phy"; 723 reg = <0xc5008000 0x4000 0xc5000000 0x4000>; 724 phy_type = "utmi"; 725 clocks = <&tegra_car TEGRA20_CLK_USB3>, 726 <&tegra_car TEGRA20_CLK_PLL_U>, 727 <&tegra_car TEGRA20_CLK_CLK_M>, 728 <&tegra_car TEGRA20_CLK_USBD>; 729 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 730 resets = <&tegra_car 59>, <&tegra_car 22>; 731 reset-names = "usb", "utmi-pads"; 732 nvidia,hssync-start-delay = <9>; 733 nvidia,idle-wait-delay = <17>; 734 nvidia,elastic-limit = <16>; 735 nvidia,term-range-adj = <6>; 736 nvidia,xcvr-setup = <9>; 737 nvidia,xcvr-lsfslew = <2>; 738 nvidia,xcvr-lsrslew = <2>; 739 status = "disabled"; 740 }; 741 742 sdhci@c8000000 { 743 compatible = "nvidia,tegra20-sdhci"; 744 reg = <0xc8000000 0x200>; 745 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 747 resets = <&tegra_car 14>; 748 reset-names = "sdhci"; 749 status = "disabled"; 750 }; 751 752 sdhci@c8000200 { 753 compatible = "nvidia,tegra20-sdhci"; 754 reg = <0xc8000200 0x200>; 755 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 757 resets = <&tegra_car 9>; 758 reset-names = "sdhci"; 759 status = "disabled"; 760 }; 761 762 sdhci@c8000400 { 763 compatible = "nvidia,tegra20-sdhci"; 764 reg = <0xc8000400 0x200>; 765 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 767 resets = <&tegra_car 69>; 768 reset-names = "sdhci"; 769 status = "disabled"; 770 }; 771 772 sdhci@c8000600 { 773 compatible = "nvidia,tegra20-sdhci"; 774 reg = <0xc8000600 0x200>; 775 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 777 resets = <&tegra_car 15>; 778 reset-names = "sdhci"; 779 status = "disabled"; 780 }; 781 782 cpus { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 786 cpu@0 { 787 device_type = "cpu"; 788 compatible = "arm,cortex-a9"; 789 reg = <0>; 790 }; 791 792 cpu@1 { 793 device_type = "cpu"; 794 compatible = "arm,cortex-a9"; 795 reg = <1>; 796 }; 797 }; 798 799 pmu { 800 compatible = "arm,cortex-a9-pmu"; 801 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 803 }; 804}; 805