xref: /openbmc/u-boot/arch/arm/dts/tegra20.dtsi (revision b7723f3f) 
1/include/ "skeleton.dtsi"
2
3/ {
4	compatible = "nvidia,tegra20";
5	interrupt-parent = <&intc>;
6
7	host1x {
8		compatible = "nvidia,tegra20-host1x", "simple-bus";
9		reg = <0x50000000 0x00024000>;
10		interrupts = <0 65 0x04   /* mpcore syncpt */
11			      0 67 0x04>; /* mpcore general */
12		status = "disabled";
13
14		#address-cells = <1>;
15		#size-cells = <1>;
16
17		ranges = <0x54000000 0x54000000 0x04000000>;
18
19		/* video-encoding/decoding */
20		mpe {
21			reg = <0x54040000 0x00040000>;
22			interrupts = <0 68 0x04>;
23			status = "disabled";
24		};
25
26		/* video input */
27		vi {
28			reg = <0x54080000 0x00040000>;
29			interrupts = <0 69 0x04>;
30			status = "disabled";
31		};
32
33		/* EPP */
34		epp {
35			reg = <0x540c0000 0x00040000>;
36			interrupts = <0 70 0x04>;
37			status = "disabled";
38		};
39
40		/* ISP */
41		isp {
42			reg = <0x54100000 0x00040000>;
43			interrupts = <0 71 0x04>;
44			status = "disabled";
45		};
46
47		/* 2D engine */
48		gr2d {
49			reg = <0x54140000 0x00040000>;
50			interrupts = <0 72 0x04>;
51			status = "disabled";
52		};
53
54		/* 3D engine */
55		gr3d {
56			reg = <0x54180000 0x00040000>;
57			status = "disabled";
58		};
59
60		/* display controllers */
61		dc@54200000 {
62			compatible = "nvidia,tegra20-dc";
63			reg = <0x54200000 0x00040000>;
64			interrupts = <0 73 0x04>;
65			status = "disabled";
66
67			rgb {
68				status = "disabled";
69			};
70		};
71
72		dc@54240000 {
73			compatible = "nvidia,tegra20-dc";
74			reg = <0x54240000 0x00040000>;
75			interrupts = <0 74 0x04>;
76			status = "disabled";
77
78			rgb {
79				status = "disabled";
80			};
81		};
82
83		/* outputs */
84		hdmi {
85			compatible = "nvidia,tegra20-hdmi";
86			reg = <0x54280000 0x00040000>;
87			interrupts = <0 75 0x04>;
88			status = "disabled";
89		};
90
91		tvo {
92			compatible = "nvidia,tegra20-tvo";
93			reg = <0x542c0000 0x00040000>;
94			interrupts = <0 76 0x04>;
95			status = "disabled";
96		};
97
98		dsi {
99			compatible = "nvidia,tegra20-dsi";
100			reg = <0x54300000 0x00040000>;
101			status = "disabled";
102		};
103	};
104
105	intc: interrupt-controller@50041000 {
106		compatible = "nvidia,tegra20-gic";
107		interrupt-controller;
108		#interrupt-cells = <1>;
109		reg = < 0x50041000 0x1000 >,
110		      < 0x50040100 0x0100 >;
111	};
112
113	tegra_car: clock@60006000 {
114		compatible = "nvidia,tegra20-car";
115		reg = <0x60006000 0x1000>;
116		#clock-cells = <1>;
117	};
118
119	gpio: gpio@6000d000 {
120		compatible = "nvidia,tegra20-gpio";
121		reg = < 0x6000d000 0x1000 >;
122		interrupts = < 64 65 66 67 87 119 121 >;
123		#gpio-cells = <2>;
124		gpio-controller;
125	};
126
127	pinmux: pinmux@70000000 {
128		compatible = "nvidia,tegra20-pinmux";
129		reg = < 0x70000014 0x10    /* Tri-state registers */
130			0x70000080 0x20    /* Mux registers */
131			0x700000a0 0x14    /* Pull-up/down registers */
132			0x70000868 0xa8 >; /* Pad control registers */
133	};
134
135	das@70000c00 {
136		#address-cells = <1>;
137		#size-cells = <0>;
138		compatible = "nvidia,tegra20-das";
139		reg = <0x70000c00 0x80>;
140	};
141
142	i2s@70002800 {
143		#address-cells = <1>;
144		#size-cells = <0>;
145		compatible = "nvidia,tegra20-i2s";
146		reg = <0x70002800 0x200>;
147		interrupts = < 45 >;
148		dma-channel = < 2 >;
149	};
150
151	i2s@70002a00 {
152		#address-cells = <1>;
153		#size-cells = <0>;
154		compatible = "nvidia,tegra20-i2s";
155		reg = <0x70002a00 0x200>;
156		interrupts = < 35 >;
157		dma-channel = < 1 >;
158	};
159
160	serial@70006000 {
161		compatible = "nvidia,tegra20-uart";
162		reg = <0x70006000 0x40>;
163		reg-shift = <2>;
164		interrupts = < 68 >;
165	};
166
167	serial@70006040 {
168		compatible = "nvidia,tegra20-uart";
169		reg = <0x70006040 0x40>;
170		reg-shift = <2>;
171		interrupts = < 69 >;
172	};
173
174	serial@70006200 {
175		compatible = "nvidia,tegra20-uart";
176		reg = <0x70006200 0x100>;
177		reg-shift = <2>;
178		interrupts = < 78 >;
179	};
180
181	serial@70006300 {
182		compatible = "nvidia,tegra20-uart";
183		reg = <0x70006300 0x100>;
184		reg-shift = <2>;
185		interrupts = < 122 >;
186	};
187
188	serial@70006400 {
189		compatible = "nvidia,tegra20-uart";
190		reg = <0x70006400 0x100>;
191		reg-shift = <2>;
192		interrupts = < 123 >;
193	};
194
195	nand: nand-controller@70008000 {
196		#address-cells = <1>;
197		#size-cells = <0>;
198		compatible = "nvidia,tegra20-nand";
199		reg = <0x70008000 0x100>;
200	};
201
202	pwm: pwm@7000a000 {
203		compatible = "nvidia,tegra20-pwm";
204		reg = <0x7000a000 0x100>;
205		#pwm-cells = <2>;
206	};
207
208	i2c@7000c000 {
209		#address-cells = <1>;
210		#size-cells = <0>;
211		compatible = "nvidia,tegra20-i2c";
212		reg = <0x7000C000 0x100>;
213		interrupts = < 70 >;
214		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
215		clocks = <&tegra_car 12>, <&tegra_car 124>;
216	};
217
218	i2c@7000c400 {
219		#address-cells = <1>;
220		#size-cells = <0>;
221		compatible = "nvidia,tegra20-i2c";
222		reg = <0x7000C400 0x100>;
223		interrupts = < 116 >;
224		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
225		clocks = <&tegra_car 54>, <&tegra_car 124>;
226	};
227
228	i2c@7000c500 {
229		#address-cells = <1>;
230		#size-cells = <0>;
231		compatible = "nvidia,tegra20-i2c";
232		reg = <0x7000C500 0x100>;
233		interrupts = < 124 >;
234		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
235		clocks = <&tegra_car 67>, <&tegra_car 124>;
236	};
237
238	i2c@7000d000 {
239		#address-cells = <1>;
240		#size-cells = <0>;
241		compatible = "nvidia,tegra20-i2c-dvc";
242		reg = <0x7000D000 0x200>;
243		interrupts = < 85 >;
244		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
245		clocks = <&tegra_car 47>, <&tegra_car 124>;
246	};
247
248	kbc@7000e200 {
249		compatible = "nvidia,tegra20-kbc";
250		reg = <0x7000e200 0x0078>;
251	};
252
253	emc@7000f400 {
254		#address-cells = < 1 >;
255		#size-cells = < 0 >;
256		compatible = "nvidia,tegra20-emc";
257		reg = <0x7000f400 0x200>;
258	};
259
260	usb@c5000000 {
261		compatible = "nvidia,tegra20-ehci", "usb-ehci";
262		reg = <0xc5000000 0x4000>;
263		interrupts = < 52 >;
264		phy_type = "utmi";
265		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
266		nvidia,has-legacy-mode;
267	};
268
269	usb@c5004000 {
270		compatible = "nvidia,tegra20-ehci", "usb-ehci";
271		reg = <0xc5004000 0x4000>;
272		interrupts = < 53 >;
273		phy_type = "ulpi";
274		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
275	};
276
277	usb@c5008000 {
278		compatible = "nvidia,tegra20-ehci", "usb-ehci";
279		reg = <0xc5008000 0x4000>;
280		interrupts = < 129 >;
281		phy_type = "utmi";
282		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
283	};
284
285	sdhci@c8000000 {
286		compatible = "nvidia,tegra20-sdhci";
287		reg = <0xc8000000 0x200>;
288		interrupts = < 46 >;
289	};
290
291	sdhci@c8000200 {
292		compatible = "nvidia,tegra20-sdhci";
293		reg = <0xc8000200 0x200>;
294		interrupts = < 47 >;
295	};
296
297	sdhci@c8000400 {
298		compatible = "nvidia,tegra20-sdhci";
299		reg = <0xc8000400 0x200>;
300		interrupts = < 51 >;
301	};
302
303	sdhci@c8000600 {
304		compatible = "nvidia,tegra20-sdhci";
305		reg = <0xc8000600 0x200>;
306		interrupts = < 63 >;
307	};
308};
309