1/include/ "skeleton.dtsi" 2 3/ { 4 compatible = "nvidia,tegra20"; 5 interrupt-parent = <&intc>; 6 7 tegra_car: clock@60006000 { 8 compatible = "nvidia,tegra20-car"; 9 reg = <0x60006000 0x1000>; 10 #clock-cells = <1>; 11 }; 12 13 clocks { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 osc: clock { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 }; 21 }; 22 23 intc: interrupt-controller@50041000 { 24 compatible = "nvidia,tegra20-gic"; 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 reg = < 0x50041000 0x1000 >, 28 < 0x50040100 0x0100 >; 29 }; 30 31 i2c@7000c000 { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 compatible = "nvidia,tegra20-i2c"; 35 reg = <0x7000C000 0x100>; 36 interrupts = < 70 >; 37 }; 38 39 i2c@7000c400 { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 compatible = "nvidia,tegra20-i2c"; 43 reg = <0x7000C400 0x100>; 44 interrupts = < 116 >; 45 }; 46 47 i2c@7000c500 { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 compatible = "nvidia,tegra20-i2c"; 51 reg = <0x7000C500 0x100>; 52 interrupts = < 124 >; 53 }; 54 55 i2c@7000d000 { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 compatible = "nvidia,tegra20-i2c"; 59 reg = <0x7000D000 0x200>; 60 interrupts = < 85 >; 61 }; 62 63 i2s@70002800 { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 compatible = "nvidia,tegra20-i2s"; 67 reg = <0x70002800 0x200>; 68 interrupts = < 45 >; 69 dma-channel = < 2 >; 70 }; 71 72 i2s@70002a00 { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 compatible = "nvidia,tegra20-i2s"; 76 reg = <0x70002a00 0x200>; 77 interrupts = < 35 >; 78 dma-channel = < 1 >; 79 }; 80 81 das@70000c00 { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 compatible = "nvidia,tegra20-das"; 85 reg = <0x70000c00 0x80>; 86 }; 87 88 gpio: gpio@6000d000 { 89 compatible = "nvidia,tegra20-gpio"; 90 reg = < 0x6000d000 0x1000 >; 91 interrupts = < 64 65 66 67 87 119 121 >; 92 #gpio-cells = <2>; 93 gpio-controller; 94 }; 95 96 pinmux: pinmux@70000000 { 97 compatible = "nvidia,tegra20-pinmux"; 98 reg = < 0x70000014 0x10 /* Tri-state registers */ 99 0x70000080 0x20 /* Mux registers */ 100 0x700000a0 0x14 /* Pull-up/down registers */ 101 0x70000868 0xa8 >; /* Pad control registers */ 102 }; 103 104 serial@70006000 { 105 compatible = "nvidia,tegra20-uart"; 106 reg = <0x70006000 0x40>; 107 reg-shift = <2>; 108 interrupts = < 68 >; 109 }; 110 111 serial@70006040 { 112 compatible = "nvidia,tegra20-uart"; 113 reg = <0x70006040 0x40>; 114 reg-shift = <2>; 115 interrupts = < 69 >; 116 }; 117 118 serial@70006200 { 119 compatible = "nvidia,tegra20-uart"; 120 reg = <0x70006200 0x100>; 121 reg-shift = <2>; 122 interrupts = < 78 >; 123 }; 124 125 serial@70006300 { 126 compatible = "nvidia,tegra20-uart"; 127 reg = <0x70006300 0x100>; 128 reg-shift = <2>; 129 interrupts = < 122 >; 130 }; 131 132 serial@70006400 { 133 compatible = "nvidia,tegra20-uart"; 134 reg = <0x70006400 0x100>; 135 reg-shift = <2>; 136 interrupts = < 123 >; 137 }; 138 139 sdhci@c8000000 { 140 compatible = "nvidia,tegra20-sdhci"; 141 reg = <0xc8000000 0x200>; 142 interrupts = < 46 >; 143 }; 144 145 sdhci@c8000200 { 146 compatible = "nvidia,tegra20-sdhci"; 147 reg = <0xc8000200 0x200>; 148 interrupts = < 47 >; 149 }; 150 151 sdhci@c8000400 { 152 compatible = "nvidia,tegra20-sdhci"; 153 reg = <0xc8000400 0x200>; 154 interrupts = < 51 >; 155 }; 156 157 sdhci@c8000600 { 158 compatible = "nvidia,tegra20-sdhci"; 159 reg = <0xc8000600 0x200>; 160 interrupts = < 63 >; 161 }; 162 163 usb@c5000000 { 164 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 165 reg = <0xc5000000 0x4000>; 166 interrupts = < 52 >; 167 phy_type = "utmi"; 168 }; 169 170 usb@c5004000 { 171 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 172 reg = <0xc5004000 0x4000>; 173 interrupts = < 53 >; 174 phy_type = "ulpi"; 175 }; 176 177 usb@c5008000 { 178 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 179 reg = <0xc5008000 0x4000>; 180 interrupts = < 129 >; 181 phy_type = "utmi"; 182 }; 183 184}; 185