1/dts-v1/; 2 3#include "tegra20.dtsi" 4 5/ { 6 model = "NVIDIA Seaboard"; 7 compatible = "nvidia,seaboard", "nvidia,tegra20"; 8 9 chosen { 10 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; 11 }; 12 13 chosen { 14 stdout-path = &uartd; 15 }; 16 17 aliases { 18 /* This defines the order of our ports */ 19 usb0 = "/usb@c5008000"; 20 usb1 = "/usb@c5000000"; 21 i2c0 = "/i2c@7000d000"; 22 i2c1 = "/i2c@7000c000"; 23 i2c2 = "/i2c@7000c400"; 24 i2c3 = "/i2c@7000c500"; 25 sdhci0 = "/sdhci@c8000600"; 26 sdhci1 = "/sdhci@c8000400"; 27 }; 28 29 memory { 30 device_type = "memory"; 31 reg = < 0x00000000 0x40000000 >; 32 }; 33 34 host1x@50000000 { 35 status = "okay"; 36 dc@54200000 { 37 status = "okay"; 38 rgb { 39 status = "okay"; 40 nvidia,panel = <&lcd_panel>; 41 }; 42 }; 43 }; 44 45 /* This is not used in U-Boot, but is expected to be in kernel .dts */ 46 i2c@7000d000 { 47 status = "okay"; 48 clock-frequency = <100000>; 49 pmic@34 { 50 compatible = "ti,tps6586x"; 51 reg = <0x34>; 52 53 clk_32k: clock { 54 compatible = "fixed-clock"; 55 /* 56 * leave out for now due to CPP: 57 * #clock-cells = <0>; 58 */ 59 clock-frequency = <32768>; 60 }; 61 }; 62 }; 63 64 serial@70006300 { 65 clock-frequency = < 216000000 >; 66 }; 67 68 nand-controller@70008000 { 69 nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 70 nvidia,width = <8>; 71 nvidia,timing = <26 100 20 80 20 10 12 10 70>; 72 nand@0 { 73 reg = <0>; 74 compatible = "hynix,hy27uf4g2b", "nand-flash"; 75 }; 76 }; 77 78 i2c@7000c000 { 79 status = "okay"; 80 clock-frequency = <100000>; 81 }; 82 83 i2c@7000c400 { 84 status = "okay"; 85 }; 86 87 i2c@7000c500 { 88 status = "okay"; 89 clock-frequency = <100000>; 90 }; 91 92 kbc@7000e200 { 93 status = "okay"; 94 linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c 95 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 96 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 97 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023 98 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a 99 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031 100 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018 101 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032 102 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036 103 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019 104 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044 105 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067 106 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068 107 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057 108 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d 109 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f 110 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040 111 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f 112 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050 113 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053 114 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072 115 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071 116 0x1f04008a>; 117 linux,fn-keymap = <0x05040002>; 118 }; 119 120 emc@7000f400 { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 emc-table@190000 { 124 reg = < 190000 >; 125 compatible = "nvidia,tegra20-emc-table"; 126 clock-frequency = < 190000 >; 127 nvidia,emc-registers = < 0x0000000c 0x00000026 128 0x00000009 0x00000003 0x00000004 0x00000004 129 0x00000002 0x0000000c 0x00000003 0x00000003 130 0x00000002 0x00000001 0x00000004 0x00000005 131 0x00000004 0x00000009 0x0000000d 0x0000059f 132 0x00000000 0x00000003 0x00000003 0x00000003 133 0x00000003 0x00000001 0x0000000b 0x000000c8 134 0x00000003 0x00000007 0x00000004 0x0000000f 135 0x00000002 0x00000000 0x00000000 0x00000002 136 0x00000000 0x00000000 0x00000083 0xa06204ae 137 0x007dc010 0x00000000 0x00000000 0x00000000 138 0x00000000 0x00000000 0x00000000 0x00000000 >; 139 }; 140 emc-table@380000 { 141 reg = < 380000 >; 142 compatible = "nvidia,tegra20-emc-table"; 143 clock-frequency = < 380000 >; 144 nvidia,emc-registers = < 0x00000017 0x0000004b 145 0x00000012 0x00000006 0x00000004 0x00000005 146 0x00000003 0x0000000c 0x00000006 0x00000006 147 0x00000003 0x00000001 0x00000004 0x00000005 148 0x00000004 0x00000009 0x0000000d 0x00000b5f 149 0x00000000 0x00000003 0x00000003 0x00000006 150 0x00000006 0x00000001 0x00000011 0x000000c8 151 0x00000003 0x0000000e 0x00000007 0x0000000f 152 0x00000002 0x00000000 0x00000000 0x00000002 153 0x00000000 0x00000000 0x00000083 0xe044048b 154 0x007d8010 0x00000000 0x00000000 0x00000000 155 0x00000000 0x00000000 0x00000000 0x00000000 >; 156 }; 157 }; 158 159 usb@c5000000 { 160 status = "okay"; 161 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; 162 dr_mode = "otg"; 163 }; 164 165 usb@c5004000 { 166 status = "disabled"; 167 }; 168 169 usb@c5008000 { 170 status = "okay"; 171 }; 172 173 sdhci@c8000400 { 174 status = "okay"; 175 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 176 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 177 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 178 bus-width = <4>; 179 }; 180 181 sdhci@c8000600 { 182 status = "okay"; 183 bus-width = <8>; 184 }; 185 186 clocks { 187 compatible = "simple-bus"; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 clk32k_in: clock@0 { 192 compatible = "fixed-clock"; 193 reg=<0>; 194 #clock-cells = <0>; 195 clock-frequency = <32768>; 196 }; 197 }; 198 199 pwm: pwm@7000a000 { 200 status = "okay"; 201 }; 202 203 lcd_panel: panel { 204 /* Seaboard has 1366x768 */ 205 clock = <70600000>; 206 xres = <1366>; 207 yres = <768>; 208 left-margin = <58>; 209 right-margin = <58>; 210 hsync-len = <58>; 211 lower-margin = <4>; 212 upper-margin = <4>; 213 vsync-len = <4>; 214 hsync-active-high; 215 nvidia,bits-per-pixel = <16>; 216 nvidia,pwm = <&pwm 2 0>; 217 nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) 218 GPIO_ACTIVE_HIGH>; 219 nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) 220 GPIO_ACTIVE_HIGH>; 221 nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) 222 GPIO_ACTIVE_HIGH>; 223 nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) 224 GPIO_ACTIVE_HIGH>; 225 nvidia,panel-timings = <400 4 203 17 15>; 226 }; 227}; 228