1#include "skeleton.dtsi" 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8 9/ { 10 compatible = "nvidia,tegra186"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 gpio_main: gpio@2200000 { 16 compatible = "nvidia,tegra186-gpio"; 17 reg-names = "security", "gpio"; 18 reg = 19 <0x0 0x2200000 0x0 0x10000>, 20 <0x0 0x2210000 0x0 0x10000>; 21 interrupts = 22 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 28 gpio-controller; 29 #gpio-cells = <2>; 30 interrupt-controller; 31 #interrupt-cells = <2>; 32 }; 33 34 ethernet@2490000 { 35 compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; 36 reg = <0x0 0x02490000 0x0 0x10000>; 37 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 39 <&bpmp TEGRA186_CLK_EQOS_AXI>, 40 <&bpmp TEGRA186_CLK_EQOS_RX>, 41 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>, 42 <&bpmp TEGRA186_CLK_EQOS_TX>; 43 clock-names = "slave_bus", 44 "master_bus", 45 "rx", 46 "ptp_ref", 47 "tx"; 48 resets = <&bpmp TEGRA186_RESET_EQOS>; 49 reset-names = "eqos"; 50 phy-mode = "rgmii"; 51 status = "disabled"; 52 }; 53 54 uarta: serial@3100000 { 55 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 56 reg = <0x0 0x03100000 0x0 0x10000>; 57 reg-shift = <2>; 58 status = "disabled"; 59 }; 60 61 gen1_i2c: i2c@3160000 { 62 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 63 reg = <0x0 0x3160000 0x0 0x100>; 64 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 clocks = <&bpmp TEGRA186_CLK_I2C1>; 68 clock-names = "div-clk"; 69 resets = <&bpmp TEGRA186_RESET_I2C1>; 70 reset-names = "i2c"; 71 status = "disabled"; 72 }; 73 74 cam_i2c: i2c@3180000 { 75 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 76 reg = <0x0 0x3180000 0x0 0x100>; 77 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 clocks = <&bpmp TEGRA186_CLK_I2C3>; 81 clock-names = "div-clk"; 82 resets = <&bpmp TEGRA186_RESET_I2C3>; 83 reset-names = "i2c"; 84 status = "disabled"; 85 }; 86 87 dp_aux_ch1_i2c: i2c@3190000 { 88 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 89 reg = <0x0 0x3190000 0x0 0x100>; 90 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 clocks = <&bpmp TEGRA186_CLK_I2C4>; 94 clock-names = "div-clk"; 95 resets = <&bpmp TEGRA186_RESET_I2C4>; 96 reset-names = "i2c"; 97 status = "disabled"; 98 }; 99 100 dp_aux_ch0_i2c: i2c@31b0000 { 101 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 102 reg = <0x0 0x31b0000 0x0 0x100>; 103 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 clocks = <&bpmp TEGRA186_CLK_I2C6>; 107 clock-names = "div-clk"; 108 resets = <&bpmp TEGRA186_RESET_I2C6>; 109 reset-names = "i2c"; 110 status = "disabled"; 111 }; 112 113 gen7_i2c: i2c@31c0000 { 114 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 115 reg = <0x0 0x31c0000 0x0 0x100>; 116 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 clocks = <&bpmp TEGRA186_CLK_I2C7>; 120 clock-names = "div-clk"; 121 resets = <&bpmp TEGRA186_RESET_I2C7>; 122 reset-names = "i2c"; 123 status = "disabled"; 124 }; 125 126 gen9_i2c: i2c@31e0000 { 127 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 128 reg = <0x0 0x31e0000 0x0 0x100>; 129 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 clocks = <&bpmp TEGRA186_CLK_I2C9>; 133 clock-names = "div-clk"; 134 resets = <&bpmp TEGRA186_RESET_I2C9>; 135 reset-names = "i2c"; 136 status = "disabled"; 137 }; 138 139 sdhci@3400000 { 140 compatible = "nvidia,tegra186-sdhci"; 141 reg = <0x0 0x03400000 0x0 0x200>; 142 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 143 reset-names = "sdhci"; 144 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 145 interrupts = <GIC_SPI 62 0x04>; 146 status = "disabled"; 147 }; 148 149 sdhci@3460000 { 150 compatible = "nvidia,tegra186-sdhci"; 151 reg = <0x0 0x03460000 0x0 0x200>; 152 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 153 reset-names = "sdhci"; 154 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 155 interrupts = <GIC_SPI 31 0x04>; 156 status = "disabled"; 157 }; 158 159 gic: interrupt-controller@3881000 { 160 compatible = "arm,gic-400"; 161 #interrupt-cells = <3>; 162 interrupt-controller; 163 reg = <0x0 0x3881000 0x0 0x1000>, 164 <0x0 0x3882000 0x0 0x2000>, 165 <0x0 0x3884000 0x0 0x2000>, 166 <0x0 0x3886000 0x0 0x2000>; 167 interrupts = <GIC_PPI 9 168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 169 interrupt-parent = <&gic>; 170 }; 171 172 hsp: hsp@3c00000 { 173 compatible = "nvidia,tegra186-hsp"; 174 reg = <0x0 0x03c00000 0x0 0xa0000>; 175 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "doorbell"; 177 #mbox-cells = <2>; 178 }; 179 180 gen2_i2c: i2c@c240000 { 181 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 182 reg = <0x0 0xc240000 0x0 0x100>; 183 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 clocks = <&bpmp TEGRA186_CLK_I2C2>; 187 clock-names = "div-clk"; 188 resets = <&bpmp TEGRA186_RESET_I2C2>; 189 reset-names = "i2c"; 190 status = "disabled"; 191 }; 192 193 gen8_i2c: i2c@c250000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0xc250000 0x0 0x100>; 196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C8>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C8>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gpio_aon: gpio@c2f0000 { 207 compatible = "nvidia,tegra186-gpio-aon"; 208 reg-names = "security", "gpio"; 209 reg = 210 <0x0 0xc2f0000 0x0 0x1000>, 211 <0x0 0xc2f1000 0x0 0x1000>; 212 interrupts = 213 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 }; 219 220 pcie-controller@10003000 { 221 compatible = "nvidia,tegra186-pcie"; 222 device_type = "pci"; 223 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 224 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 225 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 226 reg-names = "pads", "afi", "cs"; 227 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 228 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ 229 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ 230 interrupt-names = "intr", "msi", "wake"; 231 232 #interrupt-cells = <1>; 233 interrupt-map-mask = <0 0 0 0>; 234 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 235 236 bus-range = <0x00 0xff>; 237 #address-cells = <3>; 238 #size-cells = <2>; 239 240 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 241 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 242 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 243 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 244 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 245 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 246 247 clocks = <&bpmp TEGRA186_CLK_PCIE>, 248 <&bpmp TEGRA186_CLK_AFI>; 249 clock-names = "pex", "afi"; 250 resets = <&bpmp TEGRA186_RESET_PCIE>, 251 <&bpmp TEGRA186_RESET_AFI>, 252 <&bpmp TEGRA186_RESET_PCIEXCLK>; 253 reset-names = "pex", "afi", "pcie_x"; 254 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 255 status = "disabled"; 256 257 pci@1,0 { 258 device_type = "pci"; 259 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 260 reg = <0x000800 0 0 0 0>; 261 status = "disabled"; 262 263 #address-cells = <3>; 264 #size-cells = <2>; 265 ranges; 266 267 nvidia,num-lanes = <2>; 268 }; 269 270 pci@2,0 { 271 device_type = "pci"; 272 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 273 reg = <0x001000 0 0 0 0>; 274 status = "disabled"; 275 276 #address-cells = <3>; 277 #size-cells = <2>; 278 ranges; 279 280 nvidia,num-lanes = <1>; 281 }; 282 283 pci@3,0 { 284 device_type = "pci"; 285 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 286 reg = <0x001800 0 0 0 0>; 287 status = "disabled"; 288 289 #address-cells = <3>; 290 #size-cells = <2>; 291 ranges; 292 293 nvidia,num-lanes = <1>; 294 }; 295 }; 296 297 sysram@30000000 { 298 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 299 reg = <0x0 0x30000000 0x0 0x50000>; 300 #address-cells = <2>; 301 #size-cells = <2>; 302 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 303 304 sysram_cpu_bpmp_tx: shmem@4e000 { 305 compatible = "nvidia,tegra186-bpmp-shmem"; 306 reg = <0x0 0x4e000 0x0 0x1000>; 307 }; 308 309 sysram_cpu_bpmp_rx: shmem@4f000 { 310 compatible = "nvidia,tegra186-bpmp-shmem"; 311 reg = <0x0 0x4f000 0x0 0x1000>; 312 }; 313 }; 314 315 bpmp: bpmp { 316 compatible = "nvidia,tegra186-bpmp"; 317 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 318 /* 319 * In theory, these references, and the configuration in the 320 * node these reference point at, are board-specific, since 321 * they depend on the BCT's memory carve-out setup, the 322 * firmware that's actually loaded onto the BPMP, etc. However, 323 * in practice, all boards are likely to use identical values. 324 */ 325 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; 326 #clock-cells = <1>; 327 #power-domain-cells = <1>; 328 #reset-cells = <1>; 329 330 bpmp_i2c: i2c { 331 compatible = "nvidia,tegra186-bpmp-i2c"; 332 nvidia,bpmp-bus-id = <5>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 status = "disabled"; 336 }; 337 }; 338}; 339