1#include "skeleton.dtsi" 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8 9/ { 10 compatible = "nvidia,tegra186"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 gpio_main: gpio@2200000 { 16 compatible = "nvidia,tegra186-gpio"; 17 reg-names = "security", "gpio"; 18 reg = 19 <0x0 0x2200000 0x0 0x10000>, 20 <0x0 0x2210000 0x0 0x10000>; 21 interrupts = 22 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 28 gpio-controller; 29 #gpio-cells = <2>; 30 interrupt-controller; 31 #interrupt-cells = <2>; 32 }; 33 34 uarta: serial@3100000 { 35 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 36 reg = <0x0 0x03100000 0x0 0x10000>; 37 reg-shift = <2>; 38 status = "disabled"; 39 }; 40 41 gen1_i2c: i2c@3160000 { 42 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 43 reg = <0x0 0x3160000 0x0 0x100>; 44 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 clocks = <&bpmp TEGRA186_CLK_I2C1>; 48 clock-names = "div-clk"; 49 resets = <&bpmp TEGRA186_RESET_I2C1>; 50 reset-names = "i2c"; 51 status = "disabled"; 52 }; 53 54 cam_i2c: i2c@3180000 { 55 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 56 reg = <0x0 0x3180000 0x0 0x100>; 57 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 clocks = <&bpmp TEGRA186_CLK_I2C3>; 61 clock-names = "div-clk"; 62 resets = <&bpmp TEGRA186_RESET_I2C3>; 63 reset-names = "i2c"; 64 status = "disabled"; 65 }; 66 67 dp_aux_ch1_i2c: i2c@3190000 { 68 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 69 reg = <0x0 0x3190000 0x0 0x100>; 70 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 clocks = <&bpmp TEGRA186_CLK_I2C4>; 74 clock-names = "div-clk"; 75 resets = <&bpmp TEGRA186_RESET_I2C4>; 76 reset-names = "i2c"; 77 status = "disabled"; 78 }; 79 80 dp_aux_ch0_i2c: i2c@31b0000 { 81 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 82 reg = <0x0 0x31b0000 0x0 0x100>; 83 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 clocks = <&bpmp TEGRA186_CLK_I2C6>; 87 clock-names = "div-clk"; 88 resets = <&bpmp TEGRA186_RESET_I2C6>; 89 reset-names = "i2c"; 90 status = "disabled"; 91 }; 92 93 gen7_i2c: i2c@31c0000 { 94 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 95 reg = <0x0 0x31c0000 0x0 0x100>; 96 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 clocks = <&bpmp TEGRA186_CLK_I2C7>; 100 clock-names = "div-clk"; 101 resets = <&bpmp TEGRA186_RESET_I2C7>; 102 reset-names = "i2c"; 103 status = "disabled"; 104 }; 105 106 gen9_i2c: i2c@31e0000 { 107 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 108 reg = <0x0 0x31e0000 0x0 0x100>; 109 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clocks = <&bpmp TEGRA186_CLK_I2C9>; 113 clock-names = "div-clk"; 114 resets = <&bpmp TEGRA186_RESET_I2C9>; 115 reset-names = "i2c"; 116 status = "disabled"; 117 }; 118 119 sdhci@3400000 { 120 compatible = "nvidia,tegra186-sdhci"; 121 reg = <0x0 0x03400000 0x0 0x200>; 122 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 123 reset-names = "sdhci"; 124 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 125 interrupts = <GIC_SPI 62 0x04>; 126 status = "disabled"; 127 }; 128 129 sdhci@3460000 { 130 compatible = "nvidia,tegra186-sdhci"; 131 reg = <0x0 0x03460000 0x0 0x200>; 132 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 133 reset-names = "sdhci"; 134 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 135 interrupts = <GIC_SPI 31 0x04>; 136 status = "disabled"; 137 }; 138 139 gic: interrupt-controller@3881000 { 140 compatible = "arm,gic-400"; 141 #interrupt-cells = <3>; 142 interrupt-controller; 143 reg = <0x0 0x3881000 0x0 0x1000>, 144 <0x0 0x3882000 0x0 0x2000>, 145 <0x0 0x3884000 0x0 0x2000>, 146 <0x0 0x3886000 0x0 0x2000>; 147 interrupts = <GIC_PPI 9 148 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 149 interrupt-parent = <&gic>; 150 }; 151 152 hsp: hsp@3c00000 { 153 compatible = "nvidia,tegra186-hsp"; 154 reg = <0x0 0x03c00000 0x0 0xa0000>; 155 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "doorbell"; 157 #mbox-cells = <2>; 158 }; 159 160 gen2_i2c: i2c@c240000 { 161 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 162 reg = <0x0 0xc240000 0x0 0x100>; 163 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clocks = <&bpmp TEGRA186_CLK_I2C2>; 167 clock-names = "div-clk"; 168 resets = <&bpmp TEGRA186_RESET_I2C2>; 169 reset-names = "i2c"; 170 status = "disabled"; 171 }; 172 173 gen8_i2c: i2c@c250000 { 174 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 175 reg = <0x0 0xc250000 0x0 0x100>; 176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 clocks = <&bpmp TEGRA186_CLK_I2C8>; 180 clock-names = "div-clk"; 181 resets = <&bpmp TEGRA186_RESET_I2C8>; 182 reset-names = "i2c"; 183 status = "disabled"; 184 }; 185 186 gpio_aon: gpio@c2f0000 { 187 compatible = "nvidia,tegra186-gpio-aon"; 188 reg-names = "security", "gpio"; 189 reg = 190 <0x0 0xc2f0000 0x0 0x1000>, 191 <0x0 0xc2f1000 0x0 0x1000>; 192 interrupts = 193 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 }; 199 200 pcie-controller@10003000 { 201 compatible = "nvidia,tegra186-pcie"; 202 device_type = "pci"; 203 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 204 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 205 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 206 reg-names = "pads", "afi", "cs"; 207 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 208 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ 209 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ 210 interrupt-names = "intr", "msi", "wake"; 211 212 #interrupt-cells = <1>; 213 interrupt-map-mask = <0 0 0 0>; 214 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 215 216 bus-range = <0x00 0xff>; 217 #address-cells = <3>; 218 #size-cells = <2>; 219 220 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 221 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 222 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 223 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 224 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 225 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 226 227 clocks = <&bpmp TEGRA186_CLK_PCIE>, 228 <&bpmp TEGRA186_CLK_AFI>; 229 clock-names = "pex", "afi"; 230 resets = <&bpmp TEGRA186_RESET_PCIE>, 231 <&bpmp TEGRA186_RESET_AFI>, 232 <&bpmp TEGRA186_RESET_PCIEXCLK>; 233 reset-names = "pex", "afi", "pcie_x"; 234 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 235 status = "disabled"; 236 237 pci@1,0 { 238 device_type = "pci"; 239 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 240 reg = <0x000800 0 0 0 0>; 241 status = "disabled"; 242 243 #address-cells = <3>; 244 #size-cells = <2>; 245 ranges; 246 247 nvidia,num-lanes = <2>; 248 }; 249 250 pci@2,0 { 251 device_type = "pci"; 252 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 253 reg = <0x001000 0 0 0 0>; 254 status = "disabled"; 255 256 #address-cells = <3>; 257 #size-cells = <2>; 258 ranges; 259 260 nvidia,num-lanes = <1>; 261 }; 262 263 pci@3,0 { 264 device_type = "pci"; 265 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 266 reg = <0x001800 0 0 0 0>; 267 status = "disabled"; 268 269 #address-cells = <3>; 270 #size-cells = <2>; 271 ranges; 272 273 nvidia,num-lanes = <1>; 274 }; 275 }; 276 277 sysram@30000000 { 278 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 279 reg = <0x0 0x30000000 0x0 0x50000>; 280 #address-cells = <2>; 281 #size-cells = <2>; 282 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 283 284 sysram_cpu_bpmp_tx: shmem@4e000 { 285 compatible = "nvidia,tegra186-bpmp-shmem"; 286 reg = <0x0 0x4e000 0x0 0x1000>; 287 }; 288 289 sysram_cpu_bpmp_rx: shmem@4f000 { 290 compatible = "nvidia,tegra186-bpmp-shmem"; 291 reg = <0x0 0x4f000 0x0 0x1000>; 292 }; 293 }; 294 295 bpmp: bpmp { 296 compatible = "nvidia,tegra186-bpmp"; 297 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 298 /* 299 * In theory, these references, and the configuration in the 300 * node these reference point at, are board-specific, since 301 * they depend on the BCT's memory carve-out setup, the 302 * firmware that's actually loaded onto the BPMP, etc. However, 303 * in practice, all boards are likely to use identical values. 304 */ 305 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; 306 #clock-cells = <1>; 307 #power-domain-cells = <1>; 308 #reset-cells = <1>; 309 310 bpmp_i2c: i2c { 311 compatible = "nvidia,tegra186-bpmp-i2c"; 312 nvidia,bpmp-bus-id = <5>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 }; 318}; 319