1#include "skeleton.dtsi" 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/power/tegra186-powergate.h> 7#include <dt-bindings/reset/tegra186-reset.h> 8 9/ { 10 compatible = "nvidia,tegra186"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 gpio_main: gpio@2200000 { 16 compatible = "nvidia,tegra186-gpio"; 17 reg-names = "security", "gpio"; 18 reg = 19 <0x0 0x2200000 0x0 0x10000>, 20 <0x0 0x2210000 0x0 0x10000>; 21 interrupts = 22 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 28 gpio-controller; 29 #gpio-cells = <2>; 30 interrupt-controller; 31 #interrupt-cells = <2>; 32 }; 33 34 uarta: serial@3100000 { 35 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 36 reg = <0x0 0x03100000 0x0 0x10000>; 37 reg-shift = <2>; 38 status = "disabled"; 39 }; 40 41 gen1_i2c: i2c@3160000 { 42 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 43 reg = <0x0 0x3160000 0x0 0x100>; 44 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 clocks = <&bpmp TEGRA186_CLK_I2C1>; 48 clock-names = "i2c"; 49 resets = <&bpmp TEGRA186_RESET_I2C1>; 50 reset-names = "i2c"; 51 status = "disabled"; 52 }; 53 54 cam_i2c: i2c@3180000 { 55 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 56 reg = <0x0 0x3180000 0x0 0x100>; 57 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 clocks = <&bpmp TEGRA186_CLK_I2C3>; 61 clock-names = "i2c"; 62 resets = <&bpmp TEGRA186_RESET_I2C3>; 63 reset-names = "i2c"; 64 status = "disabled"; 65 }; 66 67 dp_aux_ch1_i2c: i2c@3190000 { 68 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 69 reg = <0x0 0x3190000 0x0 0x100>; 70 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 71 #address-cells = <1>; 72 #size-cells = <0>; 73 clocks = <&bpmp TEGRA186_CLK_I2C4>; 74 clock-names = "i2c"; 75 resets = <&bpmp TEGRA186_RESET_I2C4>; 76 reset-names = "i2c"; 77 status = "disabled"; 78 }; 79 80 dp_aux_ch0_i2c: i2c@31b0000 { 81 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 82 reg = <0x0 0x31b0000 0x0 0x100>; 83 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 clocks = <&bpmp TEGRA186_CLK_I2C6>; 87 clock-names = "i2c"; 88 resets = <&bpmp TEGRA186_RESET_I2C6>; 89 reset-names = "i2c"; 90 status = "disabled"; 91 }; 92 93 gen7_i2c: i2c@31c0000 { 94 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 95 reg = <0x0 0x31c0000 0x0 0x100>; 96 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 clocks = <&bpmp TEGRA186_CLK_I2C7>; 100 clock-names = "i2c"; 101 resets = <&bpmp TEGRA186_RESET_I2C7>; 102 reset-names = "i2c"; 103 status = "disabled"; 104 }; 105 106 gen9_i2c: i2c@31e0000 { 107 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 108 reg = <0x0 0x31e0000 0x0 0x100>; 109 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clocks = <&bpmp TEGRA186_CLK_I2C9>; 113 clock-names = "i2c"; 114 resets = <&bpmp TEGRA186_RESET_I2C9>; 115 reset-names = "i2c"; 116 status = "disabled"; 117 }; 118 119 sdhci@3400000 { 120 compatible = "nvidia,tegra186-sdhci"; 121 reg = <0x0 0x03400000 0x0 0x200>; 122 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 123 reset-names = "sdmmc"; 124 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 125 clock-names = "sdmmc"; 126 interrupts = <GIC_SPI 62 0x04>; 127 status = "disabled"; 128 }; 129 130 sdhci@3460000 { 131 compatible = "nvidia,tegra186-sdhci"; 132 reg = <0x0 0x03460000 0x0 0x200>; 133 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 134 reset-names = "sdmmc"; 135 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 136 clock-names = "sdmmc"; 137 interrupts = <GIC_SPI 31 0x04>; 138 status = "disabled"; 139 }; 140 141 gic: interrupt-controller@3881000 { 142 compatible = "arm,gic-400"; 143 #interrupt-cells = <3>; 144 interrupt-controller; 145 reg = <0x0 0x3881000 0x0 0x1000>, 146 <0x0 0x3882000 0x0 0x2000>, 147 <0x0 0x3884000 0x0 0x2000>, 148 <0x0 0x3886000 0x0 0x2000>; 149 interrupts = <GIC_PPI 9 150 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 interrupt-parent = <&gic>; 152 }; 153 154 hsp: hsp@3c00000 { 155 compatible = "nvidia,tegra186-hsp"; 156 reg = <0x0 0x03c00000 0x0 0xa0000>; 157 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "doorbell"; 159 #mbox-cells = <2>; 160 }; 161 162 gen2_i2c: i2c@c240000 { 163 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 164 reg = <0x0 0xc240000 0x0 0x100>; 165 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 clocks = <&bpmp TEGRA186_CLK_I2C2>; 169 clock-names = "i2c"; 170 resets = <&bpmp TEGRA186_RESET_I2C2>; 171 reset-names = "i2c"; 172 status = "disabled"; 173 }; 174 175 gen8_i2c: i2c@c250000 { 176 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 177 reg = <0x0 0xc250000 0x0 0x100>; 178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 clocks = <&bpmp TEGRA186_CLK_I2C8>; 182 clock-names = "i2c"; 183 resets = <&bpmp TEGRA186_RESET_I2C8>; 184 reset-names = "i2c"; 185 status = "disabled"; 186 }; 187 188 gpio_aon: gpio@c2f0000 { 189 compatible = "nvidia,tegra186-gpio-aon"; 190 reg-names = "security", "gpio"; 191 reg = 192 <0x0 0xc2f0000 0x0 0x1000>, 193 <0x0 0xc2f1000 0x0 0x1000>; 194 interrupts = 195 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 202 pcie-controller@10003000 { 203 compatible = "nvidia,tegra186-pcie"; 204 device_type = "pci"; 205 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 206 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 207 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 208 reg-names = "pads", "afi", "cs"; 209 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 210 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ 211 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ 212 interrupt-names = "intr", "msi", "wake"; 213 214 #interrupt-cells = <1>; 215 interrupt-map-mask = <0 0 0 0>; 216 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 217 218 bus-range = <0x00 0xff>; 219 #address-cells = <3>; 220 #size-cells = <2>; 221 222 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 223 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 224 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 225 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 226 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 227 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 228 229 clocks = <&bpmp TEGRA186_CLK_PCIE>, 230 <&bpmp TEGRA186_CLK_AFI>; 231 clock-names = "pex", "afi"; 232 resets = <&bpmp TEGRA186_RESET_PCIE>, 233 <&bpmp TEGRA186_RESET_AFI>, 234 <&bpmp TEGRA186_RESET_PCIEXCLK>; 235 reset-names = "pex", "afi", "pcie_x"; 236 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 237 status = "disabled"; 238 239 pci@1,0 { 240 device_type = "pci"; 241 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 242 reg = <0x000800 0 0 0 0>; 243 status = "disabled"; 244 245 #address-cells = <3>; 246 #size-cells = <2>; 247 ranges; 248 249 nvidia,num-lanes = <2>; 250 }; 251 252 pci@2,0 { 253 device_type = "pci"; 254 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 255 reg = <0x001000 0 0 0 0>; 256 status = "disabled"; 257 258 #address-cells = <3>; 259 #size-cells = <2>; 260 ranges; 261 262 nvidia,num-lanes = <1>; 263 }; 264 265 pci@3,0 { 266 device_type = "pci"; 267 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 268 reg = <0x001800 0 0 0 0>; 269 status = "disabled"; 270 271 #address-cells = <3>; 272 #size-cells = <2>; 273 ranges; 274 275 nvidia,num-lanes = <1>; 276 }; 277 }; 278 279 sysram@30000000 { 280 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 281 reg = <0x0 0x30000000 0x0 0x50000>; 282 #address-cells = <2>; 283 #size-cells = <2>; 284 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 285 286 sysram_cpu_bpmp_tx: shmem@4e000 { 287 compatible = "nvidia,tegra186-bpmp-shmem"; 288 reg = <0x0 0x4e000 0x0 0x1000>; 289 }; 290 291 sysram_cpu_bpmp_rx: shmem@4f000 { 292 compatible = "nvidia,tegra186-bpmp-shmem"; 293 reg = <0x0 0x4f000 0x0 0x1000>; 294 }; 295 }; 296 297 bpmp: bpmp { 298 compatible = "nvidia,tegra186-bpmp"; 299 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 300 /* 301 * In theory, these references, and the configuration in the 302 * node these reference point at, are board-specific, since 303 * they depend on the BCT's memory carve-out setup, the 304 * firmware that's actually loaded onto the BPMP, etc. However, 305 * in practice, all boards are likely to use identical values. 306 */ 307 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; 308 #clock-cells = <1>; 309 #power-domain-cells = <1>; 310 #reset-cells = <1>; 311 312 bpmp_i2c: i2c { 313 compatible = "nvidia,tegra186-bpmp-i2c"; 314 nvidia,bpmp = <&bpmp>; 315 nvidia,bpmp-bus-id = <5>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 }; 321}; 322