11f60f073SStephen Warren#include "tegra186.dtsi" 21f60f073SStephen Warren 31f60f073SStephen Warren/ { 41f60f073SStephen Warren model = "NVIDIA P2771-0000"; 51f60f073SStephen Warren compatible = "nvidia,p2771-0000", "nvidia,tegra186"; 61f60f073SStephen Warren 71f60f073SStephen Warren chosen { 81f60f073SStephen Warren stdout-path = &uarta; 91f60f073SStephen Warren }; 101f60f073SStephen Warren 111f60f073SStephen Warren aliases { 121f60f073SStephen Warren sdhci0 = "/sdhci@3460000"; 13*ad3c144fSBryan Wu i2c1 = "/i2c@3160000"; 14*ad3c144fSBryan Wu i2c2 = "/i2c@c240000"; 15*ad3c144fSBryan Wu i2c3 = "/i2c@3180000"; 16*ad3c144fSBryan Wu i2c4 = "/i2c@3190000"; 17*ad3c144fSBryan Wu i2c5 = "/i2c@31c0000"; 18*ad3c144fSBryan Wu i2c6 = "/i2c@c250000"; 19*ad3c144fSBryan Wu i2c7 = "/i2c@31e0000"; 201f60f073SStephen Warren }; 211f60f073SStephen Warren 221f60f073SStephen Warren memory { 231f60f073SStephen Warren reg = <0x0 0x80000000 0x0 0x60000000>; 241f60f073SStephen Warren }; 251f60f073SStephen Warren 26*ad3c144fSBryan Wu i2c@3160000 { 27*ad3c144fSBryan Wu status = "okay"; 28*ad3c144fSBryan Wu }; 29*ad3c144fSBryan Wu 30*ad3c144fSBryan Wu i2c@3180000 { 31*ad3c144fSBryan Wu status = "okay"; 32*ad3c144fSBryan Wu }; 33*ad3c144fSBryan Wu 34*ad3c144fSBryan Wu i2c@3190000 { 35*ad3c144fSBryan Wu status = "okay"; 36*ad3c144fSBryan Wu }; 37*ad3c144fSBryan Wu 38*ad3c144fSBryan Wu i2c@31c0000 { 39*ad3c144fSBryan Wu status = "okay"; 40*ad3c144fSBryan Wu }; 41*ad3c144fSBryan Wu 421f60f073SStephen Warren sdhci@3460000 { 431f60f073SStephen Warren status = "okay"; 441f60f073SStephen Warren bus-width = <8>; 451f60f073SStephen Warren }; 46*ad3c144fSBryan Wu 47*ad3c144fSBryan Wu i2c@c240000 { 48*ad3c144fSBryan Wu status = "okay"; 49*ad3c144fSBryan Wu }; 50*ad3c144fSBryan Wu 51*ad3c144fSBryan Wu i2c@c250000 { 52*ad3c144fSBryan Wu status = "okay"; 53*ad3c144fSBryan Wu }; 54*ad3c144fSBryan Wu 55*ad3c144fSBryan Wu i2c@31e0000 { 56*ad3c144fSBryan Wu status = "okay"; 57*ad3c144fSBryan Wu }; 581f60f073SStephen Warren}; 59