1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 6 7#include "skeleton.dtsi" 8 9/ { 10 compatible = "nvidia,tegra124"; 11 interrupt-parent = <&gic>; 12 13 pcie-controller@01003000 { 14 compatible = "nvidia,tegra124-pcie"; 15 device_type = "pci"; 16 reg = <0x01003000 0x00000800 /* PADS registers */ 17 0x01003800 0x00000800 /* AFI registers */ 18 0x02000000 0x10000000>; /* configuration space */ 19 reg-names = "pads", "afi", "cs"; 20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22 interrupt-names = "intr", "msi"; 23 24 #interrupt-cells = <1>; 25 interrupt-map-mask = <0 0 0 0>; 26 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 27 28 bus-range = <0x00 0xff>; 29 #address-cells = <3>; 30 #size-cells = <2>; 31 32 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */ 33 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */ 34 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 35 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 36 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 37 38 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 39 <&tegra_car TEGRA124_CLK_AFI>, 40 <&tegra_car TEGRA124_CLK_PLL_E>, 41 <&tegra_car TEGRA124_CLK_CML0>; 42 clock-names = "pex", "afi", "pll_e", "cml"; 43 resets = <&tegra_car 70>, 44 <&tegra_car 72>, 45 <&tegra_car 74>; 46 reset-names = "pex", "afi", "pcie_x"; 47 status = "disabled"; 48 49 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 50 phy-names = "pcie"; 51 52 pci@1,0 { 53 device_type = "pci"; 54 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 55 reg = <0x000800 0 0 0 0>; 56 status = "disabled"; 57 58 #address-cells = <3>; 59 #size-cells = <2>; 60 ranges; 61 62 nvidia,num-lanes = <2>; 63 }; 64 65 pci@2,0 { 66 device_type = "pci"; 67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 68 reg = <0x001000 0 0 0 0>; 69 status = "disabled"; 70 71 #address-cells = <3>; 72 #size-cells = <2>; 73 ranges; 74 75 nvidia,num-lanes = <1>; 76 }; 77 }; 78 79 gic: interrupt-controller@50041000 { 80 compatible = "arm,cortex-a15-gic"; 81 #interrupt-cells = <3>; 82 interrupt-controller; 83 reg = <0x50041000 0x1000>, 84 <0x50042000 0x2000>, 85 <0x50044000 0x2000>, 86 <0x50046000 0x2000>; 87 interrupts = <GIC_PPI 9 88 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 89 }; 90 91 tegra_car: clock@60006000 { 92 compatible = "nvidia,tegra124-car"; 93 reg = <0x60006000 0x1000>; 94 #clock-cells = <1>; 95 }; 96 97 apbdma: dma@60020000 { 98 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 99 reg = <0x60020000 0x1400>; 100 interrupts = <0 104 0x04 101 0 105 0x04 102 0 106 0x04 103 0 107 0x04 104 0 108 0x04 105 0 109 0x04 106 0 110 0x04 107 0 111 0x04 108 0 112 0x04 109 0 113 0x04 110 0 114 0x04 111 0 115 0x04 112 0 116 0x04 113 0 117 0x04 114 0 118 0x04 115 0 119 0x04 116 0 128 0x04 117 0 129 0x04 118 0 130 0x04 119 0 131 0x04 120 0 132 0x04 121 0 133 0x04 122 0 134 0x04 123 0 135 0x04 124 0 136 0x04 125 0 137 0x04 126 0 138 0x04 127 0 139 0x04 128 0 140 0x04 129 0 141 0x04 130 0 142 0x04 131 0 143 0x04>; 132 }; 133 134 gpio: gpio@6000d000 { 135 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 136 reg = <0x6000d000 0x1000>; 137 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 145 #gpio-cells = <2>; 146 gpio-controller; 147 #interrupt-cells = <2>; 148 interrupt-controller; 149 }; 150 151 i2c@7000c000 { 152 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x7000c000 0x100>; 154 interrupts = <0 38 0x04>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&tegra_car 12>; 158 status = "disabled"; 159 }; 160 161 i2c@7000c400 { 162 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 163 reg = <0x7000c400 0x100>; 164 interrupts = <0 84 0x04>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&tegra_car 54>; 168 status = "disabled"; 169 }; 170 171 i2c@7000c500 { 172 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 173 reg = <0x7000c500 0x100>; 174 interrupts = <0 92 0x04>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clocks = <&tegra_car 67>; 178 status = "disabled"; 179 }; 180 181 i2c@7000c700 { 182 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 183 reg = <0x7000c700 0x100>; 184 interrupts = <0 120 0x04>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 clocks = <&tegra_car 103>; 188 status = "disabled"; 189 }; 190 191 i2c@7000d000 { 192 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 193 reg = <0x7000d000 0x100>; 194 interrupts = <0 53 0x04>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 clocks = <&tegra_car 47>; 198 status = "disabled"; 199 }; 200 201 i2c@7000d100 { 202 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 203 reg = <0x7000d100 0x100>; 204 interrupts = <0 53 0x04>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&tegra_car 47>; 208 status = "disabled"; 209 }; 210 211 uarta: serial@70006000 { 212 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 213 reg = <0x70006000 0x40>; 214 reg-shift = <2>; 215 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 217 resets = <&tegra_car 6>; 218 reset-names = "serial"; 219 dmas = <&apbdma 8>, <&apbdma 8>; 220 dma-names = "rx", "tx"; 221 status = "disabled"; 222 }; 223 224 uartb: serial@70006040 { 225 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 226 reg = <0x70006040 0x40>; 227 reg-shift = <2>; 228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 230 resets = <&tegra_car 7>; 231 reset-names = "serial"; 232 dmas = <&apbdma 9>, <&apbdma 9>; 233 dma-names = "rx", "tx"; 234 status = "disabled"; 235 }; 236 237 uartc: serial@70006200 { 238 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 239 reg = <0x70006200 0x40>; 240 reg-shift = <2>; 241 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 243 resets = <&tegra_car 55>; 244 reset-names = "serial"; 245 dmas = <&apbdma 10>, <&apbdma 10>; 246 dma-names = "rx", "tx"; 247 status = "disabled"; 248 }; 249 250 uartd: serial@70006300 { 251 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 252 reg = <0x70006300 0x40>; 253 reg-shift = <2>; 254 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 256 resets = <&tegra_car 65>; 257 reset-names = "serial"; 258 dmas = <&apbdma 19>, <&apbdma 19>; 259 dma-names = "rx", "tx"; 260 status = "disabled"; 261 }; 262 263 uarte: serial@70006400 { 264 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 265 reg = <0x70006400 0x40>; 266 reg-shift = <2>; 267 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 269 resets = <&tegra_car 66>; 270 reset-names = "serial"; 271 dmas = <&apbdma 20>, <&apbdma 20>; 272 dma-names = "rx", "tx"; 273 status = "disabled"; 274 }; 275 276 pwm: pwm@7000a000 { 277 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 278 reg = <0x7000a000 0x100>; 279 #pwm-cells = <2>; 280 clocks = <&tegra_car TEGRA124_CLK_PWM>; 281 resets = <&tegra_car 17>; 282 reset-names = "pwm"; 283 status = "disabled"; 284 }; 285 286 spi@7000d400 { 287 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 288 reg = <0x7000d400 0x200>; 289 interrupts = <0 59 0x04>; 290 nvidia,dma-request-selector = <&apbdma 15>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 clocks = <&tegra_car 41>; 295 }; 296 297 spi@7000d600 { 298 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 299 reg = <0x7000d600 0x200>; 300 interrupts = <0 82 0x04>; 301 nvidia,dma-request-selector = <&apbdma 16>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 status = "disabled"; 305 clocks = <&tegra_car 44>; 306 }; 307 308 spi@7000d800 { 309 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 310 reg = <0x7000d800 0x200>; 311 interrupts = <0 83 0x04>; 312 nvidia,dma-request-selector = <&apbdma 17>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 clocks = <&tegra_car 46>; 317 }; 318 319 spi@7000da00 { 320 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 321 reg = <0x7000da00 0x200>; 322 interrupts = <0 93 0x04>; 323 nvidia,dma-request-selector = <&apbdma 18>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 status = "disabled"; 327 clocks = <&tegra_car 68>; 328 }; 329 330 spi@7000dc00 { 331 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 332 reg = <0x7000dc00 0x200>; 333 interrupts = <0 94 0x04>; 334 nvidia,dma-request-selector = <&apbdma 27>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 clocks = <&tegra_car 104>; 339 }; 340 341 spi@7000de00 { 342 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 343 reg = <0x7000de00 0x200>; 344 interrupts = <0 79 0x04>; 345 nvidia,dma-request-selector = <&apbdma 28>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 clocks = <&tegra_car 105>; 350 }; 351 352 padctl: padctl@7009f000 { 353 compatible = "nvidia,tegra124-xusb-padctl"; 354 reg = <0x7009f000 0x1000>; 355 resets = <&tegra_car 142>; 356 reset-names = "padctl"; 357 358 #phy-cells = <1>; 359 }; 360 361 sdhci@700b0000 { 362 compatible = "nvidia,tegra124-sdhci"; 363 reg = <0x700b0000 0x200>; 364 interrupts = <0 14 0x04>; 365 clocks = <&tegra_car 14>; 366 status = "disabled"; 367 }; 368 369 sdhci@700b0200 { 370 compatible = "nvidia,tegra124-sdhci"; 371 reg = <0x700b0200 0x200>; 372 interrupts = <0 15 0x04>; 373 clocks = <&tegra_car 9>; 374 status = "disabled"; 375 }; 376 377 sdhci@700b0400 { 378 compatible = "nvidia,tegra124-sdhci"; 379 reg = <0x700b0400 0x200>; 380 interrupts = <0 19 0x04>; 381 clocks = <&tegra_car 69>; 382 status = "disabled"; 383 }; 384 385 sdhci@700b0600 { 386 compatible = "nvidia,tegra124-sdhci"; 387 reg = <0x700b0600 0x200>; 388 interrupts = <0 31 0x04>; 389 clocks = <&tegra_car 15>; 390 status = "disabled"; 391 }; 392 393 ahub@70300000 { 394 compatible = "nvidia,tegra124-ahub"; 395 reg = <0x70300000 0x200>, 396 <0x70300800 0x800>, 397 <0x70300200 0x600>; 398 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 400 <&tegra_car TEGRA124_CLK_APBIF>; 401 clock-names = "d_audio", "apbif"; 402 resets = <&tegra_car 106>, /* d_audio */ 403 <&tegra_car 107>, /* apbif */ 404 <&tegra_car 30>, /* i2s0 */ 405 <&tegra_car 11>, /* i2s1 */ 406 <&tegra_car 18>, /* i2s2 */ 407 <&tegra_car 101>, /* i2s3 */ 408 <&tegra_car 102>, /* i2s4 */ 409 <&tegra_car 108>, /* dam0 */ 410 <&tegra_car 109>, /* dam1 */ 411 <&tegra_car 110>, /* dam2 */ 412 <&tegra_car 10>, /* spdif */ 413 <&tegra_car 153>, /* amx */ 414 <&tegra_car 185>, /* amx1 */ 415 <&tegra_car 154>, /* adx */ 416 <&tegra_car 180>, /* adx1 */ 417 <&tegra_car 186>, /* afc0 */ 418 <&tegra_car 187>, /* afc1 */ 419 <&tegra_car 188>, /* afc2 */ 420 <&tegra_car 189>, /* afc3 */ 421 <&tegra_car 190>, /* afc4 */ 422 <&tegra_car 191>; /* afc5 */ 423 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 424 "i2s3", "i2s4", "dam0", "dam1", "dam2", 425 "spdif", "amx", "amx1", "adx", "adx1", 426 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 427 dmas = <&apbdma 1>, <&apbdma 1>, 428 <&apbdma 2>, <&apbdma 2>, 429 <&apbdma 3>, <&apbdma 3>, 430 <&apbdma 4>, <&apbdma 4>, 431 <&apbdma 6>, <&apbdma 6>, 432 <&apbdma 7>, <&apbdma 7>, 433 <&apbdma 12>, <&apbdma 12>, 434 <&apbdma 13>, <&apbdma 13>, 435 <&apbdma 14>, <&apbdma 14>, 436 <&apbdma 29>, <&apbdma 29>; 437 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 438 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 439 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 440 "rx9", "tx9"; 441 ranges; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 445 tegra_i2s0: i2s@70301000 { 446 compatible = "nvidia,tegra124-i2s"; 447 reg = <0x70301000 0x100>; 448 nvidia,ahub-cif-ids = <4 4>; 449 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 450 resets = <&tegra_car 30>; 451 reset-names = "i2s"; 452 status = "disabled"; 453 }; 454 455 tegra_i2s1: i2s@70301100 { 456 compatible = "nvidia,tegra124-i2s"; 457 reg = <0x70301100 0x100>; 458 nvidia,ahub-cif-ids = <5 5>; 459 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 460 resets = <&tegra_car 11>; 461 reset-names = "i2s"; 462 status = "disabled"; 463 }; 464 465 tegra_i2s2: i2s@70301200 { 466 compatible = "nvidia,tegra124-i2s"; 467 reg = <0x70301200 0x100>; 468 nvidia,ahub-cif-ids = <6 6>; 469 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 470 resets = <&tegra_car 18>; 471 reset-names = "i2s"; 472 status = "disabled"; 473 }; 474 475 tegra_i2s3: i2s@70301300 { 476 compatible = "nvidia,tegra124-i2s"; 477 reg = <0x70301300 0x100>; 478 nvidia,ahub-cif-ids = <7 7>; 479 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 480 resets = <&tegra_car 101>; 481 reset-names = "i2s"; 482 status = "disabled"; 483 }; 484 485 tegra_i2s4: i2s@70301400 { 486 compatible = "nvidia,tegra124-i2s"; 487 reg = <0x70301400 0x100>; 488 nvidia,ahub-cif-ids = <8 8>; 489 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 490 resets = <&tegra_car 102>; 491 reset-names = "i2s"; 492 status = "disabled"; 493 }; 494 }; 495 496 usb@7d000000 { 497 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 498 reg = <0x7d000000 0x4000>; 499 interrupts = < 52 >; 500 phy_type = "utmi"; 501 clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ 502 status = "disabled"; 503 }; 504 505 usb@7d004000 { 506 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 507 reg = <0x7d004000 0x4000>; 508 interrupts = < 53 >; 509 phy_type = "hsic"; 510 clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ 511 status = "disabled"; 512 }; 513 514 usb@7d008000 { 515 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 516 reg = <0x7d008000 0x4000>; 517 interrupts = < 129 >; 518 phy_type = "utmi"; 519 clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ 520 status = "disabled"; 521 }; 522}; 523