1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra124-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "nvidia,tegra124"; 14 interrupt-parent = <&lic>; 15 16 17 pcie-controller@01003000 { 18 compatible = "nvidia,tegra124-pcie"; 19 device_type = "pci"; 20 reg = <0x01003000 0x00000800 /* PADS registers */ 21 0x01003800 0x00000800 /* AFI registers */ 22 0x02000000 0x10000000>; /* configuration space */ 23 reg-names = "pads", "afi", "cs"; 24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26 interrupt-names = "intr", "msi"; 27 28 #interrupt-cells = <1>; 29 interrupt-map-mask = <0 0 0 0>; 30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 31 32 bus-range = <0x00 0xff>; 33 #address-cells = <3>; 34 #size-cells = <2>; 35 36 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */ 37 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */ 38 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 39 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 40 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 41 42 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 43 <&tegra_car TEGRA124_CLK_AFI>, 44 <&tegra_car TEGRA124_CLK_PLL_E>, 45 <&tegra_car TEGRA124_CLK_CML0>; 46 clock-names = "pex", "afi", "pll_e", "cml"; 47 resets = <&tegra_car 70>, 48 <&tegra_car 72>, 49 <&tegra_car 74>; 50 reset-names = "pex", "afi", "pcie_x"; 51 status = "disabled"; 52 53 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 54 phy-names = "pcie"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 status = "disabled"; 61 62 #address-cells = <3>; 63 #size-cells = <2>; 64 ranges; 65 66 nvidia,num-lanes = <2>; 67 }; 68 69 pci@2,0 { 70 device_type = "pci"; 71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 72 reg = <0x001000 0 0 0 0>; 73 status = "disabled"; 74 75 #address-cells = <3>; 76 #size-cells = <2>; 77 ranges; 78 79 nvidia,num-lanes = <1>; 80 }; 81 }; 82 83 host1x@50000000 { 84 compatible = "nvidia,tegra124-host1x", "simple-bus"; 85 reg = <0x50000000 0x00034000>; 86 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 87 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 88 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 89 resets = <&tegra_car 28>; 90 reset-names = "host1x"; 91 92 #address-cells = <1>; 93 #size-cells = <1>; 94 95 ranges = <0x54000000 0x54000000 0x01000000>; 96 97 dc@54200000 { 98 compatible = "nvidia,tegra124-dc"; 99 reg = <0x54200000 0x00040000>; 100 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 102 <&tegra_car TEGRA124_CLK_PLL_P>; 103 clock-names = "dc", "parent"; 104 resets = <&tegra_car 27>; 105 reset-names = "dc"; 106 107 iommus = <&mc TEGRA_SWGROUP_DC>; 108 109 nvidia,head = <0>; 110 }; 111 112 dc@54240000 { 113 compatible = "nvidia,tegra124-dc"; 114 reg = <0x54240000 0x00040000>; 115 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 117 <&tegra_car TEGRA124_CLK_PLL_P>; 118 clock-names = "dc", "parent"; 119 resets = <&tegra_car 26>; 120 reset-names = "dc"; 121 122 iommus = <&mc TEGRA_SWGROUP_DCB>; 123 124 nvidia,head = <1>; 125 }; 126 127 hdmi@54280000 { 128 compatible = "nvidia,tegra124-hdmi"; 129 reg = <0x54280000 0x00040000>; 130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 132 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 133 clock-names = "hdmi", "parent"; 134 resets = <&tegra_car 51>; 135 reset-names = "hdmi"; 136 status = "disabled"; 137 }; 138 139 sor@54540000 { 140 compatible = "nvidia,tegra124-sor"; 141 reg = <0x54540000 0x00040000>; 142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 144 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 145 <&tegra_car TEGRA124_CLK_PLL_DP>, 146 <&tegra_car TEGRA124_CLK_CLK_M>; 147 clock-names = "sor", "parent", "dp", "safe"; 148 resets = <&tegra_car 182>; 149 reset-names = "sor"; 150 status = "disabled"; 151 }; 152 153 dpaux: dpaux@545c0000 { 154 compatible = "nvidia,tegra124-dpaux"; 155 reg = <0x545c0000 0x00040000>; 156 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 158 <&tegra_car TEGRA124_CLK_PLL_DP>; 159 clock-names = "dpaux", "parent"; 160 resets = <&tegra_car 181>; 161 reset-names = "dpaux"; 162 status = "disabled"; 163 }; 164 }; 165 166 gic: interrupt-controller@50041000 { 167 compatible = "arm,cortex-a15-gic"; 168 #interrupt-cells = <3>; 169 interrupt-controller; 170 reg = <0x50041000 0x1000>, 171 <0x50042000 0x2000>, 172 <0x50044000 0x2000>, 173 <0x50046000 0x2000>; 174 interrupts = <GIC_PPI 9 175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 176 interrupt-parent = <&gic>; 177 }; 178 179 gpu@57000000 { 180 compatible = "nvidia,gk20a"; 181 reg = <0x57000000 0x01000000>, 182 <0x58000000 0x01000000>; 183 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "stall", "nonstall"; 186 clocks = <&tegra_car TEGRA124_CLK_GPU>, 187 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 188 clock-names = "gpu", "pwr"; 189 resets = <&tegra_car 184>; 190 reset-names = "gpu"; 191 192 iommus = <&mc TEGRA_SWGROUP_GPU>; 193 194 status = "disabled"; 195 }; 196 197 lic: interrupt-controller@60004000 { 198 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 199 interrupt-controller; 200 #interrupt-cells = <3>; 201 interrupt-parent = <&gic>; 202 }; 203 204 timer@60005000 { 205 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 206 reg = <0x60005000 0x400>; 207 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 214 }; 215 216 tegra_car: clock@60006000 { 217 compatible = "nvidia,tegra124-car"; 218 reg = <0x60006000 0x1000>; 219 #clock-cells = <1>; 220 #reset-cells = <1>; 221 nvidia,external-memory-controller = <&emc>; 222 }; 223 224 flow-controller@60007000 { 225 compatible = "nvidia,tegra124-flowctrl"; 226 reg = <0x60007000 0x1000>; 227 }; 228 229 actmon@6000c800 { 230 compatible = "nvidia,tegra124-actmon"; 231 reg = <0x6000c800 0x400>; 232 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 234 <&tegra_car TEGRA124_CLK_EMC>; 235 clock-names = "actmon", "emc"; 236 resets = <&tegra_car 119>; 237 reset-names = "actmon"; 238 }; 239 240 gpio: gpio@6000d000 { 241 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 242 reg = <0x6000d000 0x1000>; 243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 251 #gpio-cells = <2>; 252 gpio-controller; 253 #interrupt-cells = <2>; 254 interrupt-controller; 255 /* 256 gpio-ranges = <&pinmux 0 0 251>; 257 */ 258 }; 259 260 apbdma: dma@60020000 { 261 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 262 reg = <0x60020000 0x1400>; 263 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 296 resets = <&tegra_car 34>; 297 reset-names = "dma"; 298 #dma-cells = <1>; 299 }; 300 301 apbmisc@70000800 { 302 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 303 reg = <0x70000800 0x64>, /* Chip revision */ 304 <0x7000e864 0x04>; /* Strapping options */ 305 }; 306 307 pinmux: pinmux@70000868 { 308 compatible = "nvidia,tegra124-pinmux"; 309 reg = <0x70000868 0x164>, /* Pad control registers */ 310 <0x70003000 0x434>, /* Mux registers */ 311 <0x70000820 0x008>; /* MIPI pad control */ 312 }; 313 314 /* 315 * There are two serial driver i.e. 8250 based simple serial 316 * driver and APB DMA based serial driver for higher baudrate 317 * and performace. To enable the 8250 based driver, the compatible 318 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 319 * the APB DMA based serial driver, the comptible is 320 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 321 */ 322 uarta: serial@70006000 { 323 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 324 reg = <0x70006000 0x40>; 325 reg-shift = <2>; 326 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 328 resets = <&tegra_car 6>; 329 reset-names = "serial"; 330 dmas = <&apbdma 8>, <&apbdma 8>; 331 dma-names = "rx", "tx"; 332 status = "disabled"; 333 }; 334 335 uartb: serial@70006040 { 336 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 337 reg = <0x70006040 0x40>; 338 reg-shift = <2>; 339 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 341 resets = <&tegra_car 7>; 342 reset-names = "serial"; 343 dmas = <&apbdma 9>, <&apbdma 9>; 344 dma-names = "rx", "tx"; 345 status = "disabled"; 346 }; 347 348 uartc: serial@70006200 { 349 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 350 reg = <0x70006200 0x40>; 351 reg-shift = <2>; 352 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 354 resets = <&tegra_car 55>; 355 reset-names = "serial"; 356 dmas = <&apbdma 10>, <&apbdma 10>; 357 dma-names = "rx", "tx"; 358 status = "disabled"; 359 }; 360 361 uartd: serial@70006300 { 362 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 363 reg = <0x70006300 0x40>; 364 reg-shift = <2>; 365 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 367 resets = <&tegra_car 65>; 368 reset-names = "serial"; 369 dmas = <&apbdma 19>, <&apbdma 19>; 370 dma-names = "rx", "tx"; 371 status = "disabled"; 372 }; 373 374 pwm: pwm@7000a000 { 375 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 376 reg = <0x7000a000 0x100>; 377 #pwm-cells = <2>; 378 clocks = <&tegra_car TEGRA124_CLK_PWM>; 379 resets = <&tegra_car 17>; 380 reset-names = "pwm"; 381 status = "disabled"; 382 }; 383 384 i2c@7000c000 { 385 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 386 reg = <0x7000c000 0x100>; 387 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 391 clock-names = "div-clk"; 392 resets = <&tegra_car 12>; 393 reset-names = "i2c"; 394 dmas = <&apbdma 21>, <&apbdma 21>; 395 dma-names = "rx", "tx"; 396 status = "disabled"; 397 }; 398 399 i2c@7000c400 { 400 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 401 reg = <0x7000c400 0x100>; 402 interrupts = <0 84 0x04>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&tegra_car 54>; 406 status = "disabled"; 407 }; 408 409 i2c@7000c500 { 410 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 411 reg = <0x7000c500 0x100>; 412 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 416 clock-names = "div-clk"; 417 resets = <&tegra_car 67>; 418 reset-names = "i2c"; 419 dmas = <&apbdma 23>, <&apbdma 23>; 420 dma-names = "rx", "tx"; 421 status = "disabled"; 422 }; 423 424 i2c@7000c700 { 425 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 426 reg = <0x7000c700 0x100>; 427 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 431 clock-names = "div-clk"; 432 resets = <&tegra_car 103>; 433 reset-names = "i2c"; 434 dmas = <&apbdma 26>, <&apbdma 26>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 i2c@7000d000 { 440 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 441 reg = <0x7000d000 0x100>; 442 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 446 clock-names = "div-clk"; 447 resets = <&tegra_car 47>; 448 reset-names = "i2c"; 449 dmas = <&apbdma 24>, <&apbdma 24>; 450 dma-names = "rx", "tx"; 451 status = "disabled"; 452 }; 453 454 i2c@7000d100 { 455 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 456 reg = <0x7000d100 0x100>; 457 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 461 clock-names = "div-clk"; 462 resets = <&tegra_car 166>; 463 reset-names = "i2c"; 464 dmas = <&apbdma 30>, <&apbdma 30>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 }; 468 469 spi@7000d400 { 470 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 471 reg = <0x7000d400 0x200>; 472 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 476 clock-names = "spi"; 477 resets = <&tegra_car 41>; 478 reset-names = "spi"; 479 dmas = <&apbdma 15>, <&apbdma 15>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 }; 483 484 spi@7000d600 { 485 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 486 reg = <0x7000d600 0x200>; 487 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 491 clock-names = "spi"; 492 resets = <&tegra_car 44>; 493 reset-names = "spi"; 494 dmas = <&apbdma 16>, <&apbdma 16>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 }; 498 499 spi@7000d800 { 500 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 501 reg = <0x7000d800 0x200>; 502 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 506 clock-names = "spi"; 507 resets = <&tegra_car 46>; 508 reset-names = "spi"; 509 dmas = <&apbdma 17>, <&apbdma 17>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 }; 513 514 spi@7000da00 { 515 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 516 reg = <0x7000da00 0x200>; 517 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 521 clock-names = "spi"; 522 resets = <&tegra_car 68>; 523 reset-names = "spi"; 524 dmas = <&apbdma 18>, <&apbdma 18>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 }; 528 529 spi@7000dc00 { 530 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 531 reg = <0x7000dc00 0x200>; 532 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 536 clock-names = "spi"; 537 resets = <&tegra_car 104>; 538 reset-names = "spi"; 539 dmas = <&apbdma 27>, <&apbdma 27>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 spi@7000de00 { 545 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 546 reg = <0x7000de00 0x200>; 547 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 551 clock-names = "spi"; 552 resets = <&tegra_car 105>; 553 reset-names = "spi"; 554 dmas = <&apbdma 28>, <&apbdma 28>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 }; 558 559 rtc@7000e000 { 560 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 561 reg = <0x7000e000 0x100>; 562 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&tegra_car TEGRA124_CLK_RTC>; 564 }; 565 566 pmc@7000e400 { 567 compatible = "nvidia,tegra124-pmc"; 568 reg = <0x7000e400 0x400>; 569 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 570 clock-names = "pclk", "clk32k_in"; 571 }; 572 573 fuse@7000f800 { 574 compatible = "nvidia,tegra124-efuse"; 575 reg = <0x7000f800 0x400>; 576 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 577 clock-names = "fuse"; 578 resets = <&tegra_car 39>; 579 reset-names = "fuse"; 580 }; 581 582 mc: memory-controller@70019000 { 583 compatible = "nvidia,tegra124-mc"; 584 reg = <0x70019000 0x1000>; 585 clocks = <&tegra_car TEGRA124_CLK_MC>; 586 clock-names = "mc"; 587 588 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 589 590 #iommu-cells = <1>; 591 }; 592 593 emc: emc@7001b000 { 594 compatible = "nvidia,tegra124-emc"; 595 reg = <0x7001b000 0x1000>; 596 597 nvidia,memory-controller = <&mc>; 598 }; 599 600 sata@70020000 { 601 compatible = "nvidia,tegra124-ahci"; 602 reg = <0x70027000 0x2000>, /* AHCI */ 603 <0x70020000 0x7000>; /* SATA */ 604 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&tegra_car TEGRA124_CLK_SATA>, 606 <&tegra_car TEGRA124_CLK_SATA_OOB>, 607 <&tegra_car TEGRA124_CLK_CML1>, 608 <&tegra_car TEGRA124_CLK_PLL_E>; 609 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 610 resets = <&tegra_car 124>, 611 <&tegra_car 123>, 612 <&tegra_car 129>; 613 reset-names = "sata", "sata-oob", "sata-cold"; 614 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 615 phy-names = "sata-phy"; 616 status = "disabled"; 617 }; 618 619 hda@70030000 { 620 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 621 reg = <0x70030000 0x10000>; 622 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&tegra_car TEGRA124_CLK_HDA>, 624 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 625 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 626 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 627 resets = <&tegra_car 125>, /* hda */ 628 <&tegra_car 128>, /* hda2hdmi */ 629 <&tegra_car 111>; /* hda2codec_2x */ 630 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 631 status = "disabled"; 632 }; 633 634 padctl: padctl@7009f000 { 635 compatible = "nvidia,tegra124-xusb-padctl"; 636 reg = <0x7009f000 0x1000>; 637 resets = <&tegra_car 142>; 638 reset-names = "padctl"; 639 640 #phy-cells = <1>; 641 }; 642 643 sdhci@700b0000 { 644 compatible = "nvidia,tegra124-sdhci"; 645 reg = <0x700b0000 0x200>; 646 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 648 resets = <&tegra_car 14>; 649 reset-names = "sdhci"; 650 status = "disabled"; 651 }; 652 653 sdhci@700b0200 { 654 compatible = "nvidia,tegra124-sdhci"; 655 reg = <0x700b0200 0x200>; 656 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 658 resets = <&tegra_car 9>; 659 reset-names = "sdhci"; 660 status = "disabled"; 661 }; 662 663 sdhci@700b0400 { 664 compatible = "nvidia,tegra124-sdhci"; 665 reg = <0x700b0400 0x200>; 666 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 668 resets = <&tegra_car 69>; 669 reset-names = "sdhci"; 670 status = "disabled"; 671 }; 672 673 sdhci@700b0600 { 674 compatible = "nvidia,tegra124-sdhci"; 675 reg = <0x700b0600 0x200>; 676 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 678 resets = <&tegra_car 15>; 679 reset-names = "sdhci"; 680 status = "disabled"; 681 }; 682 683 soctherm: thermal-sensor@700e2000 { 684 compatible = "nvidia,tegra124-soctherm"; 685 reg = <0x700e2000 0x1000>; 686 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 688 <&tegra_car TEGRA124_CLK_SOC_THERM>; 689 clock-names = "tsensor", "soctherm"; 690 resets = <&tegra_car 78>; 691 reset-names = "soctherm"; 692 #thermal-sensor-cells = <1>; 693 }; 694 695 dfll: clock@70110000 { 696 compatible = "nvidia,tegra124-dfll"; 697 reg = <0x70110000 0x100>, /* DFLL control */ 698 <0x70110000 0x100>, /* I2C output control */ 699 <0x70110100 0x100>, /* Integrated I2C controller */ 700 <0x70110200 0x100>; /* Look-up table RAM */ 701 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 703 <&tegra_car TEGRA124_CLK_DFLL_REF>, 704 <&tegra_car TEGRA124_CLK_I2C5>; 705 clock-names = "soc", "ref", "i2c"; 706 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 707 reset-names = "dvco"; 708 #clock-cells = <0>; 709 clock-output-names = "dfllCPU_out"; 710 nvidia,sample-rate = <12500>; 711 nvidia,droop-ctrl = <0x00000f00>; 712 nvidia,force-mode = <1>; 713 nvidia,cf = <10>; 714 nvidia,ci = <0>; 715 nvidia,cg = <2>; 716 status = "disabled"; 717 }; 718 719 ahub@70300000 { 720 compatible = "nvidia,tegra124-ahub"; 721 reg = <0x70300000 0x200>, 722 <0x70300800 0x800>, 723 <0x70300200 0x600>; 724 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 726 <&tegra_car TEGRA124_CLK_APBIF>; 727 clock-names = "d_audio", "apbif"; 728 resets = <&tegra_car 106>, /* d_audio */ 729 <&tegra_car 107>, /* apbif */ 730 <&tegra_car 30>, /* i2s0 */ 731 <&tegra_car 11>, /* i2s1 */ 732 <&tegra_car 18>, /* i2s2 */ 733 <&tegra_car 101>, /* i2s3 */ 734 <&tegra_car 102>, /* i2s4 */ 735 <&tegra_car 108>, /* dam0 */ 736 <&tegra_car 109>, /* dam1 */ 737 <&tegra_car 110>, /* dam2 */ 738 <&tegra_car 10>, /* spdif */ 739 <&tegra_car 153>, /* amx */ 740 <&tegra_car 185>, /* amx1 */ 741 <&tegra_car 154>, /* adx */ 742 <&tegra_car 180>, /* adx1 */ 743 <&tegra_car 186>, /* afc0 */ 744 <&tegra_car 187>, /* afc1 */ 745 <&tegra_car 188>, /* afc2 */ 746 <&tegra_car 189>, /* afc3 */ 747 <&tegra_car 190>, /* afc4 */ 748 <&tegra_car 191>; /* afc5 */ 749 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 750 "i2s3", "i2s4", "dam0", "dam1", "dam2", 751 "spdif", "amx", "amx1", "adx", "adx1", 752 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 753 dmas = <&apbdma 1>, <&apbdma 1>, 754 <&apbdma 2>, <&apbdma 2>, 755 <&apbdma 3>, <&apbdma 3>, 756 <&apbdma 4>, <&apbdma 4>, 757 <&apbdma 6>, <&apbdma 6>, 758 <&apbdma 7>, <&apbdma 7>, 759 <&apbdma 12>, <&apbdma 12>, 760 <&apbdma 13>, <&apbdma 13>, 761 <&apbdma 14>, <&apbdma 14>, 762 <&apbdma 29>, <&apbdma 29>; 763 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 764 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 765 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 766 "rx9", "tx9"; 767 ranges; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 771 tegra_i2s0: i2s@70301000 { 772 compatible = "nvidia,tegra124-i2s"; 773 reg = <0x70301000 0x100>; 774 nvidia,ahub-cif-ids = <4 4>; 775 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 776 resets = <&tegra_car 30>; 777 reset-names = "i2s"; 778 status = "disabled"; 779 }; 780 781 tegra_i2s1: i2s@70301100 { 782 compatible = "nvidia,tegra124-i2s"; 783 reg = <0x70301100 0x100>; 784 nvidia,ahub-cif-ids = <5 5>; 785 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 786 resets = <&tegra_car 11>; 787 reset-names = "i2s"; 788 status = "disabled"; 789 }; 790 791 tegra_i2s2: i2s@70301200 { 792 compatible = "nvidia,tegra124-i2s"; 793 reg = <0x70301200 0x100>; 794 nvidia,ahub-cif-ids = <6 6>; 795 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 796 resets = <&tegra_car 18>; 797 reset-names = "i2s"; 798 status = "disabled"; 799 }; 800 801 tegra_i2s3: i2s@70301300 { 802 compatible = "nvidia,tegra124-i2s"; 803 reg = <0x70301300 0x100>; 804 nvidia,ahub-cif-ids = <7 7>; 805 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 806 resets = <&tegra_car 101>; 807 reset-names = "i2s"; 808 status = "disabled"; 809 }; 810 811 tegra_i2s4: i2s@70301400 { 812 compatible = "nvidia,tegra124-i2s"; 813 reg = <0x70301400 0x100>; 814 nvidia,ahub-cif-ids = <8 8>; 815 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 816 resets = <&tegra_car 102>; 817 reset-names = "i2s"; 818 status = "disabled"; 819 }; 820 }; 821 822 usb@7d000000 { 823 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 824 reg = <0x7d000000 0x4000>; 825 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 826 phy_type = "utmi"; 827 clocks = <&tegra_car TEGRA124_CLK_USBD>; 828 resets = <&tegra_car 22>; 829 reset-names = "usb"; 830 nvidia,phy = <&phy1>; 831 status = "disabled"; 832 }; 833 834 phy1: usb-phy@7d000000 { 835 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 836 reg = <0x7d000000 0x4000>, 837 <0x7d000000 0x4000>; 838 phy_type = "utmi"; 839 clocks = <&tegra_car TEGRA124_CLK_USBD>, 840 <&tegra_car TEGRA124_CLK_PLL_U>, 841 <&tegra_car TEGRA124_CLK_USBD>; 842 clock-names = "reg", "pll_u", "utmi-pads"; 843 resets = <&tegra_car 22>, <&tegra_car 22>; 844 reset-names = "usb", "utmi-pads"; 845 nvidia,hssync-start-delay = <0>; 846 nvidia,idle-wait-delay = <17>; 847 nvidia,elastic-limit = <16>; 848 nvidia,term-range-adj = <6>; 849 nvidia,xcvr-setup = <9>; 850 nvidia,xcvr-lsfslew = <0>; 851 nvidia,xcvr-lsrslew = <3>; 852 nvidia,hssquelch-level = <2>; 853 nvidia,hsdiscon-level = <5>; 854 nvidia,xcvr-hsslew = <12>; 855 nvidia,has-utmi-pad-registers; 856 status = "disabled"; 857 }; 858 859 usb@7d004000 { 860 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 861 reg = <0x7d004000 0x4000>; 862 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 863 phy_type = "hsic"; 864 clocks = <&tegra_car TEGRA124_CLK_USB2>; 865 resets = <&tegra_car 58>; 866 reset-names = "usb"; 867 nvidia,phy = <&phy2>; 868 status = "disabled"; 869 }; 870 871 phy2: usb-phy@7d004000 { 872 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 873 reg = <0x7d004000 0x4000>, 874 <0x7d000000 0x4000>; 875 phy_type = "utmi"; 876 clocks = <&tegra_car TEGRA124_CLK_USB2>, 877 <&tegra_car TEGRA124_CLK_PLL_U>, 878 <&tegra_car TEGRA124_CLK_USBD>; 879 clock-names = "reg", "pll_u", "utmi-pads"; 880 resets = <&tegra_car 58>, <&tegra_car 22>; 881 reset-names = "usb", "utmi-pads"; 882 nvidia,hssync-start-delay = <0>; 883 nvidia,idle-wait-delay = <17>; 884 nvidia,elastic-limit = <16>; 885 nvidia,term-range-adj = <6>; 886 nvidia,xcvr-setup = <9>; 887 nvidia,xcvr-lsfslew = <0>; 888 nvidia,xcvr-lsrslew = <3>; 889 nvidia,hssquelch-level = <2>; 890 nvidia,hsdiscon-level = <5>; 891 nvidia,xcvr-hsslew = <12>; 892 status = "disabled"; 893 }; 894 895 usb@7d008000 { 896 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 897 reg = <0x7d008000 0x4000>; 898 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 899 phy_type = "utmi"; 900 clocks = <&tegra_car TEGRA124_CLK_USB3>; 901 resets = <&tegra_car 59>; 902 reset-names = "usb"; 903 nvidia,phy = <&phy3>; 904 status = "disabled"; 905 }; 906 907 phy3: usb-phy@7d008000 { 908 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 909 reg = <0x7d008000 0x4000>, 910 <0x7d000000 0x4000>; 911 phy_type = "utmi"; 912 clocks = <&tegra_car TEGRA124_CLK_USB3>, 913 <&tegra_car TEGRA124_CLK_PLL_U>, 914 <&tegra_car TEGRA124_CLK_USBD>; 915 clock-names = "reg", "pll_u", "utmi-pads"; 916 resets = <&tegra_car 59>, <&tegra_car 22>; 917 reset-names = "usb", "utmi-pads"; 918 nvidia,hssync-start-delay = <0>; 919 nvidia,idle-wait-delay = <17>; 920 nvidia,elastic-limit = <16>; 921 nvidia,term-range-adj = <6>; 922 nvidia,xcvr-setup = <9>; 923 nvidia,xcvr-lsfslew = <0>; 924 nvidia,xcvr-lsrslew = <3>; 925 nvidia,hssquelch-level = <2>; 926 nvidia,hsdiscon-level = <5>; 927 nvidia,xcvr-hsslew = <12>; 928 status = "disabled"; 929 }; 930 931 cpus { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 cpu@0 { 936 device_type = "cpu"; 937 compatible = "arm,cortex-a15"; 938 reg = <0>; 939 940 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 941 <&tegra_car TEGRA124_CLK_CCLK_LP>, 942 <&tegra_car TEGRA124_CLK_PLL_X>, 943 <&tegra_car TEGRA124_CLK_PLL_P>, 944 <&dfll>; 945 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 946 /* FIXME: what's the actual transition time? */ 947 clock-latency = <300000>; 948 }; 949 950 cpu@1 { 951 device_type = "cpu"; 952 compatible = "arm,cortex-a15"; 953 reg = <1>; 954 }; 955 956 cpu@2 { 957 device_type = "cpu"; 958 compatible = "arm,cortex-a15"; 959 reg = <2>; 960 }; 961 962 cpu@3 { 963 device_type = "cpu"; 964 compatible = "arm,cortex-a15"; 965 reg = <3>; 966 }; 967 }; 968 969 pmu { 970 compatible = "arm,cortex-a15-pmu"; 971 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-affinity = <&{/cpus/cpu@0}>, 976 <&{/cpus/cpu@1}>, 977 <&{/cpus/cpu@2}>, 978 <&{/cpus/cpu@3}>; 979 }; 980 981 thermal-zones { 982 cpu { 983 polling-delay-passive = <1000>; 984 polling-delay = <1000>; 985 986 thermal-sensors = 987 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 988 }; 989 990 mem { 991 polling-delay-passive = <1000>; 992 polling-delay = <1000>; 993 994 thermal-sensors = 995 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 996 }; 997 998 gpu { 999 polling-delay-passive = <1000>; 1000 polling-delay = <1000>; 1001 1002 thermal-sensors = 1003 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1004 }; 1005 1006 pllx { 1007 polling-delay-passive = <1000>; 1008 polling-delay = <1000>; 1009 1010 thermal-sensors = 1011 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1012 }; 1013 }; 1014 1015 timer { 1016 compatible = "arm,armv7-timer"; 1017 interrupts = <GIC_PPI 13 1018 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1019 <GIC_PPI 14 1020 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1021 <GIC_PPI 11 1022 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1023 <GIC_PPI 10 1024 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1025 interrupt-parent = <&gic>; 1026 }; 1027}; 1028