xref: /openbmc/u-boot/arch/arm/dts/tegra124.dtsi (revision 20c700f8)
1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/tegra124-car.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h>
9
10#include "skeleton.dtsi"
11
12/ {
13	compatible = "nvidia,tegra124";
14	interrupt-parent = <&lic>;
15
16
17	pcie-controller@01003000 {
18		compatible = "nvidia,tegra124-pcie";
19		device_type = "pci";
20		reg = <0x01003000 0x00000800   /* PADS registers */
21		       0x01003800 0x00000800   /* AFI registers */
22		       0x02000000 0x10000000>; /* configuration space */
23		reg-names = "pads", "afi", "cs";
24		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26		interrupt-names = "intr", "msi";
27
28		#interrupt-cells = <1>;
29		interrupt-map-mask = <0 0 0 0>;
30		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
31
32		bus-range = <0x00 0xff>;
33		#address-cells = <3>;
34		#size-cells = <2>;
35
36		ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000   /* port 0 configuration space */
37			  0x82000000 0 0x01001000 0x01001000 0 0x00001000   /* port 1 configuration space */
38			  0x81000000 0 0x0        0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
39			  0x82000000 0 0x13000000 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
40			  0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
41
42		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43			 <&tegra_car TEGRA124_CLK_AFI>,
44			 <&tegra_car TEGRA124_CLK_PLL_E>,
45			 <&tegra_car TEGRA124_CLK_CML0>;
46		clock-names = "pex", "afi", "pll_e", "cml";
47		resets = <&tegra_car 70>,
48			 <&tegra_car 72>,
49			 <&tegra_car 74>;
50		reset-names = "pex", "afi", "pcie_x";
51		status = "disabled";
52
53		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
54		phy-names = "pcie";
55
56		pci@1,0 {
57			device_type = "pci";
58			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
59			reg = <0x000800 0 0 0 0>;
60			status = "disabled";
61
62			#address-cells = <3>;
63			#size-cells = <2>;
64			ranges;
65
66			nvidia,num-lanes = <2>;
67		};
68
69		pci@2,0 {
70			device_type = "pci";
71			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72			reg = <0x001000 0 0 0 0>;
73			status = "disabled";
74
75			#address-cells = <3>;
76			#size-cells = <2>;
77			ranges;
78
79			nvidia,num-lanes = <1>;
80		};
81	};
82
83	host1x@50000000 {
84		compatible = "nvidia,tegra124-host1x", "simple-bus";
85		reg = <0x50000000 0x00034000>;
86		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
87			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
88		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
89		resets = <&tegra_car 28>;
90		reset-names = "host1x";
91
92		#address-cells = <1>;
93		#size-cells = <1>;
94
95		ranges = <0x54000000 0x54000000 0x01000000>;
96
97		dc@54200000 {
98			compatible = "nvidia,tegra124-dc";
99			reg = <0x54200000 0x00040000>;
100			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
101			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
102				 <&tegra_car TEGRA124_CLK_PLL_P>;
103			clock-names = "dc", "parent";
104			resets = <&tegra_car 27>;
105			reset-names = "dc";
106
107			iommus = <&mc TEGRA_SWGROUP_DC>;
108
109			nvidia,head = <0>;
110		};
111
112		dc@54240000 {
113			compatible = "nvidia,tegra124-dc";
114			reg = <0x54240000 0x00040000>;
115			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
116			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
117				 <&tegra_car TEGRA124_CLK_PLL_P>;
118			clock-names = "dc", "parent";
119			resets = <&tegra_car 26>;
120			reset-names = "dc";
121
122			iommus = <&mc TEGRA_SWGROUP_DCB>;
123
124			nvidia,head = <1>;
125		};
126
127		hdmi@54280000 {
128			compatible = "nvidia,tegra124-hdmi";
129			reg = <0x54280000 0x00040000>;
130			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
131			clocks = <&tegra_car TEGRA124_CLK_HDMI>,
132				 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
133			clock-names = "hdmi", "parent";
134			resets = <&tegra_car 51>;
135			reset-names = "hdmi";
136			status = "disabled";
137		};
138
139		sor@54540000 {
140			compatible = "nvidia,tegra124-sor";
141			reg = <0x54540000 0x00040000>;
142			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
143			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
144				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
145				 <&tegra_car TEGRA124_CLK_PLL_DP>,
146				 <&tegra_car TEGRA124_CLK_CLK_M>;
147			clock-names = "sor", "parent", "dp", "safe";
148			resets = <&tegra_car 182>;
149			reset-names = "sor";
150			status = "disabled";
151		};
152
153		dpaux: dpaux@545c0000 {
154			compatible = "nvidia,tegra124-dpaux";
155			reg = <0x545c0000 0x00040000>;
156			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
157			clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
158				 <&tegra_car TEGRA124_CLK_PLL_DP>;
159			clock-names = "dpaux", "parent";
160			resets = <&tegra_car 181>;
161			reset-names = "dpaux";
162			status = "disabled";
163		};
164	};
165
166	gic: interrupt-controller@50041000 {
167		compatible = "arm,cortex-a15-gic";
168		#interrupt-cells = <3>;
169		interrupt-controller;
170		reg = <0x50041000 0x1000>,
171		      <0x50042000 0x2000>,
172		      <0x50044000 0x2000>,
173		      <0x50046000 0x2000>;
174		interrupts = <GIC_PPI 9
175			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
176		interrupt-parent = <&gic>;
177	};
178
179	gpu@57000000 {
180		compatible = "nvidia,gk20a";
181		reg = <0x57000000 0x01000000>,
182		      <0x58000000 0x01000000>;
183		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
184			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
185		interrupt-names = "stall", "nonstall";
186		clocks = <&tegra_car TEGRA124_CLK_GPU>,
187			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
188		clock-names = "gpu", "pwr";
189		resets = <&tegra_car 184>;
190		reset-names = "gpu";
191
192		iommus = <&mc TEGRA_SWGROUP_GPU>;
193
194		status = "disabled";
195	};
196
197	lic: interrupt-controller@60004000 {
198		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
199		reg = <0x0 0x60004000 0x0 0x100>,
200		      <0x0 0x60004100 0x0 0x100>,
201		      <0x0 0x60004200 0x0 0x100>,
202		      <0x0 0x60004300 0x0 0x100>,
203		      <0x0 0x60004400 0x0 0x100>;
204		interrupt-controller;
205		#interrupt-cells = <3>;
206		interrupt-parent = <&gic>;
207	};
208
209	timer@60005000 {
210		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
211		reg = <0x60005000 0x400>;
212		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
213			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
214			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
215			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
216			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
217			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
218		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
219	};
220
221	tegra_car: clock@60006000 {
222		compatible = "nvidia,tegra124-car";
223		reg = <0x60006000 0x1000>;
224		#clock-cells = <1>;
225		#reset-cells = <1>;
226		nvidia,external-memory-controller = <&emc>;
227	};
228
229	flow-controller@60007000 {
230		compatible = "nvidia,tegra124-flowctrl";
231		reg = <0x60007000 0x1000>;
232	};
233
234	actmon@6000c800 {
235		compatible = "nvidia,tegra124-actmon";
236		reg = <0x6000c800 0x400>;
237		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
238		clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
239			 <&tegra_car TEGRA124_CLK_EMC>;
240		clock-names = "actmon", "emc";
241		resets = <&tegra_car 119>;
242		reset-names = "actmon";
243	};
244
245	gpio: gpio@6000d000 {
246		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
247		reg = <0x6000d000 0x1000>;
248		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
249			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
250			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
251			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
252			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
253			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
254			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
255			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
256		#gpio-cells = <2>;
257		gpio-controller;
258		#interrupt-cells = <2>;
259		interrupt-controller;
260		/*
261		gpio-ranges = <&pinmux 0 0 251>;
262		*/
263	};
264
265	apbdma: dma@60020000 {
266		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
267		reg = <0x60020000 0x1400>;
268		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
269			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
270			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
271			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
272			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
273			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
274			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
275			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
276			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
277			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
278			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
279			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
280			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
281			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
282			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
283			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
284			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
285			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
286			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
287			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
288			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
289			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
290			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
291			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
292			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
293			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
294			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
295			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
296			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
297			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
298			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
299			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
300		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
301		resets = <&tegra_car 34>;
302		reset-names = "dma";
303		#dma-cells = <1>;
304	};
305
306	apbmisc@70000800 {
307		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
308		reg = <0x70000800 0x64>,   /* Chip revision */
309		      <0x7000e864 0x04>;   /* Strapping options */
310	};
311
312	pinmux: pinmux@70000868 {
313		compatible = "nvidia,tegra124-pinmux";
314		reg = <0x70000868 0x164>, /* Pad control registers */
315		      <0x70003000 0x434>, /* Mux registers */
316		      <0x70000820 0x008>; /* MIPI pad control */
317	};
318
319	/*
320	 * There are two serial driver i.e. 8250 based simple serial
321	 * driver and APB DMA based serial driver for higher baudrate
322	 * and performace. To enable the 8250 based driver, the compatible
323	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
324	 * the APB DMA based serial driver, the compatible is
325	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
326	 */
327	uarta: serial@70006000 {
328		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
329		reg = <0x70006000 0x40>;
330		reg-shift = <2>;
331		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
332		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
333		resets = <&tegra_car 6>;
334		reset-names = "serial";
335		dmas = <&apbdma 8>, <&apbdma 8>;
336		dma-names = "rx", "tx";
337		status = "disabled";
338	};
339
340	uartb: serial@70006040 {
341		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
342		reg = <0x70006040 0x40>;
343		reg-shift = <2>;
344		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
345		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
346		resets = <&tegra_car 7>;
347		reset-names = "serial";
348		dmas = <&apbdma 9>, <&apbdma 9>;
349		dma-names = "rx", "tx";
350		status = "disabled";
351	};
352
353	uartc: serial@70006200 {
354		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
355		reg = <0x70006200 0x40>;
356		reg-shift = <2>;
357		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
358		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
359		resets = <&tegra_car 55>;
360		reset-names = "serial";
361		dmas = <&apbdma 10>, <&apbdma 10>;
362		dma-names = "rx", "tx";
363		status = "disabled";
364	};
365
366	uartd: serial@70006300 {
367		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
368		reg = <0x70006300 0x40>;
369		reg-shift = <2>;
370		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
371		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
372		resets = <&tegra_car 65>;
373		reset-names = "serial";
374		dmas = <&apbdma 19>, <&apbdma 19>;
375		dma-names = "rx", "tx";
376		status = "disabled";
377	};
378
379	pwm: pwm@7000a000 {
380		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
381		reg = <0x7000a000 0x100>;
382		#pwm-cells = <2>;
383		clocks = <&tegra_car TEGRA124_CLK_PWM>;
384		resets = <&tegra_car 17>;
385		reset-names = "pwm";
386		status = "disabled";
387	};
388
389	i2c@7000c000 {
390		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
391		reg = <0x7000c000 0x100>;
392		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
393		#address-cells = <1>;
394		#size-cells = <0>;
395		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
396		clock-names = "div-clk";
397		resets = <&tegra_car 12>;
398		reset-names = "i2c";
399		dmas = <&apbdma 21>, <&apbdma 21>;
400		dma-names = "rx", "tx";
401		status = "disabled";
402	};
403
404	i2c@7000c400 {
405		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
406		reg = <0x7000c400 0x100>;
407		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
408		#address-cells = <1>;
409		#size-cells = <0>;
410		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
411		clock-names = "div-clk";
412		resets = <&tegra_car 54>;
413		reset-names = "i2c";
414		dmas = <&apbdma 22>, <&apbdma 22>;
415		dma-names = "rx", "tx";
416		status = "disabled";
417	};
418
419	i2c@7000c500 {
420		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
421		reg = <0x7000c500 0x100>;
422		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
423		#address-cells = <1>;
424		#size-cells = <0>;
425		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
426		clock-names = "div-clk";
427		resets = <&tegra_car 67>;
428		reset-names = "i2c";
429		dmas = <&apbdma 23>, <&apbdma 23>;
430		dma-names = "rx", "tx";
431		status = "disabled";
432	};
433
434	i2c@7000c700 {
435		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
436		reg = <0x7000c700 0x100>;
437		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
438		#address-cells = <1>;
439		#size-cells = <0>;
440		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
441		clock-names = "div-clk";
442		resets = <&tegra_car 103>;
443		reset-names = "i2c";
444		dmas = <&apbdma 26>, <&apbdma 26>;
445		dma-names = "rx", "tx";
446		status = "disabled";
447	};
448
449	i2c@7000d000 {
450		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
451		reg = <0x7000d000 0x100>;
452		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
453		#address-cells = <1>;
454		#size-cells = <0>;
455		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
456		clock-names = "div-clk";
457		resets = <&tegra_car 47>;
458		reset-names = "i2c";
459		dmas = <&apbdma 24>, <&apbdma 24>;
460		dma-names = "rx", "tx";
461		status = "disabled";
462	};
463
464	i2c@7000d100 {
465		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
466		reg = <0x7000d100 0x100>;
467		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
468		#address-cells = <1>;
469		#size-cells = <0>;
470		clocks = <&tegra_car TEGRA124_CLK_I2C6>;
471		clock-names = "div-clk";
472		resets = <&tegra_car 166>;
473		reset-names = "i2c";
474		dmas = <&apbdma 30>, <&apbdma 30>;
475		dma-names = "rx", "tx";
476		status = "disabled";
477	};
478
479	spi@7000d400 {
480		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
481		reg = <0x7000d400 0x200>;
482		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
483		#address-cells = <1>;
484		#size-cells = <0>;
485		clocks = <&tegra_car TEGRA124_CLK_SBC1>;
486		clock-names = "spi";
487		resets = <&tegra_car 41>;
488		reset-names = "spi";
489		dmas = <&apbdma 15>, <&apbdma 15>;
490		dma-names = "rx", "tx";
491		status = "disabled";
492	};
493
494	spi@7000d600 {
495		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
496		reg = <0x7000d600 0x200>;
497		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
498		#address-cells = <1>;
499		#size-cells = <0>;
500		clocks = <&tegra_car TEGRA124_CLK_SBC2>;
501		clock-names = "spi";
502		resets = <&tegra_car 44>;
503		reset-names = "spi";
504		dmas = <&apbdma 16>, <&apbdma 16>;
505		dma-names = "rx", "tx";
506		status = "disabled";
507	};
508
509	spi@7000d800 {
510		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
511		reg = <0x7000d800 0x200>;
512		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513		#address-cells = <1>;
514		#size-cells = <0>;
515		clocks = <&tegra_car TEGRA124_CLK_SBC3>;
516		clock-names = "spi";
517		resets = <&tegra_car 46>;
518		reset-names = "spi";
519		dmas = <&apbdma 17>, <&apbdma 17>;
520		dma-names = "rx", "tx";
521		status = "disabled";
522	};
523
524	spi@7000da00 {
525		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
526		reg = <0x7000da00 0x200>;
527		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
528		#address-cells = <1>;
529		#size-cells = <0>;
530		clocks = <&tegra_car TEGRA124_CLK_SBC4>;
531		clock-names = "spi";
532		resets = <&tegra_car 68>;
533		reset-names = "spi";
534		dmas = <&apbdma 18>, <&apbdma 18>;
535		dma-names = "rx", "tx";
536		status = "disabled";
537	};
538
539	spi@7000dc00 {
540		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
541		reg = <0x7000dc00 0x200>;
542		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
543		#address-cells = <1>;
544		#size-cells = <0>;
545		clocks = <&tegra_car TEGRA124_CLK_SBC5>;
546		clock-names = "spi";
547		resets = <&tegra_car 104>;
548		reset-names = "spi";
549		dmas = <&apbdma 27>, <&apbdma 27>;
550		dma-names = "rx", "tx";
551		status = "disabled";
552	};
553
554	spi@7000de00 {
555		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
556		reg = <0x7000de00 0x200>;
557		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
558		#address-cells = <1>;
559		#size-cells = <0>;
560		clocks = <&tegra_car TEGRA124_CLK_SBC6>;
561		clock-names = "spi";
562		resets = <&tegra_car 105>;
563		reset-names = "spi";
564		dmas = <&apbdma 28>, <&apbdma 28>;
565		dma-names = "rx", "tx";
566		status = "disabled";
567	};
568
569	rtc@7000e000 {
570		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
571		reg = <0x7000e000 0x100>;
572		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
573		clocks = <&tegra_car TEGRA124_CLK_RTC>;
574	};
575
576	pmc@7000e400 {
577		compatible = "nvidia,tegra124-pmc";
578		reg = <0x7000e400 0x400>;
579		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
580		clock-names = "pclk", "clk32k_in";
581	};
582
583	fuse@7000f800 {
584		compatible = "nvidia,tegra124-efuse";
585		reg = <0x7000f800 0x400>;
586		clocks = <&tegra_car TEGRA124_CLK_FUSE>;
587		clock-names = "fuse";
588		resets = <&tegra_car 39>;
589		reset-names = "fuse";
590	};
591
592	mc: memory-controller@70019000 {
593		compatible = "nvidia,tegra124-mc";
594		reg = <0x70019000 0x1000>;
595		clocks = <&tegra_car TEGRA124_CLK_MC>;
596		clock-names = "mc";
597
598		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
599
600		#iommu-cells = <1>;
601	};
602
603	emc: emc@7001b000 {
604		compatible = "nvidia,tegra124-emc";
605		reg = <0x7001b000 0x1000>;
606
607		nvidia,memory-controller = <&mc>;
608	};
609
610	sata@70020000 {
611		compatible = "nvidia,tegra124-ahci";
612		reg = <0x70027000 0x2000>, /* AHCI */
613		      <0x70020000 0x7000>; /* SATA */
614		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
615		clocks = <&tegra_car TEGRA124_CLK_SATA>,
616			 <&tegra_car TEGRA124_CLK_SATA_OOB>,
617			 <&tegra_car TEGRA124_CLK_CML1>,
618			 <&tegra_car TEGRA124_CLK_PLL_E>;
619		clock-names = "sata", "sata-oob", "cml1", "pll_e";
620		resets = <&tegra_car 124>,
621			 <&tegra_car 123>,
622			 <&tegra_car 129>;
623		reset-names = "sata", "sata-oob", "sata-cold";
624		phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
625		phy-names = "sata-phy";
626		status = "disabled";
627	};
628
629	hda@70030000 {
630		compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
631		reg = <0x70030000 0x10000>;
632		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
633		clocks = <&tegra_car TEGRA124_CLK_HDA>,
634			 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
635			 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
636		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
637		resets = <&tegra_car 125>, /* hda */
638			 <&tegra_car 128>, /* hda2hdmi */
639			 <&tegra_car 111>; /* hda2codec_2x */
640		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
641		status = "disabled";
642	};
643
644	usb@70090000 {
645		compatible = "nvidia,tegra124-xusb";
646		reg = <0x70090000 0x8000>,
647		      <0x70098000 0x1000>,
648		      <0x70099000 0x1000>;
649		reg-names = "hcd", "fpci", "ipfs";
650
651		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
652			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
653
654		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
655			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
656			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
657			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
658			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
659			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
660			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
661			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
662			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
663			 <&tegra_car TEGRA124_CLK_CLK_M>,
664			 <&tegra_car TEGRA124_CLK_PLL_E>;
665		clock-names = "xusb_host", "xusb_host_src",
666			      "xusb_falcon_src", "xusb_ss",
667			      "xusb_ss_div2", "xusb_ss_src",
668			      "xusb_hs_src", "xusb_fs_src",
669			      "pll_u_480m", "clk_m", "pll_e";
670		resets = <&tegra_car 89>, <&tegra_car 156>,
671			 <&tegra_car 143>;
672		reset-names = "xusb_host", "xusb_ss", "xusb_src";
673
674		nvidia,xusb-padctl = <&padctl>;
675
676		status = "disabled";
677	};
678
679	padctl: padctl@7009f000 {
680		compatible = "nvidia,tegra124-xusb-padctl";
681		reg = <0x7009f000 0x1000>;
682		resets = <&tegra_car 142>;
683		reset-names = "padctl";
684
685		#phy-cells = <1>;
686	};
687
688	sdhci@700b0000 {
689		compatible = "nvidia,tegra124-sdhci";
690		reg = <0x700b0000 0x200>;
691		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
692		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
693		resets = <&tegra_car 14>;
694		reset-names = "sdhci";
695		status = "disabled";
696	};
697
698	sdhci@700b0200 {
699		compatible = "nvidia,tegra124-sdhci";
700		reg = <0x700b0200 0x200>;
701		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
702		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
703		resets = <&tegra_car 9>;
704		reset-names = "sdhci";
705		status = "disabled";
706	};
707
708	sdhci@700b0400 {
709		compatible = "nvidia,tegra124-sdhci";
710		reg = <0x700b0400 0x200>;
711		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
712		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
713		resets = <&tegra_car 69>;
714		reset-names = "sdhci";
715		status = "disabled";
716	};
717
718	sdhci@700b0600 {
719		compatible = "nvidia,tegra124-sdhci";
720		reg = <0x700b0600 0x200>;
721		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
722		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
723		resets = <&tegra_car 15>;
724		reset-names = "sdhci";
725		status = "disabled";
726	};
727
728	soctherm: thermal-sensor@700e2000 {
729		compatible = "nvidia,tegra124-soctherm";
730		reg = <0x700e2000 0x1000>;
731		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
732		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
733			<&tegra_car TEGRA124_CLK_SOC_THERM>;
734		clock-names = "tsensor", "soctherm";
735		resets = <&tegra_car 78>;
736		reset-names = "soctherm";
737		#thermal-sensor-cells = <1>;
738	};
739
740	dfll: clock@70110000 {
741		compatible = "nvidia,tegra124-dfll";
742		reg = <0x70110000 0x100>, /* DFLL control */
743		      <0x70110000 0x100>, /* I2C output control */
744		      <0x70110100 0x100>, /* Integrated I2C controller */
745		      <0x70110200 0x100>; /* Look-up table RAM */
746		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
747		clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
748			 <&tegra_car TEGRA124_CLK_DFLL_REF>,
749			 <&tegra_car TEGRA124_CLK_I2C5>;
750		clock-names = "soc", "ref", "i2c";
751		resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
752		reset-names = "dvco";
753		#clock-cells = <0>;
754		clock-output-names = "dfllCPU_out";
755		nvidia,sample-rate = <12500>;
756		nvidia,droop-ctrl = <0x00000f00>;
757		nvidia,force-mode = <1>;
758		nvidia,cf = <10>;
759		nvidia,ci = <0>;
760		nvidia,cg = <2>;
761		status = "disabled";
762	};
763
764	ahub@70300000 {
765		compatible = "nvidia,tegra124-ahub";
766		reg = <0x70300000 0x200>,
767		      <0x70300800 0x800>,
768		      <0x70300200 0x600>;
769		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
770		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
771			 <&tegra_car TEGRA124_CLK_APBIF>;
772		clock-names = "d_audio", "apbif";
773		resets = <&tegra_car 106>, /* d_audio */
774			 <&tegra_car 107>, /* apbif */
775			 <&tegra_car 30>,  /* i2s0 */
776			 <&tegra_car 11>,  /* i2s1 */
777			 <&tegra_car 18>,  /* i2s2 */
778			 <&tegra_car 101>, /* i2s3 */
779			 <&tegra_car 102>, /* i2s4 */
780			 <&tegra_car 108>, /* dam0 */
781			 <&tegra_car 109>, /* dam1 */
782			 <&tegra_car 110>, /* dam2 */
783			 <&tegra_car 10>,  /* spdif */
784			 <&tegra_car 153>, /* amx */
785			 <&tegra_car 185>, /* amx1 */
786			 <&tegra_car 154>, /* adx */
787			 <&tegra_car 180>, /* adx1 */
788			 <&tegra_car 186>, /* afc0 */
789			 <&tegra_car 187>, /* afc1 */
790			 <&tegra_car 188>, /* afc2 */
791			 <&tegra_car 189>, /* afc3 */
792			 <&tegra_car 190>, /* afc4 */
793			 <&tegra_car 191>; /* afc5 */
794		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
795			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
796			      "spdif", "amx", "amx1", "adx", "adx1",
797			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
798		dmas = <&apbdma 1>, <&apbdma 1>,
799		       <&apbdma 2>, <&apbdma 2>,
800		       <&apbdma 3>, <&apbdma 3>,
801		       <&apbdma 4>, <&apbdma 4>,
802		       <&apbdma 6>, <&apbdma 6>,
803		       <&apbdma 7>, <&apbdma 7>,
804		       <&apbdma 12>, <&apbdma 12>,
805		       <&apbdma 13>, <&apbdma 13>,
806		       <&apbdma 14>, <&apbdma 14>,
807		       <&apbdma 29>, <&apbdma 29>;
808		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
809			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
810			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
811			    "rx9", "tx9";
812		ranges;
813		#address-cells = <1>;
814		#size-cells = <1>;
815
816		tegra_i2s0: i2s@70301000 {
817			compatible = "nvidia,tegra124-i2s";
818			reg = <0x70301000 0x100>;
819			nvidia,ahub-cif-ids = <4 4>;
820			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
821			resets = <&tegra_car 30>;
822			reset-names = "i2s";
823			status = "disabled";
824		};
825
826		tegra_i2s1: i2s@70301100 {
827			compatible = "nvidia,tegra124-i2s";
828			reg = <0x70301100 0x100>;
829			nvidia,ahub-cif-ids = <5 5>;
830			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
831			resets = <&tegra_car 11>;
832			reset-names = "i2s";
833			status = "disabled";
834		};
835
836		tegra_i2s2: i2s@70301200 {
837			compatible = "nvidia,tegra124-i2s";
838			reg = <0x70301200 0x100>;
839			nvidia,ahub-cif-ids = <6 6>;
840			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
841			resets = <&tegra_car 18>;
842			reset-names = "i2s";
843			status = "disabled";
844		};
845
846		tegra_i2s3: i2s@70301300 {
847			compatible = "nvidia,tegra124-i2s";
848			reg = <0x70301300 0x100>;
849			nvidia,ahub-cif-ids = <7 7>;
850			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
851			resets = <&tegra_car 101>;
852			reset-names = "i2s";
853			status = "disabled";
854		};
855
856		tegra_i2s4: i2s@70301400 {
857			compatible = "nvidia,tegra124-i2s";
858			reg = <0x70301400 0x100>;
859			nvidia,ahub-cif-ids = <8 8>;
860			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
861			resets = <&tegra_car 102>;
862			reset-names = "i2s";
863			status = "disabled";
864		};
865	};
866
867	usb@7d000000 {
868		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
869		reg = <0x7d000000 0x4000>;
870		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
871		phy_type = "utmi";
872		clocks = <&tegra_car TEGRA124_CLK_USBD>;
873		resets = <&tegra_car 22>;
874		reset-names = "usb";
875		nvidia,phy = <&phy1>;
876		status = "disabled";
877	};
878
879	phy1: usb-phy@7d000000 {
880		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
881		reg = <0x7d000000 0x4000>,
882		      <0x7d000000 0x4000>;
883		phy_type = "utmi";
884		clocks = <&tegra_car TEGRA124_CLK_USBD>,
885			 <&tegra_car TEGRA124_CLK_PLL_U>,
886			 <&tegra_car TEGRA124_CLK_USBD>;
887		clock-names = "reg", "pll_u", "utmi-pads";
888		resets = <&tegra_car 22>, <&tegra_car 22>;
889		reset-names = "usb", "utmi-pads";
890		nvidia,hssync-start-delay = <0>;
891		nvidia,idle-wait-delay = <17>;
892		nvidia,elastic-limit = <16>;
893		nvidia,term-range-adj = <6>;
894		nvidia,xcvr-setup = <9>;
895		nvidia,xcvr-lsfslew = <0>;
896		nvidia,xcvr-lsrslew = <3>;
897		nvidia,hssquelch-level = <2>;
898		nvidia,hsdiscon-level = <5>;
899		nvidia,xcvr-hsslew = <12>;
900		nvidia,has-utmi-pad-registers;
901		status = "disabled";
902	};
903
904	usb@7d004000 {
905		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
906		reg = <0x7d004000 0x4000>;
907		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
908		phy_type = "utmi";
909		clocks = <&tegra_car TEGRA124_CLK_USB2>;
910		resets = <&tegra_car 58>;
911		reset-names = "usb";
912		nvidia,phy = <&phy2>;
913		status = "disabled";
914	};
915
916	phy2: usb-phy@7d004000 {
917		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
918		reg = <0x7d004000 0x4000>,
919		      <0x7d000000 0x4000>;
920		phy_type = "utmi";
921		clocks = <&tegra_car TEGRA124_CLK_USB2>,
922			 <&tegra_car TEGRA124_CLK_PLL_U>,
923			 <&tegra_car TEGRA124_CLK_USBD>;
924		clock-names = "reg", "pll_u", "utmi-pads";
925		resets = <&tegra_car 58>, <&tegra_car 22>;
926		reset-names = "usb", "utmi-pads";
927		nvidia,hssync-start-delay = <0>;
928		nvidia,idle-wait-delay = <17>;
929		nvidia,elastic-limit = <16>;
930		nvidia,term-range-adj = <6>;
931		nvidia,xcvr-setup = <9>;
932		nvidia,xcvr-lsfslew = <0>;
933		nvidia,xcvr-lsrslew = <3>;
934		nvidia,hssquelch-level = <2>;
935		nvidia,hsdiscon-level = <5>;
936		nvidia,xcvr-hsslew = <12>;
937		status = "disabled";
938	};
939
940	usb@7d008000 {
941		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
942		reg = <0x7d008000 0x4000>;
943		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
944		phy_type = "utmi";
945		clocks = <&tegra_car TEGRA124_CLK_USB3>;
946		resets = <&tegra_car 59>;
947		reset-names = "usb";
948		nvidia,phy = <&phy3>;
949		status = "disabled";
950	};
951
952	phy3: usb-phy@7d008000 {
953		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
954		reg = <0x7d008000 0x4000>,
955		      <0x7d000000 0x4000>;
956		phy_type = "utmi";
957		clocks = <&tegra_car TEGRA124_CLK_USB3>,
958			 <&tegra_car TEGRA124_CLK_PLL_U>,
959			 <&tegra_car TEGRA124_CLK_USBD>;
960		clock-names = "reg", "pll_u", "utmi-pads";
961		resets = <&tegra_car 59>, <&tegra_car 22>;
962		reset-names = "usb", "utmi-pads";
963		nvidia,hssync-start-delay = <0>;
964		nvidia,idle-wait-delay = <17>;
965		nvidia,elastic-limit = <16>;
966		nvidia,term-range-adj = <6>;
967		nvidia,xcvr-setup = <9>;
968		nvidia,xcvr-lsfslew = <0>;
969		nvidia,xcvr-lsrslew = <3>;
970		nvidia,hssquelch-level = <2>;
971		nvidia,hsdiscon-level = <5>;
972		nvidia,xcvr-hsslew = <12>;
973		status = "disabled";
974	};
975
976	cpus {
977		#address-cells = <1>;
978		#size-cells = <0>;
979
980		cpu@0 {
981			device_type = "cpu";
982			compatible = "arm,cortex-a15";
983			reg = <0>;
984
985			clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
986				 <&tegra_car TEGRA124_CLK_CCLK_LP>,
987				 <&tegra_car TEGRA124_CLK_PLL_X>,
988				 <&tegra_car TEGRA124_CLK_PLL_P>,
989				 <&dfll>;
990			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
991			/* FIXME: what's the actual transition time? */
992			clock-latency = <300000>;
993		};
994
995		cpu@1 {
996			device_type = "cpu";
997			compatible = "arm,cortex-a15";
998			reg = <1>;
999		};
1000
1001		cpu@2 {
1002			device_type = "cpu";
1003			compatible = "arm,cortex-a15";
1004			reg = <2>;
1005		};
1006
1007		cpu@3 {
1008			device_type = "cpu";
1009			compatible = "arm,cortex-a15";
1010			reg = <3>;
1011		};
1012	};
1013
1014	pmu {
1015		compatible = "arm,cortex-a15-pmu";
1016		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1017			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1018			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1019			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1020		interrupt-affinity = <&{/cpus/cpu@0}>,
1021				     <&{/cpus/cpu@1}>,
1022				     <&{/cpus/cpu@2}>,
1023				     <&{/cpus/cpu@3}>;
1024	};
1025
1026	thermal-zones {
1027		cpu {
1028			polling-delay-passive = <1000>;
1029			polling-delay = <1000>;
1030
1031			thermal-sensors =
1032				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1033		};
1034
1035		mem {
1036			polling-delay-passive = <1000>;
1037			polling-delay = <1000>;
1038
1039			thermal-sensors =
1040				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1041		};
1042
1043		gpu {
1044			polling-delay-passive = <1000>;
1045			polling-delay = <1000>;
1046
1047			thermal-sensors =
1048				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1049		};
1050
1051		pllx {
1052			polling-delay-passive = <1000>;
1053			polling-delay = <1000>;
1054
1055			thermal-sensors =
1056				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1057		};
1058	};
1059
1060	timer {
1061		compatible = "arm,armv7-timer";
1062		interrupts = <GIC_PPI 13
1063				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1064			     <GIC_PPI 14
1065				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1066			     <GIC_PPI 11
1067				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1068			     <GIC_PPI 10
1069				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1070		interrupt-parent = <&gic>;
1071	};
1072};
1073