1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun8i-de2.h> 44#include <dt-bindings/clock/sun8i-h3-ccu.h> 45#include <dt-bindings/clock/sun8i-r-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun8i-de2.h> 48#include <dt-bindings/reset/sun8i-h3-ccu.h> 49#include <dt-bindings/reset/sun8i-r-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 chosen { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61 framebuffer-hdmi { 62 compatible = "allwinner,simple-framebuffer", 63 "simple-framebuffer"; 64 allwinner,pipeline = "mixer0-lcd0-hdmi"; 65 clocks = <&display_clocks CLK_MIXER0>, 66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; 67 status = "disabled"; 68 }; 69 70 framebuffer-tve { 71 compatible = "allwinner,simple-framebuffer", 72 "simple-framebuffer"; 73 allwinner,pipeline = "mixer1-lcd1-tve"; 74 clocks = <&display_clocks CLK_MIXER1>, 75 <&ccu CLK_TVE>; 76 status = "disabled"; 77 }; 78 }; 79 80 clocks { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 osc24M: osc24M_clk { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-frequency = <24000000>; 89 clock-output-names = "osc24M"; 90 }; 91 92 osc32k: osc32k_clk { 93 #clock-cells = <0>; 94 compatible = "fixed-clock"; 95 clock-frequency = <32768>; 96 clock-output-names = "osc32k"; 97 }; 98 99 iosc: internal-osc-clk { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <16000000>; 103 clock-accuracy = <300000000>; 104 clock-output-names = "iosc"; 105 }; 106 }; 107 108 de: display-engine { 109 compatible = "allwinner,sun8i-h3-display-engine"; 110 allwinner,pipelines = <&mixer0>; 111 status = "disabled"; 112 }; 113 114 soc { 115 compatible = "simple-bus"; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 display_clocks: clock@1000000 { 121 /* compatible is in per SoC .dtsi file */ 122 reg = <0x01000000 0x100000>; 123 clocks = <&ccu CLK_DE>, 124 <&ccu CLK_BUS_DE>; 125 clock-names = "mod", 126 "bus"; 127 resets = <&ccu RST_BUS_DE>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 mixer0: mixer@1100000 { 133 compatible = "allwinner,sun8i-h3-de2-mixer-0"; 134 reg = <0x01100000 0x100000>; 135 clocks = <&display_clocks CLK_BUS_MIXER0>, 136 <&display_clocks CLK_MIXER0>; 137 clock-names = "bus", 138 "mod"; 139 resets = <&display_clocks RST_MIXER0>; 140 141 ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 mixer0_out: port@1 { 146 reg = <1>; 147 148 mixer0_out_tcon0: endpoint { 149 remote-endpoint = <&tcon0_in_mixer0>; 150 }; 151 }; 152 }; 153 }; 154 155 syscon: syscon@1c00000 { 156 compatible = "allwinner,sun8i-h3-system-controller", 157 "syscon"; 158 reg = <0x01c00000 0x1000>; 159 }; 160 161 dma: dma-controller@1c02000 { 162 compatible = "allwinner,sun8i-h3-dma"; 163 reg = <0x01c02000 0x1000>; 164 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&ccu CLK_BUS_DMA>; 166 resets = <&ccu RST_BUS_DMA>; 167 #dma-cells = <1>; 168 }; 169 170 tcon0: lcd-controller@1c0c000 { 171 compatible = "allwinner,sun8i-h3-tcon-tv", 172 "allwinner,sun8i-a83t-tcon-tv"; 173 reg = <0x01c0c000 0x1000>; 174 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 176 clock-names = "ahb", "tcon-ch1"; 177 resets = <&ccu RST_BUS_TCON0>; 178 reset-names = "lcd"; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 tcon0_in: port@0 { 185 reg = <0>; 186 187 tcon0_in_mixer0: endpoint { 188 remote-endpoint = <&mixer0_out_tcon0>; 189 }; 190 }; 191 192 tcon0_out: port@1 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 reg = <1>; 196 197 tcon0_out_hdmi: endpoint@1 { 198 reg = <1>; 199 remote-endpoint = <&hdmi_in_tcon0>; 200 }; 201 }; 202 }; 203 }; 204 205 mmc0: mmc@1c0f000 { 206 /* compatible and clocks are in per SoC .dtsi file */ 207 reg = <0x01c0f000 0x1000>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&mmc0_pins>; 210 resets = <&ccu RST_BUS_MMC0>; 211 reset-names = "ahb"; 212 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 213 status = "disabled"; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 }; 217 218 mmc1: mmc@1c10000 { 219 /* compatible and clocks are in per SoC .dtsi file */ 220 reg = <0x01c10000 0x1000>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&mmc1_pins>; 223 resets = <&ccu RST_BUS_MMC1>; 224 reset-names = "ahb"; 225 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 226 status = "disabled"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 }; 230 231 mmc2: mmc@1c11000 { 232 /* compatible and clocks are in per SoC .dtsi file */ 233 reg = <0x01c11000 0x1000>; 234 resets = <&ccu RST_BUS_MMC2>; 235 reset-names = "ahb"; 236 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 237 status = "disabled"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 }; 241 242 usb_otg: usb@1c19000 { 243 compatible = "allwinner,sun8i-h3-musb"; 244 reg = <0x01c19000 0x400>; 245 clocks = <&ccu CLK_BUS_OTG>; 246 resets = <&ccu RST_BUS_OTG>; 247 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "mc"; 249 phys = <&usbphy 0>; 250 phy-names = "usb"; 251 extcon = <&usbphy 0>; 252 status = "disabled"; 253 }; 254 255 usbphy: phy@1c19400 { 256 compatible = "allwinner,sun8i-h3-usb-phy"; 257 reg = <0x01c19400 0x2c>, 258 <0x01c1a800 0x4>, 259 <0x01c1b800 0x4>, 260 <0x01c1c800 0x4>, 261 <0x01c1d800 0x4>; 262 reg-names = "phy_ctrl", 263 "pmu0", 264 "pmu1", 265 "pmu2", 266 "pmu3"; 267 clocks = <&ccu CLK_USB_PHY0>, 268 <&ccu CLK_USB_PHY1>, 269 <&ccu CLK_USB_PHY2>, 270 <&ccu CLK_USB_PHY3>; 271 clock-names = "usb0_phy", 272 "usb1_phy", 273 "usb2_phy", 274 "usb3_phy"; 275 resets = <&ccu RST_USB_PHY0>, 276 <&ccu RST_USB_PHY1>, 277 <&ccu RST_USB_PHY2>, 278 <&ccu RST_USB_PHY3>; 279 reset-names = "usb0_reset", 280 "usb1_reset", 281 "usb2_reset", 282 "usb3_reset"; 283 status = "disabled"; 284 #phy-cells = <1>; 285 }; 286 287 ehci0: usb@1c1a000 { 288 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 289 reg = <0x01c1a000 0x100>; 290 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 292 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 293 status = "disabled"; 294 }; 295 296 ohci0: usb@1c1a400 { 297 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 298 reg = <0x01c1a400 0x100>; 299 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 301 <&ccu CLK_USB_OHCI0>; 302 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 303 status = "disabled"; 304 }; 305 306 ehci1: usb@1c1b000 { 307 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 308 reg = <0x01c1b000 0x100>; 309 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 311 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 312 phys = <&usbphy 1>; 313 phy-names = "usb"; 314 status = "disabled"; 315 }; 316 317 ohci1: usb@1c1b400 { 318 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 319 reg = <0x01c1b400 0x100>; 320 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 322 <&ccu CLK_USB_OHCI1>; 323 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 324 phys = <&usbphy 1>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 ehci2: usb@1c1c000 { 330 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 331 reg = <0x01c1c000 0x100>; 332 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 334 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 335 phys = <&usbphy 2>; 336 phy-names = "usb"; 337 status = "disabled"; 338 }; 339 340 ohci2: usb@1c1c400 { 341 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 342 reg = <0x01c1c400 0x100>; 343 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 345 <&ccu CLK_USB_OHCI2>; 346 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 347 phys = <&usbphy 2>; 348 phy-names = "usb"; 349 status = "disabled"; 350 }; 351 352 ehci3: usb@1c1d000 { 353 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 354 reg = <0x01c1d000 0x100>; 355 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 357 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 358 phys = <&usbphy 3>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 ohci3: usb@1c1d400 { 364 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 365 reg = <0x01c1d400 0x100>; 366 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 368 <&ccu CLK_USB_OHCI3>; 369 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 370 phys = <&usbphy 3>; 371 phy-names = "usb"; 372 status = "disabled"; 373 }; 374 375 ccu: clock@1c20000 { 376 /* compatible is in per SoC .dtsi file */ 377 reg = <0x01c20000 0x400>; 378 clocks = <&osc24M>, <&osc32k>; 379 clock-names = "hosc", "losc"; 380 #clock-cells = <1>; 381 #reset-cells = <1>; 382 }; 383 384 pio: pinctrl@1c20800 { 385 /* compatible is in per SoC .dtsi file */ 386 reg = <0x01c20800 0x400>; 387 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 390 clock-names = "apb", "hosc", "losc"; 391 gpio-controller; 392 #gpio-cells = <3>; 393 interrupt-controller; 394 #interrupt-cells = <3>; 395 396 emac_rgmii_pins: emac0 { 397 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 398 "PD5", "PD7", "PD8", "PD9", "PD10", 399 "PD12", "PD13", "PD15", "PD16", "PD17"; 400 function = "emac"; 401 drive-strength = <40>; 402 }; 403 404 i2c0_pins: i2c0 { 405 pins = "PA11", "PA12"; 406 function = "i2c0"; 407 }; 408 409 i2c1_pins: i2c1 { 410 pins = "PA18", "PA19"; 411 function = "i2c1"; 412 }; 413 414 i2c2_pins: i2c2 { 415 pins = "PE12", "PE13"; 416 function = "i2c2"; 417 }; 418 419 mmc0_pins: mmc0 { 420 pins = "PF0", "PF1", "PF2", "PF3", 421 "PF4", "PF5"; 422 function = "mmc0"; 423 drive-strength = <30>; 424 bias-pull-up; 425 }; 426 427 mmc1_pins: mmc1 { 428 pins = "PG0", "PG1", "PG2", "PG3", 429 "PG4", "PG5"; 430 function = "mmc1"; 431 drive-strength = <30>; 432 bias-pull-up; 433 }; 434 435 mmc2_8bit_pins: mmc2_8bit { 436 pins = "PC5", "PC6", "PC8", 437 "PC9", "PC10", "PC11", 438 "PC12", "PC13", "PC14", 439 "PC15", "PC16"; 440 function = "mmc2"; 441 drive-strength = <30>; 442 bias-pull-up; 443 }; 444 445 spdif_tx_pins_a: spdif { 446 pins = "PA17"; 447 function = "spdif"; 448 }; 449 450 spi0_pins: spi0 { 451 pins = "PC0", "PC1", "PC2", "PC3"; 452 function = "spi0"; 453 }; 454 455 spi1_pins: spi1 { 456 pins = "PA15", "PA16", "PA14", "PA13"; 457 function = "spi1"; 458 }; 459 460 uart0_pins_a: uart0 { 461 pins = "PA4", "PA5"; 462 function = "uart0"; 463 }; 464 465 uart1_pins: uart1 { 466 pins = "PG6", "PG7"; 467 function = "uart1"; 468 }; 469 470 uart1_rts_cts_pins: uart1_rts_cts { 471 pins = "PG8", "PG9"; 472 function = "uart1"; 473 }; 474 475 uart2_pins: uart2 { 476 pins = "PA0", "PA1"; 477 function = "uart2"; 478 }; 479 480 uart3_pins: uart3 { 481 pins = "PA13", "PA14"; 482 function = "uart3"; 483 }; 484 485 uart3_rts_cts_pins: uart3_rts_cts { 486 pins = "PA15", "PA16"; 487 function = "uart3"; 488 }; 489 }; 490 491 timer@1c20c00 { 492 compatible = "allwinner,sun4i-a10-timer"; 493 reg = <0x01c20c00 0xa0>; 494 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&osc24M>; 497 }; 498 499 emac: ethernet@1c30000 { 500 compatible = "allwinner,sun8i-h3-emac"; 501 syscon = <&syscon>; 502 reg = <0x01c30000 0x10000>; 503 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "macirq"; 505 resets = <&ccu RST_BUS_EMAC>; 506 reset-names = "stmmaceth"; 507 clocks = <&ccu CLK_BUS_EMAC>; 508 clock-names = "stmmaceth"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 status = "disabled"; 512 513 mdio: mdio { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 compatible = "snps,dwmac-mdio"; 517 }; 518 519 mdio-mux { 520 compatible = "allwinner,sun8i-h3-mdio-mux"; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 mdio-parent-bus = <&mdio>; 525 /* Only one MDIO is usable at the time */ 526 internal_mdio: mdio@1 { 527 compatible = "allwinner,sun8i-h3-mdio-internal"; 528 reg = <1>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 int_mii_phy: ethernet-phy@1 { 533 compatible = "ethernet-phy-ieee802.3-c22"; 534 reg = <1>; 535 clocks = <&ccu CLK_BUS_EPHY>; 536 resets = <&ccu RST_BUS_EPHY>; 537 }; 538 }; 539 540 external_mdio: mdio@2 { 541 reg = <2>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 }; 545 }; 546 }; 547 548 spi0: spi@1c68000 { 549 compatible = "allwinner,sun8i-h3-spi"; 550 reg = <0x01c68000 0x1000>; 551 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 553 clock-names = "ahb", "mod"; 554 dmas = <&dma 23>, <&dma 23>; 555 dma-names = "rx", "tx"; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&spi0_pins>; 558 resets = <&ccu RST_BUS_SPI0>; 559 status = "disabled"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 }; 563 564 spi1: spi@1c69000 { 565 compatible = "allwinner,sun8i-h3-spi"; 566 reg = <0x01c69000 0x1000>; 567 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 569 clock-names = "ahb", "mod"; 570 dmas = <&dma 24>, <&dma 24>; 571 dma-names = "rx", "tx"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&spi1_pins>; 574 resets = <&ccu RST_BUS_SPI1>; 575 status = "disabled"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 }; 579 580 wdt0: watchdog@1c20ca0 { 581 compatible = "allwinner,sun6i-a31-wdt"; 582 reg = <0x01c20ca0 0x20>; 583 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 584 }; 585 586 spdif: spdif@1c21000 { 587 #sound-dai-cells = <0>; 588 compatible = "allwinner,sun8i-h3-spdif"; 589 reg = <0x01c21000 0x400>; 590 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 592 resets = <&ccu RST_BUS_SPDIF>; 593 clock-names = "apb", "spdif"; 594 dmas = <&dma 2>; 595 dma-names = "tx"; 596 status = "disabled"; 597 }; 598 599 pwm: pwm@1c21400 { 600 compatible = "allwinner,sun8i-h3-pwm"; 601 reg = <0x01c21400 0x8>; 602 clocks = <&osc24M>; 603 #pwm-cells = <3>; 604 status = "disabled"; 605 }; 606 607 i2s0: i2s@1c22000 { 608 #sound-dai-cells = <0>; 609 compatible = "allwinner,sun8i-h3-i2s"; 610 reg = <0x01c22000 0x400>; 611 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 613 clock-names = "apb", "mod"; 614 dmas = <&dma 3>, <&dma 3>; 615 resets = <&ccu RST_BUS_I2S0>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 i2s1: i2s@1c22400 { 621 #sound-dai-cells = <0>; 622 compatible = "allwinner,sun8i-h3-i2s"; 623 reg = <0x01c22400 0x400>; 624 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 626 clock-names = "apb", "mod"; 627 dmas = <&dma 4>, <&dma 4>; 628 resets = <&ccu RST_BUS_I2S1>; 629 dma-names = "rx", "tx"; 630 status = "disabled"; 631 }; 632 633 codec: codec@1c22c00 { 634 #sound-dai-cells = <0>; 635 compatible = "allwinner,sun8i-h3-codec"; 636 reg = <0x01c22c00 0x400>; 637 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 639 clock-names = "apb", "codec"; 640 resets = <&ccu RST_BUS_CODEC>; 641 dmas = <&dma 15>, <&dma 15>; 642 dma-names = "rx", "tx"; 643 allwinner,codec-analog-controls = <&codec_analog>; 644 status = "disabled"; 645 }; 646 647 uart0: serial@1c28000 { 648 compatible = "snps,dw-apb-uart"; 649 reg = <0x01c28000 0x400>; 650 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 651 reg-shift = <2>; 652 reg-io-width = <4>; 653 clocks = <&ccu CLK_BUS_UART0>; 654 resets = <&ccu RST_BUS_UART0>; 655 dmas = <&dma 6>, <&dma 6>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 uart1: serial@1c28400 { 661 compatible = "snps,dw-apb-uart"; 662 reg = <0x01c28400 0x400>; 663 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 664 reg-shift = <2>; 665 reg-io-width = <4>; 666 clocks = <&ccu CLK_BUS_UART1>; 667 resets = <&ccu RST_BUS_UART1>; 668 dmas = <&dma 7>, <&dma 7>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 uart2: serial@1c28800 { 674 compatible = "snps,dw-apb-uart"; 675 reg = <0x01c28800 0x400>; 676 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 677 reg-shift = <2>; 678 reg-io-width = <4>; 679 clocks = <&ccu CLK_BUS_UART2>; 680 resets = <&ccu RST_BUS_UART2>; 681 dmas = <&dma 8>, <&dma 8>; 682 dma-names = "rx", "tx"; 683 status = "disabled"; 684 }; 685 686 uart3: serial@1c28c00 { 687 compatible = "snps,dw-apb-uart"; 688 reg = <0x01c28c00 0x400>; 689 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 690 reg-shift = <2>; 691 reg-io-width = <4>; 692 clocks = <&ccu CLK_BUS_UART3>; 693 resets = <&ccu RST_BUS_UART3>; 694 dmas = <&dma 9>, <&dma 9>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 i2c0: i2c@1c2ac00 { 700 compatible = "allwinner,sun6i-a31-i2c"; 701 reg = <0x01c2ac00 0x400>; 702 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&ccu CLK_BUS_I2C0>; 704 resets = <&ccu RST_BUS_I2C0>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&i2c0_pins>; 707 status = "disabled"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 }; 711 712 i2c1: i2c@1c2b000 { 713 compatible = "allwinner,sun6i-a31-i2c"; 714 reg = <0x01c2b000 0x400>; 715 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&ccu CLK_BUS_I2C1>; 717 resets = <&ccu RST_BUS_I2C1>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&i2c1_pins>; 720 status = "disabled"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 }; 724 725 i2c2: i2c@1c2b400 { 726 compatible = "allwinner,sun6i-a31-i2c"; 727 reg = <0x01c2b400 0x400>; 728 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_I2C2>; 730 resets = <&ccu RST_BUS_I2C2>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&i2c2_pins>; 733 status = "disabled"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 }; 737 738 gic: interrupt-controller@1c81000 { 739 compatible = "arm,gic-400"; 740 reg = <0x01c81000 0x1000>, 741 <0x01c82000 0x2000>, 742 <0x01c84000 0x2000>, 743 <0x01c86000 0x2000>; 744 interrupt-controller; 745 #interrupt-cells = <3>; 746 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 747 }; 748 749 hdmi: hdmi@1ee0000 { 750 compatible = "allwinner,sun8i-h3-dw-hdmi", 751 "allwinner,sun8i-a83t-dw-hdmi"; 752 reg = <0x01ee0000 0x10000>; 753 reg-io-width = <1>; 754 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 756 <&ccu CLK_HDMI>; 757 clock-names = "iahb", "isfr", "tmds"; 758 resets = <&ccu RST_BUS_HDMI1>; 759 reset-names = "ctrl"; 760 phys = <&hdmi_phy>; 761 phy-names = "hdmi-phy"; 762 status = "disabled"; 763 764 ports { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 hdmi_in: port@0 { 769 reg = <0>; 770 771 hdmi_in_tcon0: endpoint { 772 remote-endpoint = <&tcon0_out_hdmi>; 773 }; 774 }; 775 776 hdmi_out: port@1 { 777 reg = <1>; 778 }; 779 }; 780 }; 781 782 hdmi_phy: hdmi-phy@1ef0000 { 783 compatible = "allwinner,sun8i-h3-hdmi-phy"; 784 reg = <0x01ef0000 0x10000>; 785 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 786 <&ccu 6>; 787 clock-names = "bus", "mod", "pll-0"; 788 resets = <&ccu RST_BUS_HDMI0>; 789 reset-names = "phy"; 790 #phy-cells = <0>; 791 }; 792 793 rtc: rtc@1f00000 { 794 compatible = "allwinner,sun6i-a31-rtc"; 795 reg = <0x01f00000 0x54>; 796 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 798 }; 799 800 r_ccu: clock@1f01400 { 801 compatible = "allwinner,sun8i-h3-r-ccu"; 802 reg = <0x01f01400 0x100>; 803 clocks = <&osc24M>, <&osc32k>, <&iosc>, 804 <&ccu 9>; 805 clock-names = "hosc", "losc", "iosc", "pll-periph"; 806 #clock-cells = <1>; 807 #reset-cells = <1>; 808 }; 809 810 codec_analog: codec-analog@1f015c0 { 811 compatible = "allwinner,sun8i-h3-codec-analog"; 812 reg = <0x01f015c0 0x4>; 813 }; 814 815 ir: ir@1f02000 { 816 compatible = "allwinner,sun5i-a13-ir"; 817 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 818 clock-names = "apb", "ir"; 819 resets = <&r_ccu RST_APB0_IR>; 820 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 821 reg = <0x01f02000 0x40>; 822 status = "disabled"; 823 }; 824 825 r_i2c: i2c@1f02400 { 826 compatible = "allwinner,sun6i-a31-i2c"; 827 reg = <0x01f02400 0x400>; 828 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&r_i2c_pins>; 831 clocks = <&r_ccu CLK_APB0_I2C>; 832 resets = <&r_ccu RST_APB0_I2C>; 833 status = "disabled"; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 }; 837 838 r_pio: pinctrl@1f02c00 { 839 compatible = "allwinner,sun8i-h3-r-pinctrl"; 840 reg = <0x01f02c00 0x400>; 841 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 843 clock-names = "apb", "hosc", "losc"; 844 gpio-controller; 845 #gpio-cells = <3>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 849 ir_pins_a: ir { 850 pins = "PL11"; 851 function = "s_cir_rx"; 852 }; 853 854 r_i2c_pins: r-i2c { 855 pins = "PL0", "PL1"; 856 function = "s_i2c"; 857 }; 858 }; 859 }; 860}; 861