1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton64.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/pinctrl/sun4i-a10.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a7"; 60 device_type = "cpu"; 61 reg = <0x0>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a7"; 66 device_type = "cpu"; 67 reg = <0x1>; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a7"; 72 device_type = "cpu"; 73 reg = <0x2>; 74 }; 75 76 cpu3: cpu@3 { 77 compatible = "arm,cortex-a7"; 78 device_type = "cpu"; 79 reg = <0x3>; 80 }; 81 82 cpu4: cpu@100 { 83 compatible = "arm,cortex-a15"; 84 device_type = "cpu"; 85 reg = <0x100>; 86 }; 87 88 cpu5: cpu@101 { 89 compatible = "arm,cortex-a15"; 90 device_type = "cpu"; 91 reg = <0x101>; 92 }; 93 94 cpu6: cpu@102 { 95 compatible = "arm,cortex-a15"; 96 device_type = "cpu"; 97 reg = <0x102>; 98 }; 99 100 cpu7: cpu@103 { 101 compatible = "arm,cortex-a15"; 102 device_type = "cpu"; 103 reg = <0x103>; 104 }; 105 }; 106 107 memory { 108 /* 8GB max. with LPAE */ 109 reg = <0 0x20000000 0x02 0>; 110 }; 111 112 timer { 113 compatible = "arm,armv7-timer"; 114 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 118 clock-frequency = <24000000>; 119 arm,cpu-registers-not-fw-configured; 120 }; 121 122 clocks { 123 #address-cells = <1>; 124 #size-cells = <1>; 125 /* 126 * map 64 bit address range down to 32 bits, 127 * as the peripherals are all under 512MB. 128 */ 129 ranges = <0 0 0 0x20000000>; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 usb_mod_clk: clk@00a08000 { 146 #clock-cells = <1>; 147 #reset-cells = <1>; 148 compatible = "allwinner,sun9i-a80-usb-mod-clk"; 149 reg = <0x00a08000 0x4>; 150 clocks = <&ahb1_gates 1>; 151 clock-output-names = "usb0_ahb", "usb_ohci0", 152 "usb1_ahb", "usb_ohci1", 153 "usb2_ahb", "usb_ohci2"; 154 }; 155 156 usb_phy_clk: clk@00a08004 { 157 #clock-cells = <1>; 158 #reset-cells = <1>; 159 compatible = "allwinner,sun9i-a80-usb-phy-clk"; 160 reg = <0x00a08004 0x4>; 161 clocks = <&ahb1_gates 1>; 162 clock-output-names = "usb_phy0", "usb_hsic1_480M", 163 "usb_phy1", "usb_hsic2_480M", 164 "usb_phy2", "usb_hsic_12M"; 165 }; 166 167 pll4: clk@0600000c { 168 #clock-cells = <0>; 169 compatible = "allwinner,sun9i-a80-pll4-clk"; 170 reg = <0x0600000c 0x4>; 171 clocks = <&osc24M>; 172 clock-output-names = "pll4"; 173 }; 174 175 pll12: clk@0600002c { 176 #clock-cells = <0>; 177 compatible = "allwinner,sun9i-a80-pll4-clk"; 178 reg = <0x0600002c 0x4>; 179 clocks = <&osc24M>; 180 clock-output-names = "pll12"; 181 }; 182 183 gt_clk: clk@0600005c { 184 #clock-cells = <0>; 185 compatible = "allwinner,sun9i-a80-gt-clk"; 186 reg = <0x0600005c 0x4>; 187 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; 188 clock-output-names = "gt"; 189 }; 190 191 ahb0: clk@06000060 { 192 #clock-cells = <0>; 193 compatible = "allwinner,sun9i-a80-ahb-clk"; 194 reg = <0x06000060 0x4>; 195 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; 196 clock-output-names = "ahb0"; 197 }; 198 199 ahb1: clk@06000064 { 200 #clock-cells = <0>; 201 compatible = "allwinner,sun9i-a80-ahb-clk"; 202 reg = <0x06000064 0x4>; 203 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; 204 clock-output-names = "ahb1"; 205 }; 206 207 ahb2: clk@06000068 { 208 #clock-cells = <0>; 209 compatible = "allwinner,sun9i-a80-ahb-clk"; 210 reg = <0x06000068 0x4>; 211 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; 212 clock-output-names = "ahb2"; 213 }; 214 215 apb0: clk@06000070 { 216 #clock-cells = <0>; 217 compatible = "allwinner,sun9i-a80-apb0-clk"; 218 reg = <0x06000070 0x4>; 219 clocks = <&osc24M>, <&pll4>; 220 clock-output-names = "apb0"; 221 }; 222 223 apb1: clk@06000074 { 224 #clock-cells = <0>; 225 compatible = "allwinner,sun9i-a80-apb1-clk"; 226 reg = <0x06000074 0x4>; 227 clocks = <&osc24M>, <&pll4>; 228 clock-output-names = "apb1"; 229 }; 230 231 cci400_clk: clk@06000078 { 232 #clock-cells = <0>; 233 compatible = "allwinner,sun9i-a80-gt-clk"; 234 reg = <0x06000078 0x4>; 235 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; 236 clock-output-names = "cci400"; 237 }; 238 239 mmc0_clk: clk@06000410 { 240 #clock-cells = <1>; 241 compatible = "allwinner,sun9i-a80-mmc-clk"; 242 reg = <0x06000410 0x4>; 243 clocks = <&osc24M>, <&pll4>; 244 clock-output-names = "mmc0", "mmc0_output", 245 "mmc0_sample"; 246 }; 247 248 mmc1_clk: clk@06000414 { 249 #clock-cells = <1>; 250 compatible = "allwinner,sun9i-a80-mmc-clk"; 251 reg = <0x06000414 0x4>; 252 clocks = <&osc24M>, <&pll4>; 253 clock-output-names = "mmc1", "mmc1_output", 254 "mmc1_sample"; 255 }; 256 257 mmc2_clk: clk@06000418 { 258 #clock-cells = <1>; 259 compatible = "allwinner,sun9i-a80-mmc-clk"; 260 reg = <0x06000418 0x4>; 261 clocks = <&osc24M>, <&pll4>; 262 clock-output-names = "mmc2", "mmc2_output", 263 "mmc2_sample"; 264 }; 265 266 mmc3_clk: clk@0600041c { 267 #clock-cells = <1>; 268 compatible = "allwinner,sun9i-a80-mmc-clk"; 269 reg = <0x0600041c 0x4>; 270 clocks = <&osc24M>, <&pll4>; 271 clock-output-names = "mmc3", "mmc3_output", 272 "mmc3_sample"; 273 }; 274 275 ahb0_gates: clk@06000580 { 276 #clock-cells = <1>; 277 compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; 278 reg = <0x06000580 0x4>; 279 clocks = <&ahb0>; 280 clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>, 281 <14>, <15>, <16>, <18>, <20>, <21>, 282 <22>, <23>; 283 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", 284 "ahb0_ss", "ahb0_sd", "ahb0_nand1", 285 "ahb0_nand0", "ahb0_sdram", 286 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", 287 "ahb0_spi0", "ahb0_spi1", "ahb0_spi2", 288 "ahb0_spi3"; 289 }; 290 291 ahb1_gates: clk@06000584 { 292 #clock-cells = <1>; 293 compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; 294 reg = <0x06000584 0x4>; 295 clocks = <&ahb1>; 296 clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>; 297 clock-output-names = "ahb1_usbotg", "ahb1_usbhci", 298 "ahb1_gmac", "ahb1_msgbox", 299 "ahb1_spinlock", "ahb1_hstimer", 300 "ahb1_dma"; 301 }; 302 303 ahb2_gates: clk@06000588 { 304 #clock-cells = <1>; 305 compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; 306 reg = <0x06000588 0x4>; 307 clocks = <&ahb2>; 308 clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>, 309 <11>; 310 clock-output-names = "ahb2_lcd0", "ahb2_lcd1", 311 "ahb2_edp", "ahb2_csi", "ahb2_hdmi", 312 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; 313 }; 314 315 apb0_gates: clk@06000590 { 316 #clock-cells = <1>; 317 compatible = "allwinner,sun9i-a80-apb0-gates-clk"; 318 reg = <0x06000590 0x4>; 319 clocks = <&apb0>; 320 clock-indices = <1>, <5>, <11>, <12>, <13>, <15>, 321 <17>, <18>, <19>; 322 clock-output-names = "apb0_spdif", "apb0_pio", 323 "apb0_ac97", "apb0_i2s0", "apb0_i2s1", 324 "apb0_lradc", "apb0_gpadc", "apb0_twd", 325 "apb0_cirtx"; 326 }; 327 328 apb1_gates: clk@06000594 { 329 #clock-cells = <1>; 330 compatible = "allwinner,sun9i-a80-apb1-gates-clk"; 331 reg = <0x06000594 0x4>; 332 clocks = <&apb1>; 333 clock-indices = <0>, <1>, <2>, <3>, <4>, 334 <16>, <17>, <18>, <19>, <20>, <21>; 335 clock-output-names = "apb1_i2c0", "apb1_i2c1", 336 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", 337 "apb1_uart0", "apb1_uart1", 338 "apb1_uart2", "apb1_uart3", 339 "apb1_uart4", "apb1_uart5"; 340 }; 341 }; 342 343 soc { 344 compatible = "simple-bus"; 345 #address-cells = <1>; 346 #size-cells = <1>; 347 /* 348 * map 64 bit address range down to 32 bits, 349 * as the peripherals are all under 512MB. 350 */ 351 ranges = <0 0 0 0x20000000>; 352 353 ehci0: usb@00a00000 { 354 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 355 reg = <0x00a00000 0x100>; 356 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&usb_mod_clk 1>; 358 resets = <&usb_mod_clk 17>; 359 phys = <&usbphy1>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 ohci0: usb@00a00400 { 365 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 366 reg = <0x00a00400 0x100>; 367 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; 369 resets = <&usb_mod_clk 17>; 370 phys = <&usbphy1>; 371 phy-names = "usb"; 372 status = "disabled"; 373 }; 374 375 usbphy1: phy@00a00800 { 376 compatible = "allwinner,sun9i-a80-usb-phy"; 377 reg = <0x00a00800 0x4>; 378 clocks = <&usb_phy_clk 1>; 379 clock-names = "phy"; 380 resets = <&usb_phy_clk 17>; 381 reset-names = "phy"; 382 status = "disabled"; 383 #phy-cells = <0>; 384 }; 385 386 ehci1: usb@00a01000 { 387 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 388 reg = <0x00a01000 0x100>; 389 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&usb_mod_clk 3>; 391 resets = <&usb_mod_clk 18>; 392 phys = <&usbphy2>; 393 phy-names = "usb"; 394 status = "disabled"; 395 }; 396 397 usbphy2: phy@00a01800 { 398 compatible = "allwinner,sun9i-a80-usb-phy"; 399 reg = <0x00a01800 0x4>; 400 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, 401 <&usb_phy_clk 3>; 402 clock-names = "hsic_480M", "hsic_12M", "phy"; 403 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; 404 reset-names = "hsic", "phy"; 405 status = "disabled"; 406 #phy-cells = <0>; 407 /* usb1 is always used with HSIC */ 408 phy_type = "hsic"; 409 }; 410 411 ehci2: usb@00a02000 { 412 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 413 reg = <0x00a02000 0x100>; 414 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&usb_mod_clk 5>; 416 resets = <&usb_mod_clk 19>; 417 phys = <&usbphy3>; 418 phy-names = "usb"; 419 status = "disabled"; 420 }; 421 422 ohci2: usb@00a02400 { 423 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 424 reg = <0x00a02400 0x100>; 425 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; 427 resets = <&usb_mod_clk 19>; 428 phys = <&usbphy3>; 429 phy-names = "usb"; 430 status = "disabled"; 431 }; 432 433 usbphy3: phy@00a02800 { 434 compatible = "allwinner,sun9i-a80-usb-phy"; 435 reg = <0x00a02800 0x4>; 436 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, 437 <&usb_phy_clk 5>; 438 clock-names = "hsic_480M", "hsic_12M", "phy"; 439 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; 440 reset-names = "hsic", "phy"; 441 status = "disabled"; 442 #phy-cells = <0>; 443 }; 444 445 mmc0: mmc@01c0f000 { 446 compatible = "allwinner,sun5i-a13-mmc"; 447 reg = <0x01c0f000 0x1000>; 448 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, 449 <&mmc0_clk 1>, <&mmc0_clk 2>; 450 clock-names = "ahb", "mmc", "output", "sample"; 451 resets = <&mmc_config_clk 0>; 452 reset-names = "ahb"; 453 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 454 status = "disabled"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 }; 458 459 mmc1: mmc@01c10000 { 460 compatible = "allwinner,sun5i-a13-mmc"; 461 reg = <0x01c10000 0x1000>; 462 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, 463 <&mmc1_clk 1>, <&mmc1_clk 2>; 464 clock-names = "ahb", "mmc", "output", "sample"; 465 resets = <&mmc_config_clk 1>; 466 reset-names = "ahb"; 467 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 468 status = "disabled"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 }; 472 473 mmc2: mmc@01c11000 { 474 compatible = "allwinner,sun5i-a13-mmc"; 475 reg = <0x01c11000 0x1000>; 476 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, 477 <&mmc2_clk 1>, <&mmc2_clk 2>; 478 clock-names = "ahb", "mmc", "output", "sample"; 479 resets = <&mmc_config_clk 2>; 480 reset-names = "ahb"; 481 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 482 status = "disabled"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 }; 486 487 mmc3: mmc@01c12000 { 488 compatible = "allwinner,sun5i-a13-mmc"; 489 reg = <0x01c12000 0x1000>; 490 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, 491 <&mmc3_clk 1>, <&mmc3_clk 2>; 492 clock-names = "ahb", "mmc", "output", "sample"; 493 resets = <&mmc_config_clk 3>; 494 reset-names = "ahb"; 495 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 496 status = "disabled"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 }; 500 501 mmc_config_clk: clk@01c13000 { 502 compatible = "allwinner,sun9i-a80-mmc-config-clk"; 503 reg = <0x01c13000 0x10>; 504 clocks = <&ahb0_gates 8>; 505 clock-names = "ahb"; 506 resets = <&ahb0_resets 8>; 507 reset-names = "ahb"; 508 #clock-cells = <1>; 509 #reset-cells = <1>; 510 clock-output-names = "mmc0_config", "mmc1_config", 511 "mmc2_config", "mmc3_config"; 512 }; 513 514 gic: interrupt-controller@01c41000 { 515 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 516 reg = <0x01c41000 0x1000>, 517 <0x01c42000 0x1000>, 518 <0x01c44000 0x2000>, 519 <0x01c46000 0x2000>; 520 interrupt-controller; 521 #interrupt-cells = <3>; 522 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 523 }; 524 525 ahb0_resets: reset@060005a0 { 526 #reset-cells = <1>; 527 compatible = "allwinner,sun6i-a31-clock-reset"; 528 reg = <0x060005a0 0x4>; 529 }; 530 531 ahb1_resets: reset@060005a4 { 532 #reset-cells = <1>; 533 compatible = "allwinner,sun6i-a31-clock-reset"; 534 reg = <0x060005a4 0x4>; 535 }; 536 537 ahb2_resets: reset@060005a8 { 538 #reset-cells = <1>; 539 compatible = "allwinner,sun6i-a31-clock-reset"; 540 reg = <0x060005a8 0x4>; 541 }; 542 543 apb0_resets: reset@060005b0 { 544 #reset-cells = <1>; 545 compatible = "allwinner,sun6i-a31-clock-reset"; 546 reg = <0x060005b0 0x4>; 547 }; 548 549 apb1_resets: reset@060005b4 { 550 #reset-cells = <1>; 551 compatible = "allwinner,sun6i-a31-clock-reset"; 552 reg = <0x060005b4 0x4>; 553 }; 554 555 timer@06000c00 { 556 compatible = "allwinner,sun4i-a10-timer"; 557 reg = <0x06000c00 0xa0>; 558 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 564 565 clocks = <&osc24M>; 566 }; 567 568 wdt: watchdog@06000ca0 { 569 compatible = "allwinner,sun6i-a31-wdt"; 570 reg = <0x06000ca0 0x20>; 571 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 572 }; 573 574 pio: pinctrl@06000800 { 575 compatible = "allwinner,sun9i-a80-pinctrl"; 576 reg = <0x06000800 0x400>; 577 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&apb0_gates 5>; 583 gpio-controller; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 #size-cells = <0>; 587 #gpio-cells = <3>; 588 589 i2c3_pins_a: i2c3@0 { 590 allwinner,pins = "PG10", "PG11"; 591 allwinner,function = "i2c3"; 592 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 593 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 594 }; 595 596 mmc0_pins: mmc0 { 597 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3", 598 "PF4", "PF5"; 599 allwinner,function = "mmc0"; 600 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 601 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 602 }; 603 604 mmc2_8bit_pins: mmc2_8bit { 605 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 606 "PC10", "PC11", "PC12", 607 "PC13", "PC14", "PC15"; 608 allwinner,function = "mmc2"; 609 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 610 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 611 }; 612 613 uart0_pins_a: uart0@0 { 614 allwinner,pins = "PH12", "PH13"; 615 allwinner,function = "uart0"; 616 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 617 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 618 }; 619 620 uart4_pins_a: uart4@0 { 621 allwinner,pins = "PG12", "PG13", "PG14", "PG15"; 622 allwinner,function = "uart4"; 623 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 624 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 625 }; 626 }; 627 628 uart0: serial@07000000 { 629 compatible = "snps,dw-apb-uart"; 630 reg = <0x07000000 0x400>; 631 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 632 reg-shift = <2>; 633 reg-io-width = <4>; 634 clocks = <&apb1_gates 16>; 635 resets = <&apb1_resets 16>; 636 status = "disabled"; 637 }; 638 639 uart1: serial@07000400 { 640 compatible = "snps,dw-apb-uart"; 641 reg = <0x07000400 0x400>; 642 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 643 reg-shift = <2>; 644 reg-io-width = <4>; 645 clocks = <&apb1_gates 17>; 646 resets = <&apb1_resets 17>; 647 status = "disabled"; 648 }; 649 650 uart2: serial@07000800 { 651 compatible = "snps,dw-apb-uart"; 652 reg = <0x07000800 0x400>; 653 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 654 reg-shift = <2>; 655 reg-io-width = <4>; 656 clocks = <&apb1_gates 18>; 657 resets = <&apb1_resets 18>; 658 status = "disabled"; 659 }; 660 661 uart3: serial@07000c00 { 662 compatible = "snps,dw-apb-uart"; 663 reg = <0x07000c00 0x400>; 664 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 665 reg-shift = <2>; 666 reg-io-width = <4>; 667 clocks = <&apb1_gates 19>; 668 resets = <&apb1_resets 19>; 669 status = "disabled"; 670 }; 671 672 uart4: serial@07001000 { 673 compatible = "snps,dw-apb-uart"; 674 reg = <0x07001000 0x400>; 675 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 676 reg-shift = <2>; 677 reg-io-width = <4>; 678 clocks = <&apb1_gates 20>; 679 resets = <&apb1_resets 20>; 680 status = "disabled"; 681 }; 682 683 uart5: serial@07001400 { 684 compatible = "snps,dw-apb-uart"; 685 reg = <0x07001400 0x400>; 686 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 687 reg-shift = <2>; 688 reg-io-width = <4>; 689 clocks = <&apb1_gates 21>; 690 resets = <&apb1_resets 21>; 691 status = "disabled"; 692 }; 693 694 i2c0: i2c@07002800 { 695 compatible = "allwinner,sun6i-a31-i2c"; 696 reg = <0x07002800 0x400>; 697 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&apb1_gates 0>; 699 resets = <&apb1_resets 0>; 700 status = "disabled"; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 }; 704 705 i2c1: i2c@07002c00 { 706 compatible = "allwinner,sun6i-a31-i2c"; 707 reg = <0x07002c00 0x400>; 708 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&apb1_gates 1>; 710 resets = <&apb1_resets 1>; 711 status = "disabled"; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 }; 715 716 i2c2: i2c@07003000 { 717 compatible = "allwinner,sun6i-a31-i2c"; 718 reg = <0x07003000 0x400>; 719 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&apb1_gates 2>; 721 resets = <&apb1_resets 2>; 722 status = "disabled"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 }; 726 727 i2c3: i2c@07003400 { 728 compatible = "allwinner,sun6i-a31-i2c"; 729 reg = <0x07003400 0x400>; 730 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&apb1_gates 3>; 732 resets = <&apb1_resets 3>; 733 status = "disabled"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 }; 737 738 i2c4: i2c@07003800 { 739 compatible = "allwinner,sun6i-a31-i2c"; 740 reg = <0x07003800 0x400>; 741 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&apb1_gates 4>; 743 resets = <&apb1_resets 4>; 744 status = "disabled"; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 }; 748 749 r_wdt: watchdog@08001000 { 750 compatible = "allwinner,sun6i-a31-wdt"; 751 reg = <0x08001000 0x20>; 752 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 753 }; 754 755 r_uart: serial@08002800 { 756 compatible = "snps,dw-apb-uart"; 757 reg = <0x08002800 0x400>; 758 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 759 reg-shift = <2>; 760 reg-io-width = <4>; 761 clocks = <&osc24M>; 762 status = "disabled"; 763 }; 764 }; 765}; 766