1/* 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/clock/sun8i-r40-ccu.h> 46#include <dt-bindings/reset/sun8i-r40-ccu.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 interrupt-parent = <&gic>; 52 53 clocks { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges; 57 58 osc24M: osc24M { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <24000000>; 62 clock-output-names = "osc24M"; 63 }; 64 65 osc32k: osc32k { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <32768>; 69 clock-output-names = "osc32k"; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu@0 { 78 compatible = "arm,cortex-a7"; 79 device_type = "cpu"; 80 reg = <0>; 81 }; 82 83 cpu@1 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <1>; 87 }; 88 89 cpu@2 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <2>; 93 }; 94 95 cpu@3 { 96 compatible = "arm,cortex-a7"; 97 device_type = "cpu"; 98 reg = <3>; 99 }; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges; 107 108 nmi_intc: interrupt-controller@1c00030 { 109 compatible = "allwinner,sun7i-a20-sc-nmi"; 110 interrupt-controller; 111 #interrupt-cells = <2>; 112 reg = <0x01c00030 0x0c>; 113 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 mmc0: mmc@1c0f000 { 117 compatible = "allwinner,sun8i-r40-mmc", 118 "allwinner,sun50i-a64-mmc"; 119 reg = <0x01c0f000 0x1000>; 120 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 121 clock-names = "ahb", "mmc"; 122 resets = <&ccu RST_BUS_MMC0>; 123 reset-names = "ahb"; 124 pinctrl-0 = <&mmc0_pins>; 125 pinctrl-names = "default"; 126 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 127 status = "disabled"; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 132 mmc1: mmc@1c10000 { 133 compatible = "allwinner,sun8i-r40-mmc", 134 "allwinner,sun50i-a64-mmc"; 135 reg = <0x01c10000 0x1000>; 136 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 137 clock-names = "ahb", "mmc"; 138 resets = <&ccu RST_BUS_MMC1>; 139 reset-names = "ahb"; 140 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 141 status = "disabled"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 }; 145 146 mmc2: mmc@1c11000 { 147 compatible = "allwinner,sun8i-r40-emmc", 148 "allwinner,sun50i-a64-emmc"; 149 reg = <0x01c11000 0x1000>; 150 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 151 clock-names = "ahb", "mmc"; 152 resets = <&ccu RST_BUS_MMC2>; 153 reset-names = "ahb"; 154 pinctrl-0 = <&mmc2_pins>; 155 pinctrl-names = "default"; 156 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 157 status = "disabled"; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 }; 161 162 mmc3: mmc@1c12000 { 163 compatible = "allwinner,sun8i-r40-mmc", 164 "allwinner,sun50i-a64-mmc"; 165 reg = <0x01c12000 0x1000>; 166 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 167 clock-names = "ahb", "mmc"; 168 resets = <&ccu RST_BUS_MMC3>; 169 reset-names = "ahb"; 170 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 171 status = "disabled"; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 }; 175 176 usbphy: phy@1c13400 { 177 compatible = "allwinner,sun8i-r40-usb-phy"; 178 reg = <0x01c13400 0x14>, 179 <0x01c14800 0x4>, 180 <0x01c19800 0x4>, 181 <0x01c1c800 0x4>; 182 reg-names = "phy_ctrl", 183 "pmu0", 184 "pmu1", 185 "pmu2"; 186 clocks = <&ccu CLK_USB_PHY0>, 187 <&ccu CLK_USB_PHY1>, 188 <&ccu CLK_USB_PHY2>; 189 clock-names = "usb0_phy", 190 "usb1_phy", 191 "usb2_phy"; 192 resets = <&ccu RST_USB_PHY0>, 193 <&ccu RST_USB_PHY1>, 194 <&ccu RST_USB_PHY2>; 195 reset-names = "usb0_reset", 196 "usb1_reset", 197 "usb2_reset"; 198 status = "disabled"; 199 #phy-cells = <1>; 200 }; 201 202 ehci1: usb@1c19000 { 203 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 204 reg = <0x01c19000 0x100>; 205 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&ccu CLK_BUS_EHCI1>; 207 resets = <&ccu RST_BUS_EHCI1>; 208 phys = <&usbphy 1>; 209 phy-names = "usb"; 210 status = "disabled"; 211 }; 212 213 ohci1: usb@1c19400 { 214 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 215 reg = <0x01c19400 0x100>; 216 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&ccu CLK_BUS_OHCI1>, 218 <&ccu CLK_USB_OHCI1>; 219 resets = <&ccu RST_BUS_OHCI1>; 220 phys = <&usbphy 1>; 221 phy-names = "usb"; 222 status = "disabled"; 223 }; 224 225 ehci2: usb@1c1c000 { 226 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 227 reg = <0x01c1c000 0x100>; 228 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&ccu CLK_BUS_EHCI2>; 230 resets = <&ccu RST_BUS_EHCI2>; 231 phys = <&usbphy 2>; 232 phy-names = "usb"; 233 status = "disabled"; 234 }; 235 236 ohci2: usb@1c1c400 { 237 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 238 reg = <0x01c1c400 0x100>; 239 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&ccu CLK_BUS_OHCI2>, 241 <&ccu CLK_USB_OHCI2>; 242 resets = <&ccu RST_BUS_OHCI2>; 243 phys = <&usbphy 2>; 244 phy-names = "usb"; 245 status = "disabled"; 246 }; 247 248 ccu: clock@1c20000 { 249 compatible = "allwinner,sun8i-r40-ccu"; 250 reg = <0x01c20000 0x400>; 251 clocks = <&osc24M>, <&osc32k>; 252 clock-names = "hosc", "losc"; 253 #clock-cells = <1>; 254 #reset-cells = <1>; 255 }; 256 257 pio: pinctrl@1c20800 { 258 compatible = "allwinner,sun8i-r40-pinctrl"; 259 reg = <0x01c20800 0x400>; 260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 262 clock-names = "apb", "hosc", "losc"; 263 gpio-controller; 264 interrupt-controller; 265 #interrupt-cells = <3>; 266 #gpio-cells = <3>; 267 268 gmac_rgmii_pins: gmac-rgmii-pins { 269 pins = "PA0", "PA1", "PA2", "PA3", 270 "PA4", "PA5", "PA6", "PA7", 271 "PA8", "PA10", "PA11", "PA12", 272 "PA13", "PA15", "PA16"; 273 function = "gmac"; 274 /* 275 * data lines in RGMII mode use DDR mode 276 * and need a higher signal drive strength 277 */ 278 drive-strength = <40>; 279 }; 280 281 i2c0_pins: i2c0-pins { 282 pins = "PB0", "PB1"; 283 function = "i2c0"; 284 }; 285 286 mmc0_pins: mmc0-pins { 287 pins = "PF0", "PF1", "PF2", 288 "PF3", "PF4", "PF5"; 289 function = "mmc0"; 290 drive-strength = <30>; 291 bias-pull-up; 292 }; 293 294 mmc1_pg_pins: mmc1-pg-pins { 295 pins = "PG0", "PG1", "PG2", 296 "PG3", "PG4", "PG5"; 297 function = "mmc1"; 298 drive-strength = <30>; 299 bias-pull-up; 300 }; 301 302 mmc2_pins: mmc2-pins { 303 pins = "PC5", "PC6", "PC7", "PC8", "PC9", 304 "PC10", "PC11", "PC12", "PC13", "PC14", 305 "PC15", "PC24"; 306 function = "mmc2"; 307 drive-strength = <30>; 308 bias-pull-up; 309 }; 310 311 uart0_pb_pins: uart0-pb-pins { 312 pins = "PB22", "PB23"; 313 function = "uart0"; 314 }; 315 }; 316 317 wdt: watchdog@1c20c90 { 318 compatible = "allwinner,sun4i-a10-wdt"; 319 reg = <0x01c20c90 0x10>; 320 }; 321 322 uart0: serial@1c28000 { 323 compatible = "snps,dw-apb-uart"; 324 reg = <0x01c28000 0x400>; 325 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 326 reg-shift = <2>; 327 reg-io-width = <4>; 328 clocks = <&ccu CLK_BUS_UART0>; 329 resets = <&ccu RST_BUS_UART0>; 330 status = "disabled"; 331 }; 332 333 uart1: serial@1c28400 { 334 compatible = "snps,dw-apb-uart"; 335 reg = <0x01c28400 0x400>; 336 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 337 reg-shift = <2>; 338 reg-io-width = <4>; 339 clocks = <&ccu CLK_BUS_UART1>; 340 resets = <&ccu RST_BUS_UART1>; 341 status = "disabled"; 342 }; 343 344 uart2: serial@1c28800 { 345 compatible = "snps,dw-apb-uart"; 346 reg = <0x01c28800 0x400>; 347 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 clocks = <&ccu CLK_BUS_UART2>; 351 resets = <&ccu RST_BUS_UART2>; 352 status = "disabled"; 353 }; 354 355 uart3: serial@1c28c00 { 356 compatible = "snps,dw-apb-uart"; 357 reg = <0x01c28c00 0x400>; 358 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 359 reg-shift = <2>; 360 reg-io-width = <4>; 361 clocks = <&ccu CLK_BUS_UART3>; 362 resets = <&ccu RST_BUS_UART3>; 363 status = "disabled"; 364 }; 365 366 uart4: serial@1c29000 { 367 compatible = "snps,dw-apb-uart"; 368 reg = <0x01c29000 0x400>; 369 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 370 reg-shift = <2>; 371 reg-io-width = <4>; 372 clocks = <&ccu CLK_BUS_UART4>; 373 resets = <&ccu RST_BUS_UART4>; 374 status = "disabled"; 375 }; 376 377 uart5: serial@1c29400 { 378 compatible = "snps,dw-apb-uart"; 379 reg = <0x01c29400 0x400>; 380 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 clocks = <&ccu CLK_BUS_UART5>; 384 resets = <&ccu RST_BUS_UART5>; 385 status = "disabled"; 386 }; 387 388 uart6: serial@1c29800 { 389 compatible = "snps,dw-apb-uart"; 390 reg = <0x01c29800 0x400>; 391 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 392 reg-shift = <2>; 393 reg-io-width = <4>; 394 clocks = <&ccu CLK_BUS_UART6>; 395 resets = <&ccu RST_BUS_UART6>; 396 status = "disabled"; 397 }; 398 399 uart7: serial@1c29c00 { 400 compatible = "snps,dw-apb-uart"; 401 reg = <0x01c29c00 0x400>; 402 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 403 reg-shift = <2>; 404 reg-io-width = <4>; 405 clocks = <&ccu CLK_BUS_UART7>; 406 resets = <&ccu RST_BUS_UART7>; 407 status = "disabled"; 408 }; 409 410 i2c0: i2c@1c2ac00 { 411 compatible = "allwinner,sun6i-a31-i2c"; 412 reg = <0x01c2ac00 0x400>; 413 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&ccu CLK_BUS_I2C0>; 415 resets = <&ccu RST_BUS_I2C0>; 416 pinctrl-0 = <&i2c0_pins>; 417 pinctrl-names = "default"; 418 status = "disabled"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 }; 422 423 i2c1: i2c@1c2b000 { 424 compatible = "allwinner,sun6i-a31-i2c"; 425 reg = <0x01c2b000 0x400>; 426 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&ccu CLK_BUS_I2C1>; 428 resets = <&ccu RST_BUS_I2C1>; 429 status = "disabled"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 }; 433 434 i2c2: i2c@1c2b400 { 435 compatible = "allwinner,sun6i-a31-i2c"; 436 reg = <0x01c2b400 0x400>; 437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&ccu CLK_BUS_I2C2>; 439 resets = <&ccu RST_BUS_I2C2>; 440 status = "disabled"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 }; 444 445 i2c3: i2c@1c2b800 { 446 compatible = "allwinner,sun6i-a31-i2c"; 447 reg = <0x01c2b800 0x400>; 448 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_BUS_I2C3>; 450 resets = <&ccu RST_BUS_I2C3>; 451 status = "disabled"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 }; 455 456 i2c4: i2c@1c2c000 { 457 compatible = "allwinner,sun6i-a31-i2c"; 458 reg = <0x01c2c000 0x400>; 459 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&ccu CLK_BUS_I2C4>; 461 resets = <&ccu RST_BUS_I2C4>; 462 status = "disabled"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 467 gmac: ethernet@1c50000 { 468 compatible = "allwinner,sun8i-r40-gmac"; 469 syscon = <&ccu>; 470 reg = <0x01c50000 0x10000>; 471 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "macirq"; 473 resets = <&ccu RST_BUS_GMAC>; 474 reset-names = "stmmaceth"; 475 clocks = <&ccu CLK_BUS_GMAC>; 476 clock-names = "stmmaceth"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 481 gmac_mdio: mdio { 482 compatible = "snps,dwmac-mdio"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 }; 486 }; 487 488 gic: interrupt-controller@1c81000 { 489 compatible = "arm,gic-400"; 490 reg = <0x01c81000 0x1000>, 491 <0x01c82000 0x1000>, 492 <0x01c84000 0x2000>, 493 <0x01c86000 0x2000>; 494 interrupt-controller; 495 #interrupt-cells = <3>; 496 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 497 }; 498 }; 499 500 timer { 501 compatible = "arm,armv7-timer"; 502 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 503 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 504 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 505 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 506 }; 507}; 508