1/* 2 * Copyright 2015 Vishnu Patekar 3 * 4 * Vishnu Patekar <vishnupatekar0510@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47#include <dt-bindings/clock/sun8i-a83t-ccu.h> 48#include <dt-bindings/clock/sun8i-de2.h> 49#include <dt-bindings/clock/sun8i-r-ccu.h> 50#include <dt-bindings/reset/sun8i-a83t-ccu.h> 51#include <dt-bindings/reset/sun8i-de2.h> 52#include <dt-bindings/reset/sun8i-r-ccu.h> 53 54/ { 55 interrupt-parent = <&gic>; 56 #address-cells = <1>; 57 #size-cells = <1>; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 clocks = <&ccu CLK_C0CPUX>; 65 clock-names = "cpu"; 66 compatible = "arm,cortex-a7"; 67 device_type = "cpu"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 cci-control-port = <&cci_control0>; 70 enable-method = "allwinner,sun8i-a83t-smp"; 71 reg = <0>; 72 }; 73 74 cpu@1 { 75 compatible = "arm,cortex-a7"; 76 device_type = "cpu"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 cci-control-port = <&cci_control0>; 79 enable-method = "allwinner,sun8i-a83t-smp"; 80 reg = <1>; 81 }; 82 83 cpu@2 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 cci-control-port = <&cci_control0>; 88 enable-method = "allwinner,sun8i-a83t-smp"; 89 reg = <2>; 90 }; 91 92 cpu@3 { 93 compatible = "arm,cortex-a7"; 94 device_type = "cpu"; 95 operating-points-v2 = <&cpu0_opp_table>; 96 cci-control-port = <&cci_control0>; 97 enable-method = "allwinner,sun8i-a83t-smp"; 98 reg = <3>; 99 }; 100 101 cpu100: cpu@100 { 102 clocks = <&ccu CLK_C1CPUX>; 103 clock-names = "cpu"; 104 compatible = "arm,cortex-a7"; 105 device_type = "cpu"; 106 operating-points-v2 = <&cpu1_opp_table>; 107 cci-control-port = <&cci_control1>; 108 enable-method = "allwinner,sun8i-a83t-smp"; 109 reg = <0x100>; 110 }; 111 112 cpu@101 { 113 compatible = "arm,cortex-a7"; 114 device_type = "cpu"; 115 operating-points-v2 = <&cpu1_opp_table>; 116 cci-control-port = <&cci_control1>; 117 enable-method = "allwinner,sun8i-a83t-smp"; 118 reg = <0x101>; 119 }; 120 121 cpu@102 { 122 compatible = "arm,cortex-a7"; 123 device_type = "cpu"; 124 operating-points-v2 = <&cpu1_opp_table>; 125 cci-control-port = <&cci_control1>; 126 enable-method = "allwinner,sun8i-a83t-smp"; 127 reg = <0x102>; 128 }; 129 130 cpu@103 { 131 compatible = "arm,cortex-a7"; 132 device_type = "cpu"; 133 operating-points-v2 = <&cpu1_opp_table>; 134 cci-control-port = <&cci_control1>; 135 enable-method = "allwinner,sun8i-a83t-smp"; 136 reg = <0x103>; 137 }; 138 }; 139 140 timer { 141 compatible = "arm,armv7-timer"; 142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 146 }; 147 148 clocks { 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges; 152 153 /* TODO: PRCM block has a mux for this. */ 154 osc24M: osc24M_clk { 155 #clock-cells = <0>; 156 compatible = "fixed-clock"; 157 clock-frequency = <24000000>; 158 clock-accuracy = <50000>; 159 clock-output-names = "osc24M"; 160 }; 161 162 /* 163 * This is called "internal OSC" in some places. 164 * It is an internal RC-based oscillator. 165 * TODO: Its controls are in the PRCM block. 166 */ 167 osc16M: osc16M_clk { 168 #clock-cells = <0>; 169 compatible = "fixed-clock"; 170 clock-frequency = <16000000>; 171 clock-output-names = "osc16M"; 172 }; 173 174 osc16Md512: osc16Md512_clk { 175 #clock-cells = <0>; 176 compatible = "fixed-factor-clock"; 177 clock-div = <512>; 178 clock-mult = <1>; 179 clocks = <&osc16M>; 180 clock-output-names = "osc16M-d512"; 181 }; 182 }; 183 184 de: display-engine { 185 compatible = "allwinner,sun8i-a83t-display-engine"; 186 allwinner,pipelines = <&mixer0>, <&mixer1>; 187 status = "disabled"; 188 }; 189 190 memory { 191 reg = <0x40000000 0x80000000>; 192 device_type = "memory"; 193 }; 194 195 cpu0_opp_table: opp_table0 { 196 compatible = "operating-points-v2"; 197 opp-shared; 198 199 opp-480000000 { 200 opp-hz = /bits/ 64 <480000000>; 201 opp-microvolt = <840000>; 202 clock-latency-ns = <244144>; /* 8 32k periods */ 203 }; 204 205 opp-600000000 { 206 opp-hz = /bits/ 64 <600000000>; 207 opp-microvolt = <840000>; 208 clock-latency-ns = <244144>; /* 8 32k periods */ 209 }; 210 211 opp-720000000 { 212 opp-hz = /bits/ 64 <720000000>; 213 opp-microvolt = <840000>; 214 clock-latency-ns = <244144>; /* 8 32k periods */ 215 }; 216 217 opp-864000000 { 218 opp-hz = /bits/ 64 <864000000>; 219 opp-microvolt = <840000>; 220 clock-latency-ns = <244144>; /* 8 32k periods */ 221 }; 222 223 opp-912000000 { 224 opp-hz = /bits/ 64 <912000000>; 225 opp-microvolt = <840000>; 226 clock-latency-ns = <244144>; /* 8 32k periods */ 227 }; 228 229 opp-1008000000 { 230 opp-hz = /bits/ 64 <1008000000>; 231 opp-microvolt = <840000>; 232 clock-latency-ns = <244144>; /* 8 32k periods */ 233 }; 234 235 opp-1128000000 { 236 opp-hz = /bits/ 64 <1128000000>; 237 opp-microvolt = <840000>; 238 clock-latency-ns = <244144>; /* 8 32k periods */ 239 }; 240 241 opp-1200000000 { 242 opp-hz = /bits/ 64 <1200000000>; 243 opp-microvolt = <840000>; 244 clock-latency-ns = <244144>; /* 8 32k periods */ 245 }; 246 }; 247 248 cpu1_opp_table: opp_table1 { 249 compatible = "operating-points-v2"; 250 opp-shared; 251 252 opp-480000000 { 253 opp-hz = /bits/ 64 <480000000>; 254 opp-microvolt = <840000>; 255 clock-latency-ns = <244144>; /* 8 32k periods */ 256 }; 257 258 opp-600000000 { 259 opp-hz = /bits/ 64 <600000000>; 260 opp-microvolt = <840000>; 261 clock-latency-ns = <244144>; /* 8 32k periods */ 262 }; 263 264 opp-720000000 { 265 opp-hz = /bits/ 64 <720000000>; 266 opp-microvolt = <840000>; 267 clock-latency-ns = <244144>; /* 8 32k periods */ 268 }; 269 270 opp-864000000 { 271 opp-hz = /bits/ 64 <864000000>; 272 opp-microvolt = <840000>; 273 clock-latency-ns = <244144>; /* 8 32k periods */ 274 }; 275 276 opp-912000000 { 277 opp-hz = /bits/ 64 <912000000>; 278 opp-microvolt = <840000>; 279 clock-latency-ns = <244144>; /* 8 32k periods */ 280 }; 281 282 opp-1008000000 { 283 opp-hz = /bits/ 64 <1008000000>; 284 opp-microvolt = <840000>; 285 clock-latency-ns = <244144>; /* 8 32k periods */ 286 }; 287 288 opp-1128000000 { 289 opp-hz = /bits/ 64 <1128000000>; 290 opp-microvolt = <840000>; 291 clock-latency-ns = <244144>; /* 8 32k periods */ 292 }; 293 294 opp-1200000000 { 295 opp-hz = /bits/ 64 <1200000000>; 296 opp-microvolt = <840000>; 297 clock-latency-ns = <244144>; /* 8 32k periods */ 298 }; 299 }; 300 301 soc { 302 compatible = "simple-bus"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges; 306 307 display_clocks: clock@1000000 { 308 compatible = "allwinner,sun8i-a83t-de2-clk"; 309 reg = <0x01000000 0x100000>; 310 clocks = <&ccu CLK_PLL_DE>, 311 <&ccu CLK_BUS_DE>; 312 clock-names = "mod", 313 "bus"; 314 resets = <&ccu RST_BUS_DE>; 315 #clock-cells = <1>; 316 #reset-cells = <1>; 317 }; 318 319 mixer0: mixer@1100000 { 320 compatible = "allwinner,sun8i-a83t-de2-mixer-0"; 321 reg = <0x01100000 0x100000>; 322 clocks = <&display_clocks CLK_BUS_MIXER0>, 323 <&display_clocks CLK_MIXER0>; 324 clock-names = "bus", 325 "mod"; 326 resets = <&display_clocks RST_MIXER0>; 327 328 ports { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 332 mixer0_out: port@1 { 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <1>; 336 337 mixer0_out_tcon0: endpoint@0 { 338 reg = <0>; 339 remote-endpoint = <&tcon0_in_mixer0>; 340 }; 341 }; 342 }; 343 }; 344 345 mixer1: mixer@1200000 { 346 compatible = "allwinner,sun8i-a83t-de2-mixer-1"; 347 reg = <0x01200000 0x100000>; 348 clocks = <&display_clocks CLK_BUS_MIXER1>, 349 <&display_clocks CLK_MIXER1>; 350 clock-names = "bus", 351 "mod"; 352 resets = <&display_clocks RST_WB>; 353 354 ports { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 mixer1_out: port@1 { 359 reg = <1>; 360 361 mixer1_out_tcon1: endpoint { 362 remote-endpoint = <&tcon1_in_mixer1>; 363 }; 364 }; 365 }; 366 }; 367 368 cpucfg@1700000 { 369 compatible = "allwinner,sun8i-a83t-cpucfg"; 370 reg = <0x01700000 0x400>; 371 }; 372 373 cci@1790000 { 374 compatible = "arm,cci-400"; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 reg = <0x01790000 0x10000>; 378 ranges = <0x0 0x01790000 0x10000>; 379 380 cci_control0: slave-if@4000 { 381 compatible = "arm,cci-400-ctrl-if"; 382 interface-type = "ace"; 383 reg = <0x4000 0x1000>; 384 }; 385 386 cci_control1: slave-if@5000 { 387 compatible = "arm,cci-400-ctrl-if"; 388 interface-type = "ace"; 389 reg = <0x5000 0x1000>; 390 }; 391 392 pmu@9000 { 393 compatible = "arm,cci-400-pmu,r1"; 394 reg = <0x9000 0x5000>; 395 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 403 }; 404 }; 405 406 syscon: syscon@1c00000 { 407 compatible = "allwinner,sun8i-a83t-system-controller", 408 "syscon"; 409 reg = <0x01c00000 0x1000>; 410 }; 411 412 dma: dma-controller@1c02000 { 413 compatible = "allwinner,sun8i-a83t-dma"; 414 reg = <0x01c02000 0x1000>; 415 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&ccu CLK_BUS_DMA>; 417 resets = <&ccu RST_BUS_DMA>; 418 #dma-cells = <1>; 419 }; 420 421 tcon0: lcd-controller@1c0c000 { 422 compatible = "allwinner,sun8i-a83t-tcon-lcd"; 423 reg = <0x01c0c000 0x1000>; 424 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 426 clock-names = "ahb", "tcon-ch0"; 427 clock-output-names = "tcon-pixel-clock"; 428 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 429 reset-names = "lcd", "lvds"; 430 431 ports { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 435 tcon0_in: port@0 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 reg = <0>; 439 440 tcon0_in_mixer0: endpoint@0 { 441 reg = <0>; 442 remote-endpoint = <&mixer0_out_tcon0>; 443 }; 444 }; 445 446 tcon0_out: port@1 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 reg = <1>; 450 }; 451 }; 452 }; 453 454 tcon1: lcd-controller@1c0d000 { 455 compatible = "allwinner,sun8i-a83t-tcon-tv"; 456 reg = <0x01c0d000 0x1000>; 457 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 459 clock-names = "ahb", "tcon-ch1"; 460 resets = <&ccu RST_BUS_TCON1>; 461 reset-names = "lcd"; 462 463 ports { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 467 tcon1_in: port@0 { 468 reg = <0>; 469 470 tcon1_in_mixer1: endpoint { 471 remote-endpoint = <&mixer1_out_tcon1>; 472 }; 473 }; 474 475 tcon1_out: port@1 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 reg = <1>; 479 480 tcon1_out_hdmi: endpoint@1 { 481 reg = <1>; 482 remote-endpoint = <&hdmi_in_tcon1>; 483 }; 484 }; 485 }; 486 }; 487 488 mmc0: mmc@1c0f000 { 489 compatible = "allwinner,sun8i-a83t-mmc", 490 "allwinner,sun7i-a20-mmc"; 491 reg = <0x01c0f000 0x1000>; 492 clocks = <&ccu CLK_BUS_MMC0>, 493 <&ccu CLK_MMC0>, 494 <&ccu CLK_MMC0_OUTPUT>, 495 <&ccu CLK_MMC0_SAMPLE>; 496 clock-names = "ahb", 497 "mmc", 498 "output", 499 "sample"; 500 resets = <&ccu RST_BUS_MMC0>; 501 reset-names = "ahb"; 502 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 }; 507 508 mmc1: mmc@1c10000 { 509 compatible = "allwinner,sun8i-a83t-mmc", 510 "allwinner,sun7i-a20-mmc"; 511 reg = <0x01c10000 0x1000>; 512 clocks = <&ccu CLK_BUS_MMC1>, 513 <&ccu CLK_MMC1>, 514 <&ccu CLK_MMC1_OUTPUT>, 515 <&ccu CLK_MMC1_SAMPLE>; 516 clock-names = "ahb", 517 "mmc", 518 "output", 519 "sample"; 520 resets = <&ccu RST_BUS_MMC1>; 521 reset-names = "ahb"; 522 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&mmc1_pins>; 525 status = "disabled"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 }; 529 530 mmc2: mmc@1c11000 { 531 compatible = "allwinner,sun8i-a83t-emmc"; 532 reg = <0x01c11000 0x1000>; 533 clocks = <&ccu CLK_BUS_MMC2>, 534 <&ccu CLK_MMC2>, 535 <&ccu CLK_MMC2_OUTPUT>, 536 <&ccu CLK_MMC2_SAMPLE>; 537 clock-names = "ahb", 538 "mmc", 539 "output", 540 "sample"; 541 resets = <&ccu RST_BUS_MMC2>; 542 reset-names = "ahb"; 543 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 544 status = "disabled"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 }; 548 549 sid: eeprom@1c14000 { 550 compatible = "allwinner,sun8i-a83t-sid"; 551 reg = <0x1c14000 0x400>; 552 }; 553 554 usb_otg: usb@1c19000 { 555 compatible = "allwinner,sun8i-a83t-musb", 556 "allwinner,sun8i-a33-musb"; 557 reg = <0x01c19000 0x0400>; 558 clocks = <&ccu CLK_BUS_OTG>; 559 resets = <&ccu RST_BUS_OTG>; 560 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-names = "mc"; 562 phys = <&usbphy 0>; 563 phy-names = "usb"; 564 extcon = <&usbphy 0>; 565 status = "disabled"; 566 }; 567 568 usbphy: phy@1c19400 { 569 compatible = "allwinner,sun8i-a83t-usb-phy"; 570 reg = <0x01c19400 0x10>, 571 <0x01c1a800 0x14>, 572 <0x01c1b800 0x14>; 573 reg-names = "phy_ctrl", 574 "pmu1", 575 "pmu2"; 576 clocks = <&ccu CLK_USB_PHY0>, 577 <&ccu CLK_USB_PHY1>, 578 <&ccu CLK_USB_HSIC>, 579 <&ccu CLK_USB_HSIC_12M>; 580 clock-names = "usb0_phy", 581 "usb1_phy", 582 "usb2_phy", 583 "usb2_hsic_12M"; 584 resets = <&ccu RST_USB_PHY0>, 585 <&ccu RST_USB_PHY1>, 586 <&ccu RST_USB_HSIC>; 587 reset-names = "usb0_reset", 588 "usb1_reset", 589 "usb2_reset"; 590 status = "disabled"; 591 #phy-cells = <1>; 592 }; 593 594 ehci0: usb@1c1a000 { 595 compatible = "allwinner,sun8i-a83t-ehci", 596 "generic-ehci"; 597 reg = <0x01c1a000 0x100>; 598 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&ccu CLK_BUS_EHCI0>; 600 resets = <&ccu RST_BUS_EHCI0>; 601 phys = <&usbphy 1>; 602 phy-names = "usb"; 603 status = "disabled"; 604 }; 605 606 ohci0: usb@1c1a400 { 607 compatible = "allwinner,sun8i-a83t-ohci", 608 "generic-ohci"; 609 reg = <0x01c1a400 0x100>; 610 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; 612 resets = <&ccu RST_BUS_OHCI0>; 613 phys = <&usbphy 1>; 614 phy-names = "usb"; 615 status = "disabled"; 616 }; 617 618 ehci1: usb@1c1b000 { 619 compatible = "allwinner,sun8i-a83t-ehci", 620 "generic-ehci"; 621 reg = <0x01c1b000 0x100>; 622 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&ccu CLK_BUS_EHCI1>; 624 resets = <&ccu RST_BUS_EHCI1>; 625 phys = <&usbphy 2>; 626 phy-names = "usb"; 627 status = "disabled"; 628 }; 629 630 ccu: clock@1c20000 { 631 compatible = "allwinner,sun8i-a83t-ccu"; 632 reg = <0x01c20000 0x400>; 633 clocks = <&osc24M>, <&osc16Md512>; 634 clock-names = "hosc", "losc"; 635 #clock-cells = <1>; 636 #reset-cells = <1>; 637 }; 638 639 pio: pinctrl@1c20800 { 640 compatible = "allwinner,sun8i-a83t-pinctrl"; 641 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 644 reg = <0x01c20800 0x400>; 645 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; 646 clock-names = "apb", "hosc", "losc"; 647 gpio-controller; 648 interrupt-controller; 649 #interrupt-cells = <3>; 650 #gpio-cells = <3>; 651 652 emac_rgmii_pins: emac-rgmii-pins { 653 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 654 "PD11", "PD12", "PD13", "PD14", "PD18", 655 "PD19", "PD21", "PD22", "PD23"; 656 function = "gmac"; 657 /* 658 * data lines in RGMII mode use DDR mode 659 * and need a higher signal drive strength 660 */ 661 drive-strength = <40>; 662 }; 663 664 hdmi_pins: hdmi-pins { 665 pins = "PH6", "PH7", "PH8"; 666 function = "hdmi"; 667 }; 668 669 i2c0_pins: i2c0-pins { 670 pins = "PH0", "PH1"; 671 function = "i2c0"; 672 }; 673 674 i2c1_pins: i2c1-pins { 675 pins = "PH2", "PH3"; 676 function = "i2c1"; 677 }; 678 679 i2c2_ph_pins: i2c2-ph-pins { 680 pins = "PH4", "PH5"; 681 function = "i2c2"; 682 }; 683 684 i2s1_pins: i2s1-pins { 685 /* I2S1 does not have external MCLK pin */ 686 pins = "PG10", "PG11", "PG12", "PG13"; 687 function = "i2s1"; 688 }; 689 690 lcd_lvds_pins: lcd-lvds-pins { 691 pins = "PD18", "PD19", "PD20", "PD21", "PD22", 692 "PD23", "PD24", "PD25", "PD26", "PD27"; 693 function = "lvds0"; 694 }; 695 696 mmc0_pins: mmc0-pins { 697 pins = "PF0", "PF1", "PF2", 698 "PF3", "PF4", "PF5"; 699 function = "mmc0"; 700 drive-strength = <30>; 701 bias-pull-up; 702 }; 703 704 mmc1_pins: mmc1-pins { 705 pins = "PG0", "PG1", "PG2", 706 "PG3", "PG4", "PG5"; 707 function = "mmc1"; 708 drive-strength = <30>; 709 bias-pull-up; 710 }; 711 712 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 713 pins = "PC5", "PC6", "PC8", "PC9", 714 "PC10", "PC11", "PC12", "PC13", 715 "PC14", "PC15", "PC16"; 716 function = "mmc2"; 717 drive-strength = <30>; 718 bias-pull-up; 719 }; 720 721 pwm_pin: pwm-pin { 722 pins = "PD28"; 723 function = "pwm"; 724 }; 725 726 spdif_tx_pin: spdif-tx-pin { 727 pins = "PE18"; 728 function = "spdif"; 729 }; 730 731 uart0_pb_pins: uart0-pb-pins { 732 pins = "PB9", "PB10"; 733 function = "uart0"; 734 }; 735 736 uart0_pf_pins: uart0-pf-pins { 737 pins = "PF2", "PF4"; 738 function = "uart0"; 739 }; 740 741 uart1_pins: uart1-pins { 742 pins = "PG6", "PG7"; 743 function = "uart1"; 744 }; 745 746 uart1_rts_cts_pins: uart1-rts-cts-pins { 747 pins = "PG8", "PG9"; 748 function = "uart1"; 749 }; 750 }; 751 752 timer@1c20c00 { 753 compatible = "allwinner,sun4i-a10-timer"; 754 reg = <0x01c20c00 0xa0>; 755 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&osc24M>; 758 }; 759 760 watchdog@1c20ca0 { 761 compatible = "allwinner,sun6i-a31-wdt"; 762 reg = <0x01c20ca0 0x20>; 763 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&osc24M>; 765 }; 766 767 spdif: spdif@1c21000 { 768 #sound-dai-cells = <0>; 769 compatible = "allwinner,sun8i-a83t-spdif", 770 "allwinner,sun8i-h3-spdif"; 771 reg = <0x01c21000 0x400>; 772 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 774 resets = <&ccu RST_BUS_SPDIF>; 775 clock-names = "apb", "spdif"; 776 dmas = <&dma 2>; 777 dma-names = "tx"; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&spdif_tx_pin>; 780 status = "disabled"; 781 }; 782 783 i2s0: i2s@1c22000 { 784 #sound-dai-cells = <0>; 785 compatible = "allwinner,sun8i-a83t-i2s"; 786 reg = <0x01c22000 0x400>; 787 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 789 clock-names = "apb", "mod"; 790 dmas = <&dma 3>, <&dma 3>; 791 resets = <&ccu RST_BUS_I2S0>; 792 dma-names = "rx", "tx"; 793 status = "disabled"; 794 }; 795 796 i2s1: i2s@1c22400 { 797 #sound-dai-cells = <0>; 798 compatible = "allwinner,sun8i-a83t-i2s"; 799 reg = <0x01c22400 0x400>; 800 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 802 clock-names = "apb", "mod"; 803 dmas = <&dma 4>, <&dma 4>; 804 resets = <&ccu RST_BUS_I2S1>; 805 dma-names = "rx", "tx"; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&i2s1_pins>; 808 status = "disabled"; 809 }; 810 811 i2s2: i2s@1c22800 { 812 #sound-dai-cells = <0>; 813 compatible = "allwinner,sun8i-a83t-i2s"; 814 reg = <0x01c22800 0x400>; 815 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 817 clock-names = "apb", "mod"; 818 dmas = <&dma 27>; 819 resets = <&ccu RST_BUS_I2S2>; 820 dma-names = "tx"; 821 status = "disabled"; 822 }; 823 824 pwm: pwm@1c21400 { 825 compatible = "allwinner,sun8i-a83t-pwm", 826 "allwinner,sun8i-h3-pwm"; 827 reg = <0x01c21400 0x400>; 828 clocks = <&osc24M>; 829 #pwm-cells = <3>; 830 status = "disabled"; 831 }; 832 833 uart0: serial@1c28000 { 834 compatible = "snps,dw-apb-uart"; 835 reg = <0x01c28000 0x400>; 836 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 837 reg-shift = <2>; 838 reg-io-width = <4>; 839 clocks = <&ccu CLK_BUS_UART0>; 840 resets = <&ccu RST_BUS_UART0>; 841 status = "disabled"; 842 }; 843 844 uart1: serial@1c28400 { 845 compatible = "snps,dw-apb-uart"; 846 reg = <0x01c28400 0x400>; 847 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 848 reg-shift = <2>; 849 reg-io-width = <4>; 850 clocks = <&ccu CLK_BUS_UART1>; 851 resets = <&ccu RST_BUS_UART1>; 852 status = "disabled"; 853 }; 854 855 i2c0: i2c@1c2ac00 { 856 compatible = "allwinner,sun8i-a83t-i2c", 857 "allwinner,sun6i-a31-i2c"; 858 reg = <0x01c2ac00 0x400>; 859 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&ccu CLK_BUS_I2C0>; 861 resets = <&ccu RST_BUS_I2C0>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&i2c0_pins>; 864 status = "disabled"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 }; 868 869 i2c1: i2c@1c2b000 { 870 compatible = "allwinner,sun8i-a83t-i2c", 871 "allwinner,sun6i-a31-i2c"; 872 reg = <0x01c2b000 0x400>; 873 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&ccu CLK_BUS_I2C1>; 875 resets = <&ccu RST_BUS_I2C1>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&i2c1_pins>; 878 status = "disabled"; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 }; 882 883 i2c2: i2c@1c2b400 { 884 compatible = "allwinner,sun8i-a83t-i2c", 885 "allwinner,sun6i-a31-i2c"; 886 reg = <0x01c2b400 0x400>; 887 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&ccu CLK_BUS_I2C2>; 889 resets = <&ccu RST_BUS_I2C2>; 890 status = "disabled"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 }; 894 895 emac: ethernet@1c30000 { 896 compatible = "allwinner,sun8i-a83t-emac"; 897 syscon = <&syscon>; 898 reg = <0x01c30000 0x104>; 899 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "macirq"; 901 resets = <&ccu 13>; 902 reset-names = "stmmaceth"; 903 clocks = <&ccu 27>; 904 clock-names = "stmmaceth"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 909 mdio: mdio { 910 compatible = "snps,dwmac-mdio"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 }; 914 }; 915 916 gic: interrupt-controller@1c81000 { 917 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 918 reg = <0x01c81000 0x1000>, 919 <0x01c82000 0x2000>, 920 <0x01c84000 0x2000>, 921 <0x01c86000 0x2000>; 922 interrupt-controller; 923 #interrupt-cells = <3>; 924 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 925 }; 926 927 hdmi: hdmi@1ee0000 { 928 compatible = "allwinner,sun8i-a83t-dw-hdmi"; 929 reg = <0x01ee0000 0x10000>; 930 reg-io-width = <1>; 931 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 933 <&ccu CLK_HDMI>; 934 clock-names = "iahb", "isfr", "tmds"; 935 resets = <&ccu RST_BUS_HDMI1>; 936 reset-names = "ctrl"; 937 phys = <&hdmi_phy>; 938 phy-names = "hdmi-phy"; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&hdmi_pins>; 941 status = "disabled"; 942 943 ports { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 hdmi_in: port@0 { 948 reg = <0>; 949 950 hdmi_in_tcon1: endpoint { 951 remote-endpoint = <&tcon1_out_hdmi>; 952 }; 953 }; 954 955 hdmi_out: port@1 { 956 reg = <1>; 957 }; 958 }; 959 }; 960 961 hdmi_phy: hdmi-phy@1ef0000 { 962 compatible = "allwinner,sun8i-a83t-hdmi-phy"; 963 reg = <0x01ef0000 0x10000>; 964 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 965 clock-names = "bus", "mod"; 966 resets = <&ccu RST_BUS_HDMI0>; 967 reset-names = "phy"; 968 #phy-cells = <0>; 969 }; 970 971 r_intc: interrupt-controller@1f00c00 { 972 compatible = "allwinner,sun8i-a83t-r-intc", 973 "allwinner,sun6i-a31-r-intc"; 974 interrupt-controller; 975 #interrupt-cells = <2>; 976 reg = <0x01f00c00 0x400>; 977 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 978 }; 979 980 r_ccu: clock@1f01400 { 981 compatible = "allwinner,sun8i-a83t-r-ccu"; 982 reg = <0x01f01400 0x400>; 983 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, 984 <&ccu 6>; 985 clock-names = "hosc", "losc", "iosc", "pll-periph"; 986 #clock-cells = <1>; 987 #reset-cells = <1>; 988 }; 989 990 r_cpucfg@1f01c00 { 991 compatible = "allwinner,sun8i-a83t-r-cpucfg"; 992 reg = <0x1f01c00 0x400>; 993 }; 994 995 r_pio: pinctrl@1f02c00 { 996 compatible = "allwinner,sun8i-a83t-r-pinctrl"; 997 reg = <0x01f02c00 0x400>; 998 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 1000 <&osc16Md512>; 1001 clock-names = "apb", "hosc", "losc"; 1002 gpio-controller; 1003 #gpio-cells = <3>; 1004 interrupt-controller; 1005 #interrupt-cells = <3>; 1006 1007 r_rsb_pins: r-rsb-pins { 1008 pins = "PL0", "PL1"; 1009 function = "s_rsb"; 1010 drive-strength = <20>; 1011 bias-pull-up; 1012 }; 1013 }; 1014 1015 r_rsb: rsb@1f03400 { 1016 compatible = "allwinner,sun8i-a83t-rsb", 1017 "allwinner,sun8i-a23-rsb"; 1018 reg = <0x01f03400 0x400>; 1019 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&r_ccu CLK_APB0_RSB>; 1021 clock-frequency = <3000000>; 1022 resets = <&r_ccu RST_APB0_RSB>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&r_rsb_pins>; 1025 status = "disabled"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 }; 1029 }; 1030}; 1031