1/* 2 * Copyright 2015 Vishnu Patekar 3 * 4 * Vishnu Patekar <vishnupatekar0510@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 44 */ 45 46#include "skeleton.dtsi" 47 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49 50#include <dt-bindings/pinctrl/sun4i-a10.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 55 chosen { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 }; 60 61 cpus { 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 cpu@0 { 66 compatible = "arm,cortex-a7"; 67 device_type = "cpu"; 68 reg = <0>; 69 }; 70 71 cpu@1 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <1>; 75 }; 76 77 cpu@2 { 78 compatible = "arm,cortex-a7"; 79 device_type = "cpu"; 80 reg = <2>; 81 }; 82 83 cpu@3 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <3>; 87 }; 88 cpu@100 { 89 compatible = "arm,cortex-a7"; 90 device_type = "cpu"; 91 reg = <0x100>; 92 }; 93 94 cpu@101 { 95 compatible = "arm,cortex-a7"; 96 device_type = "cpu"; 97 reg = <0x101>; 98 }; 99 cpu@102 { 100 compatible = "arm,cortex-a7"; 101 device_type = "cpu"; 102 reg = <0x102>; 103 }; 104 105 cpu@103 { 106 compatible = "arm,cortex-a7"; 107 device_type = "cpu"; 108 reg = <0x103>; 109 }; 110 }; 111 112 memory { 113 reg = <0x40000000 0x80000000>; 114 }; 115 116 timer { 117 compatible = "arm,armv7-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 clock-frequency = <24000000>; 123 arm,cpu-registers-not-fw-configured; 124 }; 125 126 clocks { 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 }; 145 146 soc@01c00000 { 147 compatible = "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges; 151 152 gic: interrupt-controller@01c81000 { 153 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 154 reg = <0x01c81000 0x1000>, 155 <0x01c82000 0x1000>, 156 <0x01c84000 0x2000>, 157 <0x01c86000 0x2000>; 158 interrupt-controller; 159 #interrupt-cells = <3>; 160 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 161 }; 162 163 pio: pinctrl@01c20800 { 164 compatible = "allwinner,sun8i-a83t-pinctrl"; 165 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 168 reg = <0x01c20800 0x400>; 169 clocks = <&osc24M>; 170 gpio-controller; 171 interrupt-controller; 172 #interrupt-cells = <3>; 173 #gpio-cells = <3>; 174 175 i2c0_pins_a: i2c0@0 { 176 allwinner,pins = "PH0", "PH1"; 177 allwinner,function = "i2c0"; 178 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 179 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 180 }; 181 182 i2c1_pins_a: i2c1@0 { 183 allwinner,pins = "PH2", "PH3"; 184 allwinner,function = "i2c1"; 185 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 186 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 187 }; 188 189 i2c2_pins_a: i2c2@0 { 190 allwinner,pins = "PH4", "PH5"; 191 allwinner,function = "i2c2"; 192 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 193 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 194 }; 195 196 mmc0_pins_a: mmc0@0 { 197 allwinner,pins = "PF0", "PF1", "PF2", 198 "PF3", "PF4", "PF5"; 199 allwinner,function = "mmc0"; 200 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 201 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 202 }; 203 204 mmc1_pins_a: mmc1@0 { 205 allwinner,pins = "PG0", "PG1", "PG2", 206 "PG3", "PG4", "PG5"; 207 allwinner,function = "mmc1"; 208 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 209 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 210 }; 211 212 mmc2_8bit_pins: mmc2_8bit { 213 allwinner,pins = "PC5", "PC6", "PC8", 214 "PC9", "PC10", "PC11", 215 "PC12", "PC13", "PC14", 216 "PC15"; 217 allwinner,function = "mmc2"; 218 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 219 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 220 }; 221 222 uart0_pins_a: uart0@0 { 223 allwinner,pins = "PF2", "PF4"; 224 allwinner,function = "uart0"; 225 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 226 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 227 }; 228 229 uart0_pins_b: uart0@1 { 230 allwinner,pins = "PB9", "PB10"; 231 allwinner,function = "uart0"; 232 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 233 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 234 }; 235 }; 236 237 uart0: serial@01c28000 { 238 compatible = "snps,dw-apb-uart"; 239 reg = <0x01c28000 0x400>; 240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 241 reg-shift = <2>; 242 reg-io-width = <4>; 243 clocks = <&osc24M>; 244 status = "disabled"; 245 }; 246 }; 247}; 248