1*53ab4af3SHans de Goede/* 2*53ab4af3SHans de Goede * Copyright 2014 Chen-Yu Tsai 3*53ab4af3SHans de Goede * 4*53ab4af3SHans de Goede * Chen-Yu Tsai <wens@csie.org> 5*53ab4af3SHans de Goede * 6*53ab4af3SHans de Goede * This file is dual-licensed: you can use it either under the terms 7*53ab4af3SHans de Goede * of the GPL or the X11 license, at your option. Note that this dual 8*53ab4af3SHans de Goede * licensing only applies to this file, and not this project as a 9*53ab4af3SHans de Goede * whole. 10*53ab4af3SHans de Goede * 11*53ab4af3SHans de Goede * a) This file is free software; you can redistribute it and/or 12*53ab4af3SHans de Goede * modify it under the terms of the GNU General Public License as 13*53ab4af3SHans de Goede * published by the Free Software Foundation; either version 2 of the 14*53ab4af3SHans de Goede * License, or (at your option) any later version. 15*53ab4af3SHans de Goede * 16*53ab4af3SHans de Goede * This file is distributed in the hope that it will be useful, 17*53ab4af3SHans de Goede * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*53ab4af3SHans de Goede * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*53ab4af3SHans de Goede * GNU General Public License for more details. 20*53ab4af3SHans de Goede * 21*53ab4af3SHans de Goede * You should have received a copy of the GNU General Public 22*53ab4af3SHans de Goede * License along with this file; if not, write to the Free 23*53ab4af3SHans de Goede * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24*53ab4af3SHans de Goede * MA 02110-1301 USA 25*53ab4af3SHans de Goede * 26*53ab4af3SHans de Goede * Or, alternatively, 27*53ab4af3SHans de Goede * 28*53ab4af3SHans de Goede * b) Permission is hereby granted, free of charge, to any person 29*53ab4af3SHans de Goede * obtaining a copy of this software and associated documentation 30*53ab4af3SHans de Goede * files (the "Software"), to deal in the Software without 31*53ab4af3SHans de Goede * restriction, including without limitation the rights to use, 32*53ab4af3SHans de Goede * copy, modify, merge, publish, distribute, sublicense, and/or 33*53ab4af3SHans de Goede * sell copies of the Software, and to permit persons to whom the 34*53ab4af3SHans de Goede * Software is furnished to do so, subject to the following 35*53ab4af3SHans de Goede * conditions: 36*53ab4af3SHans de Goede * 37*53ab4af3SHans de Goede * The above copyright notice and this permission notice shall be 38*53ab4af3SHans de Goede * included in all copies or substantial portions of the Software. 39*53ab4af3SHans de Goede * 40*53ab4af3SHans de Goede * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41*53ab4af3SHans de Goede * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42*53ab4af3SHans de Goede * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43*53ab4af3SHans de Goede * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44*53ab4af3SHans de Goede * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45*53ab4af3SHans de Goede * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46*53ab4af3SHans de Goede * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47*53ab4af3SHans de Goede * OTHER DEALINGS IN THE SOFTWARE. 48*53ab4af3SHans de Goede */ 49*53ab4af3SHans de Goede 50*53ab4af3SHans de Goede#include "skeleton.dtsi" 51*53ab4af3SHans de Goede 52*53ab4af3SHans de Goede#include <dt-bindings/interrupt-controller/arm-gic.h> 53*53ab4af3SHans de Goede 54*53ab4af3SHans de Goede#include <dt-bindings/pinctrl/sun4i-a10.h> 55*53ab4af3SHans de Goede 56*53ab4af3SHans de Goede/ { 57*53ab4af3SHans de Goede interrupt-parent = <&gic>; 58*53ab4af3SHans de Goede 59*53ab4af3SHans de Goede chosen { 60*53ab4af3SHans de Goede #address-cells = <1>; 61*53ab4af3SHans de Goede #size-cells = <1>; 62*53ab4af3SHans de Goede ranges; 63*53ab4af3SHans de Goede 64*53ab4af3SHans de Goede framebuffer@0 { 65*53ab4af3SHans de Goede compatible = "allwinner,simple-framebuffer", 66*53ab4af3SHans de Goede "simple-framebuffer"; 67*53ab4af3SHans de Goede allwinner,pipeline = "de_be0-lcd0"; 68*53ab4af3SHans de Goede clocks = <&pll6 0>; 69*53ab4af3SHans de Goede status = "disabled"; 70*53ab4af3SHans de Goede }; 71*53ab4af3SHans de Goede }; 72*53ab4af3SHans de Goede 73*53ab4af3SHans de Goede timer { 74*53ab4af3SHans de Goede compatible = "arm,armv7-timer"; 75*53ab4af3SHans de Goede interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76*53ab4af3SHans de Goede <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77*53ab4af3SHans de Goede <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 78*53ab4af3SHans de Goede <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 79*53ab4af3SHans de Goede clock-frequency = <24000000>; 80*53ab4af3SHans de Goede arm,cpu-registers-not-fw-configured; 81*53ab4af3SHans de Goede }; 82*53ab4af3SHans de Goede 83*53ab4af3SHans de Goede cpus { 84*53ab4af3SHans de Goede enable-method = "allwinner,sun8i-a23"; 85*53ab4af3SHans de Goede #address-cells = <1>; 86*53ab4af3SHans de Goede #size-cells = <0>; 87*53ab4af3SHans de Goede 88*53ab4af3SHans de Goede cpu@0 { 89*53ab4af3SHans de Goede compatible = "arm,cortex-a7"; 90*53ab4af3SHans de Goede device_type = "cpu"; 91*53ab4af3SHans de Goede reg = <0>; 92*53ab4af3SHans de Goede }; 93*53ab4af3SHans de Goede 94*53ab4af3SHans de Goede cpu@1 { 95*53ab4af3SHans de Goede compatible = "arm,cortex-a7"; 96*53ab4af3SHans de Goede device_type = "cpu"; 97*53ab4af3SHans de Goede reg = <1>; 98*53ab4af3SHans de Goede }; 99*53ab4af3SHans de Goede }; 100*53ab4af3SHans de Goede 101*53ab4af3SHans de Goede memory { 102*53ab4af3SHans de Goede reg = <0x40000000 0x40000000>; 103*53ab4af3SHans de Goede }; 104*53ab4af3SHans de Goede 105*53ab4af3SHans de Goede clocks { 106*53ab4af3SHans de Goede #address-cells = <1>; 107*53ab4af3SHans de Goede #size-cells = <1>; 108*53ab4af3SHans de Goede ranges; 109*53ab4af3SHans de Goede 110*53ab4af3SHans de Goede osc24M: osc24M_clk { 111*53ab4af3SHans de Goede #clock-cells = <0>; 112*53ab4af3SHans de Goede compatible = "fixed-clock"; 113*53ab4af3SHans de Goede clock-frequency = <24000000>; 114*53ab4af3SHans de Goede clock-output-names = "osc24M"; 115*53ab4af3SHans de Goede }; 116*53ab4af3SHans de Goede 117*53ab4af3SHans de Goede osc32k: osc32k_clk { 118*53ab4af3SHans de Goede #clock-cells = <0>; 119*53ab4af3SHans de Goede compatible = "fixed-clock"; 120*53ab4af3SHans de Goede clock-frequency = <32768>; 121*53ab4af3SHans de Goede clock-output-names = "osc32k"; 122*53ab4af3SHans de Goede }; 123*53ab4af3SHans de Goede 124*53ab4af3SHans de Goede pll1: clk@01c20000 { 125*53ab4af3SHans de Goede #clock-cells = <0>; 126*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-pll1-clk"; 127*53ab4af3SHans de Goede reg = <0x01c20000 0x4>; 128*53ab4af3SHans de Goede clocks = <&osc24M>; 129*53ab4af3SHans de Goede clock-output-names = "pll1"; 130*53ab4af3SHans de Goede }; 131*53ab4af3SHans de Goede 132*53ab4af3SHans de Goede /* dummy clock until actually implemented */ 133*53ab4af3SHans de Goede pll5: pll5_clk { 134*53ab4af3SHans de Goede #clock-cells = <0>; 135*53ab4af3SHans de Goede compatible = "fixed-clock"; 136*53ab4af3SHans de Goede clock-frequency = <0>; 137*53ab4af3SHans de Goede clock-output-names = "pll5"; 138*53ab4af3SHans de Goede }; 139*53ab4af3SHans de Goede 140*53ab4af3SHans de Goede pll6: clk@01c20028 { 141*53ab4af3SHans de Goede #clock-cells = <1>; 142*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-pll6-clk"; 143*53ab4af3SHans de Goede reg = <0x01c20028 0x4>; 144*53ab4af3SHans de Goede clocks = <&osc24M>; 145*53ab4af3SHans de Goede clock-output-names = "pll6", "pll6x2"; 146*53ab4af3SHans de Goede }; 147*53ab4af3SHans de Goede 148*53ab4af3SHans de Goede cpu: cpu_clk@01c20050 { 149*53ab4af3SHans de Goede #clock-cells = <0>; 150*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-cpu-clk"; 151*53ab4af3SHans de Goede reg = <0x01c20050 0x4>; 152*53ab4af3SHans de Goede 153*53ab4af3SHans de Goede /* 154*53ab4af3SHans de Goede * PLL1 is listed twice here. 155*53ab4af3SHans de Goede * While it looks suspicious, it's actually documented 156*53ab4af3SHans de Goede * that way both in the datasheet and in the code from 157*53ab4af3SHans de Goede * Allwinner. 158*53ab4af3SHans de Goede */ 159*53ab4af3SHans de Goede clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 160*53ab4af3SHans de Goede clock-output-names = "cpu"; 161*53ab4af3SHans de Goede }; 162*53ab4af3SHans de Goede 163*53ab4af3SHans de Goede axi: axi_clk@01c20050 { 164*53ab4af3SHans de Goede #clock-cells = <0>; 165*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-axi-clk"; 166*53ab4af3SHans de Goede reg = <0x01c20050 0x4>; 167*53ab4af3SHans de Goede clocks = <&cpu>; 168*53ab4af3SHans de Goede clock-output-names = "axi"; 169*53ab4af3SHans de Goede }; 170*53ab4af3SHans de Goede 171*53ab4af3SHans de Goede ahb1: ahb1_clk@01c20054 { 172*53ab4af3SHans de Goede #clock-cells = <0>; 173*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-ahb1-clk"; 174*53ab4af3SHans de Goede reg = <0x01c20054 0x4>; 175*53ab4af3SHans de Goede clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 176*53ab4af3SHans de Goede clock-output-names = "ahb1"; 177*53ab4af3SHans de Goede }; 178*53ab4af3SHans de Goede 179*53ab4af3SHans de Goede apb1: apb1_clk@01c20054 { 180*53ab4af3SHans de Goede #clock-cells = <0>; 181*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-apb0-clk"; 182*53ab4af3SHans de Goede reg = <0x01c20054 0x4>; 183*53ab4af3SHans de Goede clocks = <&ahb1>; 184*53ab4af3SHans de Goede clock-output-names = "apb1"; 185*53ab4af3SHans de Goede }; 186*53ab4af3SHans de Goede 187*53ab4af3SHans de Goede ahb1_gates: clk@01c20060 { 188*53ab4af3SHans de Goede #clock-cells = <1>; 189*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; 190*53ab4af3SHans de Goede reg = <0x01c20060 0x8>; 191*53ab4af3SHans de Goede clocks = <&ahb1>; 192*53ab4af3SHans de Goede clock-output-names = "ahb1_mipidsi", "ahb1_dma", 193*53ab4af3SHans de Goede "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", 194*53ab4af3SHans de Goede "ahb1_nand", "ahb1_sdram", 195*53ab4af3SHans de Goede "ahb1_hstimer", "ahb1_spi0", 196*53ab4af3SHans de Goede "ahb1_spi1", "ahb1_otg", "ahb1_ehci", 197*53ab4af3SHans de Goede "ahb1_ohci", "ahb1_ve", "ahb1_lcd", 198*53ab4af3SHans de Goede "ahb1_csi", "ahb1_be", "ahb1_fe", 199*53ab4af3SHans de Goede "ahb1_gpu", "ahb1_spinlock", 200*53ab4af3SHans de Goede "ahb1_drc"; 201*53ab4af3SHans de Goede }; 202*53ab4af3SHans de Goede 203*53ab4af3SHans de Goede apb1_gates: clk@01c20068 { 204*53ab4af3SHans de Goede #clock-cells = <1>; 205*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-apb1-gates-clk"; 206*53ab4af3SHans de Goede reg = <0x01c20068 0x4>; 207*53ab4af3SHans de Goede clocks = <&apb1>; 208*53ab4af3SHans de Goede clock-output-names = "apb1_codec", "apb1_pio", 209*53ab4af3SHans de Goede "apb1_daudio0", "apb1_daudio1"; 210*53ab4af3SHans de Goede }; 211*53ab4af3SHans de Goede 212*53ab4af3SHans de Goede apb2: clk@01c20058 { 213*53ab4af3SHans de Goede #clock-cells = <0>; 214*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-apb1-clk"; 215*53ab4af3SHans de Goede reg = <0x01c20058 0x4>; 216*53ab4af3SHans de Goede clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 217*53ab4af3SHans de Goede clock-output-names = "apb2"; 218*53ab4af3SHans de Goede }; 219*53ab4af3SHans de Goede 220*53ab4af3SHans de Goede apb2_gates: clk@01c2006c { 221*53ab4af3SHans de Goede #clock-cells = <1>; 222*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-apb2-gates-clk"; 223*53ab4af3SHans de Goede reg = <0x01c2006c 0x4>; 224*53ab4af3SHans de Goede clocks = <&apb2>; 225*53ab4af3SHans de Goede clock-output-names = "apb2_i2c0", "apb2_i2c1", 226*53ab4af3SHans de Goede "apb2_i2c2", "apb2_uart0", 227*53ab4af3SHans de Goede "apb2_uart1", "apb2_uart2", 228*53ab4af3SHans de Goede "apb2_uart3", "apb2_uart4"; 229*53ab4af3SHans de Goede }; 230*53ab4af3SHans de Goede 231*53ab4af3SHans de Goede mmc0_clk: clk@01c20088 { 232*53ab4af3SHans de Goede #clock-cells = <1>; 233*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-mmc-clk"; 234*53ab4af3SHans de Goede reg = <0x01c20088 0x4>; 235*53ab4af3SHans de Goede clocks = <&osc24M>, <&pll6 0>; 236*53ab4af3SHans de Goede clock-output-names = "mmc0", 237*53ab4af3SHans de Goede "mmc0_output", 238*53ab4af3SHans de Goede "mmc0_sample"; 239*53ab4af3SHans de Goede }; 240*53ab4af3SHans de Goede 241*53ab4af3SHans de Goede mmc1_clk: clk@01c2008c { 242*53ab4af3SHans de Goede #clock-cells = <1>; 243*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-mmc-clk"; 244*53ab4af3SHans de Goede reg = <0x01c2008c 0x4>; 245*53ab4af3SHans de Goede clocks = <&osc24M>, <&pll6 0>; 246*53ab4af3SHans de Goede clock-output-names = "mmc1", 247*53ab4af3SHans de Goede "mmc1_output", 248*53ab4af3SHans de Goede "mmc1_sample"; 249*53ab4af3SHans de Goede }; 250*53ab4af3SHans de Goede 251*53ab4af3SHans de Goede mmc2_clk: clk@01c20090 { 252*53ab4af3SHans de Goede #clock-cells = <1>; 253*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-mmc-clk"; 254*53ab4af3SHans de Goede reg = <0x01c20090 0x4>; 255*53ab4af3SHans de Goede clocks = <&osc24M>, <&pll6 0>; 256*53ab4af3SHans de Goede clock-output-names = "mmc2", 257*53ab4af3SHans de Goede "mmc2_output", 258*53ab4af3SHans de Goede "mmc2_sample"; 259*53ab4af3SHans de Goede }; 260*53ab4af3SHans de Goede 261*53ab4af3SHans de Goede mbus_clk: clk@01c2015c { 262*53ab4af3SHans de Goede #clock-cells = <0>; 263*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-mbus-clk"; 264*53ab4af3SHans de Goede reg = <0x01c2015c 0x4>; 265*53ab4af3SHans de Goede clocks = <&osc24M>, <&pll6 1>, <&pll5>; 266*53ab4af3SHans de Goede clock-output-names = "mbus"; 267*53ab4af3SHans de Goede }; 268*53ab4af3SHans de Goede }; 269*53ab4af3SHans de Goede 270*53ab4af3SHans de Goede soc@01c00000 { 271*53ab4af3SHans de Goede compatible = "simple-bus"; 272*53ab4af3SHans de Goede #address-cells = <1>; 273*53ab4af3SHans de Goede #size-cells = <1>; 274*53ab4af3SHans de Goede ranges; 275*53ab4af3SHans de Goede 276*53ab4af3SHans de Goede dma: dma-controller@01c02000 { 277*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-dma"; 278*53ab4af3SHans de Goede reg = <0x01c02000 0x1000>; 279*53ab4af3SHans de Goede interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 280*53ab4af3SHans de Goede clocks = <&ahb1_gates 6>; 281*53ab4af3SHans de Goede resets = <&ahb1_rst 6>; 282*53ab4af3SHans de Goede #dma-cells = <1>; 283*53ab4af3SHans de Goede }; 284*53ab4af3SHans de Goede 285*53ab4af3SHans de Goede mmc0: mmc@01c0f000 { 286*53ab4af3SHans de Goede compatible = "allwinner,sun5i-a13-mmc"; 287*53ab4af3SHans de Goede reg = <0x01c0f000 0x1000>; 288*53ab4af3SHans de Goede clocks = <&ahb1_gates 8>, 289*53ab4af3SHans de Goede <&mmc0_clk 0>, 290*53ab4af3SHans de Goede <&mmc0_clk 1>, 291*53ab4af3SHans de Goede <&mmc0_clk 2>; 292*53ab4af3SHans de Goede clock-names = "ahb", 293*53ab4af3SHans de Goede "mmc", 294*53ab4af3SHans de Goede "output", 295*53ab4af3SHans de Goede "sample"; 296*53ab4af3SHans de Goede resets = <&ahb1_rst 8>; 297*53ab4af3SHans de Goede reset-names = "ahb"; 298*53ab4af3SHans de Goede interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 299*53ab4af3SHans de Goede status = "disabled"; 300*53ab4af3SHans de Goede #address-cells = <1>; 301*53ab4af3SHans de Goede #size-cells = <0>; 302*53ab4af3SHans de Goede }; 303*53ab4af3SHans de Goede 304*53ab4af3SHans de Goede mmc1: mmc@01c10000 { 305*53ab4af3SHans de Goede compatible = "allwinner,sun5i-a13-mmc"; 306*53ab4af3SHans de Goede reg = <0x01c10000 0x1000>; 307*53ab4af3SHans de Goede clocks = <&ahb1_gates 9>, 308*53ab4af3SHans de Goede <&mmc1_clk 0>, 309*53ab4af3SHans de Goede <&mmc1_clk 1>, 310*53ab4af3SHans de Goede <&mmc1_clk 2>; 311*53ab4af3SHans de Goede clock-names = "ahb", 312*53ab4af3SHans de Goede "mmc", 313*53ab4af3SHans de Goede "output", 314*53ab4af3SHans de Goede "sample"; 315*53ab4af3SHans de Goede resets = <&ahb1_rst 9>; 316*53ab4af3SHans de Goede reset-names = "ahb"; 317*53ab4af3SHans de Goede interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 318*53ab4af3SHans de Goede status = "disabled"; 319*53ab4af3SHans de Goede #address-cells = <1>; 320*53ab4af3SHans de Goede #size-cells = <0>; 321*53ab4af3SHans de Goede }; 322*53ab4af3SHans de Goede 323*53ab4af3SHans de Goede mmc2: mmc@01c11000 { 324*53ab4af3SHans de Goede compatible = "allwinner,sun5i-a13-mmc"; 325*53ab4af3SHans de Goede reg = <0x01c11000 0x1000>; 326*53ab4af3SHans de Goede clocks = <&ahb1_gates 10>, 327*53ab4af3SHans de Goede <&mmc2_clk 0>, 328*53ab4af3SHans de Goede <&mmc2_clk 1>, 329*53ab4af3SHans de Goede <&mmc2_clk 2>; 330*53ab4af3SHans de Goede clock-names = "ahb", 331*53ab4af3SHans de Goede "mmc", 332*53ab4af3SHans de Goede "output", 333*53ab4af3SHans de Goede "sample"; 334*53ab4af3SHans de Goede resets = <&ahb1_rst 10>; 335*53ab4af3SHans de Goede reset-names = "ahb"; 336*53ab4af3SHans de Goede interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 337*53ab4af3SHans de Goede status = "disabled"; 338*53ab4af3SHans de Goede #address-cells = <1>; 339*53ab4af3SHans de Goede #size-cells = <0>; 340*53ab4af3SHans de Goede }; 341*53ab4af3SHans de Goede 342*53ab4af3SHans de Goede pio: pinctrl@01c20800 { 343*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-pinctrl"; 344*53ab4af3SHans de Goede reg = <0x01c20800 0x400>; 345*53ab4af3SHans de Goede interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 346*53ab4af3SHans de Goede <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 347*53ab4af3SHans de Goede <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 348*53ab4af3SHans de Goede clocks = <&apb1_gates 5>; 349*53ab4af3SHans de Goede gpio-controller; 350*53ab4af3SHans de Goede interrupt-controller; 351*53ab4af3SHans de Goede #address-cells = <1>; 352*53ab4af3SHans de Goede #size-cells = <0>; 353*53ab4af3SHans de Goede #gpio-cells = <3>; 354*53ab4af3SHans de Goede 355*53ab4af3SHans de Goede uart0_pins_a: uart0@0 { 356*53ab4af3SHans de Goede allwinner,pins = "PF2", "PF4"; 357*53ab4af3SHans de Goede allwinner,function = "uart0"; 358*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_10_MA>; 359*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 360*53ab4af3SHans de Goede }; 361*53ab4af3SHans de Goede 362*53ab4af3SHans de Goede mmc0_pins_a: mmc0@0 { 363*53ab4af3SHans de Goede allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 364*53ab4af3SHans de Goede allwinner,function = "mmc0"; 365*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_30_MA>; 366*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 367*53ab4af3SHans de Goede }; 368*53ab4af3SHans de Goede 369*53ab4af3SHans de Goede mmc1_pins_a: mmc1@0 { 370*53ab4af3SHans de Goede allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; 371*53ab4af3SHans de Goede allwinner,function = "mmc1"; 372*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_30_MA>; 373*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 374*53ab4af3SHans de Goede }; 375*53ab4af3SHans de Goede 376*53ab4af3SHans de Goede i2c0_pins_a: i2c0@0 { 377*53ab4af3SHans de Goede allwinner,pins = "PH2", "PH3"; 378*53ab4af3SHans de Goede allwinner,function = "i2c0"; 379*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_10_MA>; 380*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 381*53ab4af3SHans de Goede }; 382*53ab4af3SHans de Goede 383*53ab4af3SHans de Goede i2c1_pins_a: i2c1@0 { 384*53ab4af3SHans de Goede allwinner,pins = "PH4", "PH5"; 385*53ab4af3SHans de Goede allwinner,function = "i2c1"; 386*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_10_MA>; 387*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 388*53ab4af3SHans de Goede }; 389*53ab4af3SHans de Goede 390*53ab4af3SHans de Goede i2c2_pins_a: i2c2@0 { 391*53ab4af3SHans de Goede allwinner,pins = "PE12", "PE13"; 392*53ab4af3SHans de Goede allwinner,function = "i2c2"; 393*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_10_MA>; 394*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 395*53ab4af3SHans de Goede }; 396*53ab4af3SHans de Goede }; 397*53ab4af3SHans de Goede 398*53ab4af3SHans de Goede ahb1_rst: reset@01c202c0 { 399*53ab4af3SHans de Goede #reset-cells = <1>; 400*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-clock-reset"; 401*53ab4af3SHans de Goede reg = <0x01c202c0 0xc>; 402*53ab4af3SHans de Goede }; 403*53ab4af3SHans de Goede 404*53ab4af3SHans de Goede apb1_rst: reset@01c202d0 { 405*53ab4af3SHans de Goede #reset-cells = <1>; 406*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-clock-reset"; 407*53ab4af3SHans de Goede reg = <0x01c202d0 0x4>; 408*53ab4af3SHans de Goede }; 409*53ab4af3SHans de Goede 410*53ab4af3SHans de Goede apb2_rst: reset@01c202d8 { 411*53ab4af3SHans de Goede #reset-cells = <1>; 412*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-clock-reset"; 413*53ab4af3SHans de Goede reg = <0x01c202d8 0x4>; 414*53ab4af3SHans de Goede }; 415*53ab4af3SHans de Goede 416*53ab4af3SHans de Goede timer@01c20c00 { 417*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-timer"; 418*53ab4af3SHans de Goede reg = <0x01c20c00 0xa0>; 419*53ab4af3SHans de Goede interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 420*53ab4af3SHans de Goede <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 421*53ab4af3SHans de Goede clocks = <&osc24M>; 422*53ab4af3SHans de Goede }; 423*53ab4af3SHans de Goede 424*53ab4af3SHans de Goede wdt0: watchdog@01c20ca0 { 425*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-wdt"; 426*53ab4af3SHans de Goede reg = <0x01c20ca0 0x20>; 427*53ab4af3SHans de Goede interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 428*53ab4af3SHans de Goede }; 429*53ab4af3SHans de Goede 430*53ab4af3SHans de Goede lradc: lradc@01c22800 { 431*53ab4af3SHans de Goede compatible = "allwinner,sun4i-a10-lradc-keys"; 432*53ab4af3SHans de Goede reg = <0x01c22800 0x100>; 433*53ab4af3SHans de Goede interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 434*53ab4af3SHans de Goede status = "disabled"; 435*53ab4af3SHans de Goede }; 436*53ab4af3SHans de Goede 437*53ab4af3SHans de Goede uart0: serial@01c28000 { 438*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 439*53ab4af3SHans de Goede reg = <0x01c28000 0x400>; 440*53ab4af3SHans de Goede interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 441*53ab4af3SHans de Goede reg-shift = <2>; 442*53ab4af3SHans de Goede reg-io-width = <4>; 443*53ab4af3SHans de Goede clocks = <&apb2_gates 16>; 444*53ab4af3SHans de Goede resets = <&apb2_rst 16>; 445*53ab4af3SHans de Goede dmas = <&dma 6>, <&dma 6>; 446*53ab4af3SHans de Goede dma-names = "rx", "tx"; 447*53ab4af3SHans de Goede status = "disabled"; 448*53ab4af3SHans de Goede }; 449*53ab4af3SHans de Goede 450*53ab4af3SHans de Goede uart1: serial@01c28400 { 451*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 452*53ab4af3SHans de Goede reg = <0x01c28400 0x400>; 453*53ab4af3SHans de Goede interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 454*53ab4af3SHans de Goede reg-shift = <2>; 455*53ab4af3SHans de Goede reg-io-width = <4>; 456*53ab4af3SHans de Goede clocks = <&apb2_gates 17>; 457*53ab4af3SHans de Goede resets = <&apb2_rst 17>; 458*53ab4af3SHans de Goede dmas = <&dma 7>, <&dma 7>; 459*53ab4af3SHans de Goede dma-names = "rx", "tx"; 460*53ab4af3SHans de Goede status = "disabled"; 461*53ab4af3SHans de Goede }; 462*53ab4af3SHans de Goede 463*53ab4af3SHans de Goede uart2: serial@01c28800 { 464*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 465*53ab4af3SHans de Goede reg = <0x01c28800 0x400>; 466*53ab4af3SHans de Goede interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 467*53ab4af3SHans de Goede reg-shift = <2>; 468*53ab4af3SHans de Goede reg-io-width = <4>; 469*53ab4af3SHans de Goede clocks = <&apb2_gates 18>; 470*53ab4af3SHans de Goede resets = <&apb2_rst 18>; 471*53ab4af3SHans de Goede dmas = <&dma 8>, <&dma 8>; 472*53ab4af3SHans de Goede dma-names = "rx", "tx"; 473*53ab4af3SHans de Goede status = "disabled"; 474*53ab4af3SHans de Goede }; 475*53ab4af3SHans de Goede 476*53ab4af3SHans de Goede uart3: serial@01c28c00 { 477*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 478*53ab4af3SHans de Goede reg = <0x01c28c00 0x400>; 479*53ab4af3SHans de Goede interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 480*53ab4af3SHans de Goede reg-shift = <2>; 481*53ab4af3SHans de Goede reg-io-width = <4>; 482*53ab4af3SHans de Goede clocks = <&apb2_gates 19>; 483*53ab4af3SHans de Goede resets = <&apb2_rst 19>; 484*53ab4af3SHans de Goede dmas = <&dma 9>, <&dma 9>; 485*53ab4af3SHans de Goede dma-names = "rx", "tx"; 486*53ab4af3SHans de Goede status = "disabled"; 487*53ab4af3SHans de Goede }; 488*53ab4af3SHans de Goede 489*53ab4af3SHans de Goede uart4: serial@01c29000 { 490*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 491*53ab4af3SHans de Goede reg = <0x01c29000 0x400>; 492*53ab4af3SHans de Goede interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 493*53ab4af3SHans de Goede reg-shift = <2>; 494*53ab4af3SHans de Goede reg-io-width = <4>; 495*53ab4af3SHans de Goede clocks = <&apb2_gates 20>; 496*53ab4af3SHans de Goede resets = <&apb2_rst 20>; 497*53ab4af3SHans de Goede dmas = <&dma 10>, <&dma 10>; 498*53ab4af3SHans de Goede dma-names = "rx", "tx"; 499*53ab4af3SHans de Goede status = "disabled"; 500*53ab4af3SHans de Goede }; 501*53ab4af3SHans de Goede 502*53ab4af3SHans de Goede i2c0: i2c@01c2ac00 { 503*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-i2c"; 504*53ab4af3SHans de Goede reg = <0x01c2ac00 0x400>; 505*53ab4af3SHans de Goede interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 506*53ab4af3SHans de Goede clocks = <&apb2_gates 0>; 507*53ab4af3SHans de Goede resets = <&apb2_rst 0>; 508*53ab4af3SHans de Goede status = "disabled"; 509*53ab4af3SHans de Goede #address-cells = <1>; 510*53ab4af3SHans de Goede #size-cells = <0>; 511*53ab4af3SHans de Goede }; 512*53ab4af3SHans de Goede 513*53ab4af3SHans de Goede i2c1: i2c@01c2b000 { 514*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-i2c"; 515*53ab4af3SHans de Goede reg = <0x01c2b000 0x400>; 516*53ab4af3SHans de Goede interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 517*53ab4af3SHans de Goede clocks = <&apb2_gates 1>; 518*53ab4af3SHans de Goede resets = <&apb2_rst 1>; 519*53ab4af3SHans de Goede status = "disabled"; 520*53ab4af3SHans de Goede #address-cells = <1>; 521*53ab4af3SHans de Goede #size-cells = <0>; 522*53ab4af3SHans de Goede }; 523*53ab4af3SHans de Goede 524*53ab4af3SHans de Goede i2c2: i2c@01c2b400 { 525*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-i2c"; 526*53ab4af3SHans de Goede reg = <0x01c2b400 0x400>; 527*53ab4af3SHans de Goede interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 528*53ab4af3SHans de Goede clocks = <&apb2_gates 2>; 529*53ab4af3SHans de Goede resets = <&apb2_rst 2>; 530*53ab4af3SHans de Goede status = "disabled"; 531*53ab4af3SHans de Goede #address-cells = <1>; 532*53ab4af3SHans de Goede #size-cells = <0>; 533*53ab4af3SHans de Goede }; 534*53ab4af3SHans de Goede 535*53ab4af3SHans de Goede gic: interrupt-controller@01c81000 { 536*53ab4af3SHans de Goede compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 537*53ab4af3SHans de Goede reg = <0x01c81000 0x1000>, 538*53ab4af3SHans de Goede <0x01c82000 0x1000>, 539*53ab4af3SHans de Goede <0x01c84000 0x2000>, 540*53ab4af3SHans de Goede <0x01c86000 0x2000>; 541*53ab4af3SHans de Goede interrupt-controller; 542*53ab4af3SHans de Goede #interrupt-cells = <3>; 543*53ab4af3SHans de Goede interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 544*53ab4af3SHans de Goede }; 545*53ab4af3SHans de Goede 546*53ab4af3SHans de Goede rtc: rtc@01f00000 { 547*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-rtc"; 548*53ab4af3SHans de Goede reg = <0x01f00000 0x54>; 549*53ab4af3SHans de Goede interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 550*53ab4af3SHans de Goede <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 551*53ab4af3SHans de Goede }; 552*53ab4af3SHans de Goede 553*53ab4af3SHans de Goede prcm@01f01400 { 554*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-prcm"; 555*53ab4af3SHans de Goede reg = <0x01f01400 0x200>; 556*53ab4af3SHans de Goede 557*53ab4af3SHans de Goede ar100: ar100_clk { 558*53ab4af3SHans de Goede compatible = "fixed-factor-clock"; 559*53ab4af3SHans de Goede #clock-cells = <0>; 560*53ab4af3SHans de Goede clock-div = <1>; 561*53ab4af3SHans de Goede clock-mult = <1>; 562*53ab4af3SHans de Goede clocks = <&osc24M>; 563*53ab4af3SHans de Goede clock-output-names = "ar100"; 564*53ab4af3SHans de Goede }; 565*53ab4af3SHans de Goede 566*53ab4af3SHans de Goede ahb0: ahb0_clk { 567*53ab4af3SHans de Goede compatible = "fixed-factor-clock"; 568*53ab4af3SHans de Goede #clock-cells = <0>; 569*53ab4af3SHans de Goede clock-div = <1>; 570*53ab4af3SHans de Goede clock-mult = <1>; 571*53ab4af3SHans de Goede clocks = <&ar100>; 572*53ab4af3SHans de Goede clock-output-names = "ahb0"; 573*53ab4af3SHans de Goede }; 574*53ab4af3SHans de Goede 575*53ab4af3SHans de Goede apb0: apb0_clk { 576*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-apb0-clk"; 577*53ab4af3SHans de Goede #clock-cells = <0>; 578*53ab4af3SHans de Goede clocks = <&ahb0>; 579*53ab4af3SHans de Goede clock-output-names = "apb0"; 580*53ab4af3SHans de Goede }; 581*53ab4af3SHans de Goede 582*53ab4af3SHans de Goede apb0_gates: apb0_gates_clk { 583*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 584*53ab4af3SHans de Goede #clock-cells = <1>; 585*53ab4af3SHans de Goede clocks = <&apb0>; 586*53ab4af3SHans de Goede clock-output-names = "apb0_pio", "apb0_timer", 587*53ab4af3SHans de Goede "apb0_rsb", "apb0_uart", 588*53ab4af3SHans de Goede "apb0_i2c"; 589*53ab4af3SHans de Goede }; 590*53ab4af3SHans de Goede 591*53ab4af3SHans de Goede apb0_rst: apb0_rst { 592*53ab4af3SHans de Goede compatible = "allwinner,sun6i-a31-clock-reset"; 593*53ab4af3SHans de Goede #reset-cells = <1>; 594*53ab4af3SHans de Goede }; 595*53ab4af3SHans de Goede }; 596*53ab4af3SHans de Goede 597*53ab4af3SHans de Goede cpucfg@01f01c00 { 598*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-cpuconfig"; 599*53ab4af3SHans de Goede reg = <0x01f01c00 0x300>; 600*53ab4af3SHans de Goede }; 601*53ab4af3SHans de Goede 602*53ab4af3SHans de Goede r_uart: serial@01f02800 { 603*53ab4af3SHans de Goede compatible = "snps,dw-apb-uart"; 604*53ab4af3SHans de Goede reg = <0x01f02800 0x400>; 605*53ab4af3SHans de Goede interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 606*53ab4af3SHans de Goede reg-shift = <2>; 607*53ab4af3SHans de Goede reg-io-width = <4>; 608*53ab4af3SHans de Goede clocks = <&apb0_gates 4>; 609*53ab4af3SHans de Goede resets = <&apb0_rst 4>; 610*53ab4af3SHans de Goede status = "disabled"; 611*53ab4af3SHans de Goede }; 612*53ab4af3SHans de Goede 613*53ab4af3SHans de Goede r_pio: pinctrl@01f02c00 { 614*53ab4af3SHans de Goede compatible = "allwinner,sun8i-a23-r-pinctrl"; 615*53ab4af3SHans de Goede reg = <0x01f02c00 0x400>; 616*53ab4af3SHans de Goede interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 617*53ab4af3SHans de Goede clocks = <&apb0_gates 0>; 618*53ab4af3SHans de Goede resets = <&apb0_rst 0>; 619*53ab4af3SHans de Goede gpio-controller; 620*53ab4af3SHans de Goede interrupt-controller; 621*53ab4af3SHans de Goede #address-cells = <1>; 622*53ab4af3SHans de Goede #size-cells = <0>; 623*53ab4af3SHans de Goede #gpio-cells = <3>; 624*53ab4af3SHans de Goede 625*53ab4af3SHans de Goede r_uart_pins_a: r_uart@0 { 626*53ab4af3SHans de Goede allwinner,pins = "PL2", "PL3"; 627*53ab4af3SHans de Goede allwinner,function = "s_uart"; 628*53ab4af3SHans de Goede allwinner,drive = <SUN4I_PINCTRL_10_MA>; 629*53ab4af3SHans de Goede allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 630*53ab4af3SHans de Goede }; 631*53ab4af3SHans de Goede }; 632*53ab4af3SHans de Goede }; 633*53ab4af3SHans de Goede}; 634