1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 50#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 55 chosen { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 60 simplefb_lcd: framebuffer@0 { 61 compatible = "allwinner,simple-framebuffer", 62 "simple-framebuffer"; 63 allwinner,pipeline = "de_be0-lcd0"; 64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, 65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, 66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; 67 status = "disabled"; 68 }; 69 }; 70 71 timer { 72 compatible = "arm,armv7-timer"; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 clock-frequency = <24000000>; 78 arm,cpu-registers-not-fw-configured; 79 }; 80 81 cpus { 82 enable-method = "allwinner,sun8i-a23"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a7"; 88 device_type = "cpu"; 89 reg = <0>; 90 }; 91 92 cpu@1 { 93 compatible = "arm,cortex-a7"; 94 device_type = "cpu"; 95 reg = <1>; 96 }; 97 }; 98 99 clocks { 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 osc24M: osc24M_clk { 105 #clock-cells = <0>; 106 compatible = "fixed-clock"; 107 clock-frequency = <24000000>; 108 clock-accuracy = <50000>; 109 clock-output-names = "osc24M"; 110 }; 111 112 ext_osc32k: ext_osc32k_clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <32768>; 116 clock-accuracy = <50000>; 117 clock-output-names = "ext-osc32k"; 118 }; 119 }; 120 121 soc@1c00000 { 122 compatible = "simple-bus"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges; 126 127 dma: dma-controller@1c02000 { 128 compatible = "allwinner,sun8i-a23-dma"; 129 reg = <0x01c02000 0x1000>; 130 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&ccu CLK_BUS_DMA>; 132 resets = <&ccu RST_BUS_DMA>; 133 #dma-cells = <1>; 134 }; 135 136 mmc0: mmc@1c0f000 { 137 compatible = "allwinner,sun7i-a20-mmc"; 138 reg = <0x01c0f000 0x1000>; 139 clocks = <&ccu CLK_BUS_MMC0>, 140 <&ccu CLK_MMC0>, 141 <&ccu CLK_MMC0_OUTPUT>, 142 <&ccu CLK_MMC0_SAMPLE>; 143 clock-names = "ahb", 144 "mmc", 145 "output", 146 "sample"; 147 resets = <&ccu RST_BUS_MMC0>; 148 reset-names = "ahb"; 149 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 150 status = "disabled"; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 }; 154 155 mmc1: mmc@1c10000 { 156 compatible = "allwinner,sun7i-a20-mmc"; 157 reg = <0x01c10000 0x1000>; 158 clocks = <&ccu CLK_BUS_MMC1>, 159 <&ccu CLK_MMC1>, 160 <&ccu CLK_MMC1_OUTPUT>, 161 <&ccu CLK_MMC1_SAMPLE>; 162 clock-names = "ahb", 163 "mmc", 164 "output", 165 "sample"; 166 resets = <&ccu RST_BUS_MMC1>; 167 reset-names = "ahb"; 168 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 169 status = "disabled"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 }; 173 174 mmc2: mmc@1c11000 { 175 compatible = "allwinner,sun7i-a20-mmc"; 176 reg = <0x01c11000 0x1000>; 177 clocks = <&ccu CLK_BUS_MMC2>, 178 <&ccu CLK_MMC2>, 179 <&ccu CLK_MMC2_OUTPUT>, 180 <&ccu CLK_MMC2_SAMPLE>; 181 clock-names = "ahb", 182 "mmc", 183 "output", 184 "sample"; 185 resets = <&ccu RST_BUS_MMC2>; 186 reset-names = "ahb"; 187 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 188 status = "disabled"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 }; 192 193 nfc: nand@1c03000 { 194 compatible = "allwinner,sun4i-a10-nand"; 195 reg = <0x01c03000 0x1000>; 196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; 198 clock-names = "ahb", "mod"; 199 resets = <&ccu RST_BUS_NAND>; 200 reset-names = "ahb"; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; 203 status = "disabled"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 }; 207 208 usb_otg: usb@1c19000 { 209 /* compatible gets set in SoC specific dtsi file */ 210 reg = <0x01c19000 0x0400>; 211 clocks = <&ccu CLK_BUS_OTG>; 212 resets = <&ccu RST_BUS_OTG>; 213 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 214 interrupt-names = "mc"; 215 phys = <&usbphy 0>; 216 phy-names = "usb"; 217 extcon = <&usbphy 0>; 218 status = "disabled"; 219 }; 220 221 usbphy: phy@1c19400 { 222 /* 223 * compatible and address regions get set in 224 * SoC specific dtsi file 225 */ 226 clocks = <&ccu CLK_USB_PHY0>, 227 <&ccu CLK_USB_PHY1>; 228 clock-names = "usb0_phy", 229 "usb1_phy"; 230 resets = <&ccu RST_USB_PHY0>, 231 <&ccu RST_USB_PHY1>; 232 reset-names = "usb0_reset", 233 "usb1_reset"; 234 status = "disabled"; 235 #phy-cells = <1>; 236 }; 237 238 ehci0: usb@1c1a000 { 239 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 240 reg = <0x01c1a000 0x100>; 241 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&ccu CLK_BUS_EHCI>; 243 resets = <&ccu RST_BUS_EHCI>; 244 phys = <&usbphy 1>; 245 phy-names = "usb"; 246 status = "disabled"; 247 }; 248 249 ohci0: usb@1c1a400 { 250 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 251 reg = <0x01c1a400 0x100>; 252 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; 254 resets = <&ccu RST_BUS_OHCI>; 255 phys = <&usbphy 1>; 256 phy-names = "usb"; 257 status = "disabled"; 258 }; 259 260 ccu: clock@1c20000 { 261 reg = <0x01c20000 0x400>; 262 clocks = <&osc24M>, <&rtc 0>; 263 clock-names = "hosc", "losc"; 264 #clock-cells = <1>; 265 #reset-cells = <1>; 266 }; 267 268 pio: pinctrl@1c20800 { 269 /* compatible gets set in SoC specific dtsi file */ 270 reg = <0x01c20800 0x400>; 271 /* interrupts get set in SoC specific dtsi file */ 272 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 273 clock-names = "apb", "hosc", "losc"; 274 gpio-controller; 275 interrupt-controller; 276 #interrupt-cells = <3>; 277 #gpio-cells = <3>; 278 279 uart0_pins_a: uart0@0 { 280 pins = "PF2", "PF4"; 281 function = "uart0"; 282 }; 283 284 uart1_pins_a: uart1@0 { 285 pins = "PG6", "PG7"; 286 function = "uart1"; 287 }; 288 289 uart1_pins_cts_rts_a: uart1-cts-rts@0 { 290 pins = "PG8", "PG9"; 291 function = "uart1"; 292 }; 293 294 mmc0_pins_a: mmc0@0 { 295 pins = "PF0", "PF1", "PF2", 296 "PF3", "PF4", "PF5"; 297 function = "mmc0"; 298 drive-strength = <30>; 299 bias-pull-up; 300 }; 301 302 mmc1_pins_a: mmc1@0 { 303 pins = "PG0", "PG1", "PG2", 304 "PG3", "PG4", "PG5"; 305 function = "mmc1"; 306 drive-strength = <30>; 307 bias-pull-up; 308 }; 309 310 mmc2_8bit_pins: mmc2_8bit { 311 pins = "PC5", "PC6", "PC8", 312 "PC9", "PC10", "PC11", 313 "PC12", "PC13", "PC14", 314 "PC15", "PC16"; 315 function = "mmc2"; 316 drive-strength = <30>; 317 bias-pull-up; 318 }; 319 320 nand_pins: nand-pins { 321 pins = "PC0", "PC1", "PC2", "PC5", 322 "PC8", "PC9", "PC10", "PC11", 323 "PC12", "PC13", "PC14", "PC15"; 324 function = "nand0"; 325 }; 326 327 nand_pins_cs0: nand-pins-cs0 { 328 pins = "PC4"; 329 function = "nand0"; 330 bias-pull-up; 331 }; 332 333 nand_pins_cs1: nand-pins-cs1 { 334 pins = "PC3"; 335 function = "nand0"; 336 bias-pull-up; 337 }; 338 339 nand_pins_rb0: nand-pins-rb0 { 340 pins = "PC6"; 341 function = "nand0"; 342 bias-pull-up; 343 }; 344 345 nand_pins_rb1: nand-pins-rb1 { 346 pins = "PC7"; 347 function = "nand0"; 348 bias-pull-up; 349 }; 350 351 pwm0_pins: pwm0 { 352 pins = "PH0"; 353 function = "pwm0"; 354 }; 355 356 i2c0_pins_a: i2c0@0 { 357 pins = "PH2", "PH3"; 358 function = "i2c0"; 359 }; 360 361 i2c1_pins_a: i2c1@0 { 362 pins = "PH4", "PH5"; 363 function = "i2c1"; 364 }; 365 366 i2c2_pins_a: i2c2@0 { 367 pins = "PE12", "PE13"; 368 function = "i2c2"; 369 }; 370 371 lcd_rgb666_pins: lcd-rgb666@0 { 372 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 373 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 374 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 375 "PD24", "PD25", "PD26", "PD27"; 376 function = "lcd0"; 377 }; 378 }; 379 380 timer@1c20c00 { 381 compatible = "allwinner,sun4i-a10-timer"; 382 reg = <0x01c20c00 0xa0>; 383 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&osc24M>; 386 }; 387 388 wdt0: watchdog@1c20ca0 { 389 compatible = "allwinner,sun6i-a31-wdt"; 390 reg = <0x01c20ca0 0x20>; 391 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 392 }; 393 394 pwm: pwm@1c21400 { 395 compatible = "allwinner,sun7i-a20-pwm"; 396 reg = <0x01c21400 0xc>; 397 clocks = <&osc24M>; 398 #pwm-cells = <3>; 399 status = "disabled"; 400 }; 401 402 lradc: lradc@1c22800 { 403 compatible = "allwinner,sun4i-a10-lradc-keys"; 404 reg = <0x01c22800 0x100>; 405 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 406 status = "disabled"; 407 }; 408 409 uart0: serial@1c28000 { 410 compatible = "snps,dw-apb-uart"; 411 reg = <0x01c28000 0x400>; 412 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 413 reg-shift = <2>; 414 reg-io-width = <4>; 415 clocks = <&ccu CLK_BUS_UART0>; 416 resets = <&ccu RST_BUS_UART0>; 417 dmas = <&dma 6>, <&dma 6>; 418 dma-names = "rx", "tx"; 419 status = "disabled"; 420 }; 421 422 uart1: serial@1c28400 { 423 compatible = "snps,dw-apb-uart"; 424 reg = <0x01c28400 0x400>; 425 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 426 reg-shift = <2>; 427 reg-io-width = <4>; 428 clocks = <&ccu CLK_BUS_UART1>; 429 resets = <&ccu RST_BUS_UART1>; 430 dmas = <&dma 7>, <&dma 7>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 uart2: serial@1c28800 { 436 compatible = "snps,dw-apb-uart"; 437 reg = <0x01c28800 0x400>; 438 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 439 reg-shift = <2>; 440 reg-io-width = <4>; 441 clocks = <&ccu CLK_BUS_UART2>; 442 resets = <&ccu RST_BUS_UART2>; 443 dmas = <&dma 8>, <&dma 8>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 uart3: serial@1c28c00 { 449 compatible = "snps,dw-apb-uart"; 450 reg = <0x01c28c00 0x400>; 451 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 452 reg-shift = <2>; 453 reg-io-width = <4>; 454 clocks = <&ccu CLK_BUS_UART3>; 455 resets = <&ccu RST_BUS_UART3>; 456 dmas = <&dma 9>, <&dma 9>; 457 dma-names = "rx", "tx"; 458 status = "disabled"; 459 }; 460 461 uart4: serial@1c29000 { 462 compatible = "snps,dw-apb-uart"; 463 reg = <0x01c29000 0x400>; 464 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 clocks = <&ccu CLK_BUS_UART4>; 468 resets = <&ccu RST_BUS_UART4>; 469 dmas = <&dma 10>, <&dma 10>; 470 dma-names = "rx", "tx"; 471 status = "disabled"; 472 }; 473 474 i2c0: i2c@1c2ac00 { 475 compatible = "allwinner,sun6i-a31-i2c"; 476 reg = <0x01c2ac00 0x400>; 477 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&ccu CLK_BUS_I2C0>; 479 resets = <&ccu RST_BUS_I2C0>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 i2c1: i2c@1c2b000 { 486 compatible = "allwinner,sun6i-a31-i2c"; 487 reg = <0x01c2b000 0x400>; 488 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&ccu CLK_BUS_I2C1>; 490 resets = <&ccu RST_BUS_I2C1>; 491 status = "disabled"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 }; 495 496 i2c2: i2c@1c2b400 { 497 compatible = "allwinner,sun6i-a31-i2c"; 498 reg = <0x01c2b400 0x400>; 499 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&ccu CLK_BUS_I2C2>; 501 resets = <&ccu RST_BUS_I2C2>; 502 status = "disabled"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 }; 506 507 mali: gpu@1c40000 { 508 compatible = "allwinner,sun8i-a23-mali", 509 "allwinner,sun7i-a20-mali", "arm,mali-400"; 510 reg = <0x01c40000 0x10000>; 511 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "gp", 519 "gpmmu", 520 "pp0", 521 "ppmmu0", 522 "pp1", 523 "ppmmu1", 524 "pmu"; 525 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 526 clock-names = "bus", "core"; 527 resets = <&ccu RST_BUS_GPU>; 528 #cooling-cells = <2>; 529 530 assigned-clocks = <&ccu CLK_GPU>; 531 assigned-clock-rates = <384000000>; 532 }; 533 534 gic: interrupt-controller@1c81000 { 535 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 536 reg = <0x01c81000 0x1000>, 537 <0x01c82000 0x2000>, 538 <0x01c84000 0x2000>, 539 <0x01c86000 0x2000>; 540 interrupt-controller; 541 #interrupt-cells = <3>; 542 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 543 }; 544 545 rtc: rtc@1f00000 { 546 compatible = "allwinner,sun6i-a31-rtc"; 547 reg = <0x01f00000 0x54>; 548 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 550 clock-output-names = "osc32k"; 551 clocks = <&ext_osc32k>; 552 #clock-cells = <1>; 553 }; 554 555 nmi_intc: interrupt-controller@1f00c00 { 556 compatible = "allwinner,sun6i-a31-r-intc"; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 reg = <0x01f00c00 0x400>; 560 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 561 }; 562 563 prcm@1f01400 { 564 compatible = "allwinner,sun8i-a23-prcm"; 565 reg = <0x01f01400 0x200>; 566 567 ar100: ar100_clk { 568 compatible = "fixed-factor-clock"; 569 #clock-cells = <0>; 570 clock-div = <1>; 571 clock-mult = <1>; 572 clocks = <&osc24M>; 573 clock-output-names = "ar100"; 574 }; 575 576 ahb0: ahb0_clk { 577 compatible = "fixed-factor-clock"; 578 #clock-cells = <0>; 579 clock-div = <1>; 580 clock-mult = <1>; 581 clocks = <&ar100>; 582 clock-output-names = "ahb0"; 583 }; 584 585 apb0: apb0_clk { 586 compatible = "allwinner,sun8i-a23-apb0-clk"; 587 #clock-cells = <0>; 588 clocks = <&ahb0>; 589 clock-output-names = "apb0"; 590 }; 591 592 apb0_gates: apb0_gates_clk { 593 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 594 #clock-cells = <1>; 595 clocks = <&apb0>; 596 clock-output-names = "apb0_pio", "apb0_timer", 597 "apb0_rsb", "apb0_uart", 598 "apb0_i2c"; 599 }; 600 601 apb0_rst: apb0_rst { 602 compatible = "allwinner,sun6i-a31-clock-reset"; 603 #reset-cells = <1>; 604 }; 605 606 codec_analog: codec-analog { 607 compatible = "allwinner,sun8i-a23-codec-analog"; 608 }; 609 }; 610 611 cpucfg@1f01c00 { 612 compatible = "allwinner,sun8i-a23-cpuconfig"; 613 reg = <0x01f01c00 0x300>; 614 }; 615 616 r_uart: serial@1f02800 { 617 compatible = "snps,dw-apb-uart"; 618 reg = <0x01f02800 0x400>; 619 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 620 reg-shift = <2>; 621 reg-io-width = <4>; 622 clocks = <&apb0_gates 4>; 623 resets = <&apb0_rst 4>; 624 status = "disabled"; 625 }; 626 627 r_pio: pinctrl@1f02c00 { 628 compatible = "allwinner,sun8i-a23-r-pinctrl"; 629 reg = <0x01f02c00 0x400>; 630 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 632 clock-names = "apb", "hosc", "losc"; 633 resets = <&apb0_rst 0>; 634 gpio-controller; 635 interrupt-controller; 636 #interrupt-cells = <3>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 #gpio-cells = <3>; 640 641 r_rsb_pins: r_rsb { 642 pins = "PL0", "PL1"; 643 function = "s_rsb"; 644 drive-strength = <20>; 645 bias-pull-up; 646 }; 647 648 r_uart_pins_a: r_uart@0 { 649 pins = "PL2", "PL3"; 650 function = "s_uart"; 651 }; 652 }; 653 654 r_rsb: rsb@1f03400 { 655 compatible = "allwinner,sun8i-a23-rsb"; 656 reg = <0x01f03400 0x400>; 657 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&apb0_gates 3>; 659 clock-frequency = <3000000>; 660 resets = <&apb0_rst 3>; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&r_rsb_pins>; 663 status = "disabled"; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 }; 667 }; 668}; 669