1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 50#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 55 chosen { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 ranges; 59 60 simplefb_lcd: framebuffer@0 { 61 compatible = "allwinner,simple-framebuffer", 62 "simple-framebuffer"; 63 allwinner,pipeline = "de_be0-lcd0"; 64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, 65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, 66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; 67 status = "disabled"; 68 }; 69 }; 70 71 timer { 72 compatible = "arm,armv7-timer"; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 77 clock-frequency = <24000000>; 78 arm,cpu-registers-not-fw-configured; 79 }; 80 81 cpus { 82 enable-method = "allwinner,sun8i-a23"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a7"; 88 device_type = "cpu"; 89 reg = <0>; 90 }; 91 92 cpu@1 { 93 compatible = "arm,cortex-a7"; 94 device_type = "cpu"; 95 reg = <1>; 96 }; 97 }; 98 99 clocks { 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 osc24M: osc24M_clk { 105 #clock-cells = <0>; 106 compatible = "fixed-clock"; 107 clock-frequency = <24000000>; 108 clock-accuracy = <50000>; 109 clock-output-names = "osc24M"; 110 }; 111 112 ext_osc32k: ext_osc32k_clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <32768>; 116 clock-accuracy = <50000>; 117 clock-output-names = "ext-osc32k"; 118 }; 119 }; 120 121 soc@01c00000 { 122 compatible = "simple-bus"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges; 126 127 dma: dma-controller@01c02000 { 128 compatible = "allwinner,sun8i-a23-dma"; 129 reg = <0x01c02000 0x1000>; 130 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&ccu CLK_BUS_DMA>; 132 resets = <&ccu RST_BUS_DMA>; 133 #dma-cells = <1>; 134 }; 135 136 mmc0: mmc@01c0f000 { 137 compatible = "allwinner,sun7i-a20-mmc"; 138 reg = <0x01c0f000 0x1000>; 139 clocks = <&ccu CLK_BUS_MMC0>, 140 <&ccu CLK_MMC0>, 141 <&ccu CLK_MMC0_OUTPUT>, 142 <&ccu CLK_MMC0_SAMPLE>; 143 clock-names = "ahb", 144 "mmc", 145 "output", 146 "sample"; 147 resets = <&ccu RST_BUS_MMC0>; 148 reset-names = "ahb"; 149 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 150 status = "disabled"; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 }; 154 155 mmc1: mmc@01c10000 { 156 compatible = "allwinner,sun7i-a20-mmc"; 157 reg = <0x01c10000 0x1000>; 158 clocks = <&ccu CLK_BUS_MMC1>, 159 <&ccu CLK_MMC1>, 160 <&ccu CLK_MMC1_OUTPUT>, 161 <&ccu CLK_MMC1_SAMPLE>; 162 clock-names = "ahb", 163 "mmc", 164 "output", 165 "sample"; 166 resets = <&ccu RST_BUS_MMC1>; 167 reset-names = "ahb"; 168 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 169 status = "disabled"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 }; 173 174 mmc2: mmc@01c11000 { 175 compatible = "allwinner,sun7i-a20-mmc"; 176 reg = <0x01c11000 0x1000>; 177 clocks = <&ccu CLK_BUS_MMC2>, 178 <&ccu CLK_MMC2>, 179 <&ccu CLK_MMC2_OUTPUT>, 180 <&ccu CLK_MMC2_SAMPLE>; 181 clock-names = "ahb", 182 "mmc", 183 "output", 184 "sample"; 185 resets = <&ccu RST_BUS_MMC2>; 186 reset-names = "ahb"; 187 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 188 status = "disabled"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 }; 192 193 nfc: nand@01c03000 { 194 compatible = "allwinner,sun4i-a10-nand"; 195 reg = <0x01c03000 0x1000>; 196 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; 198 clock-names = "ahb", "mod"; 199 resets = <&ccu RST_BUS_NAND>; 200 reset-names = "ahb"; 201 status = "disabled"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 }; 205 206 usb_otg: usb@01c19000 { 207 /* compatible gets set in SoC specific dtsi file */ 208 reg = <0x01c19000 0x0400>; 209 clocks = <&ccu CLK_BUS_OTG>; 210 resets = <&ccu RST_BUS_OTG>; 211 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "mc"; 213 phys = <&usbphy 0>; 214 phy-names = "usb"; 215 extcon = <&usbphy 0>; 216 status = "disabled"; 217 }; 218 219 usbphy: phy@01c19400 { 220 /* 221 * compatible and address regions get set in 222 * SoC specific dtsi file 223 */ 224 clocks = <&ccu CLK_USB_PHY0>, 225 <&ccu CLK_USB_PHY1>; 226 clock-names = "usb0_phy", 227 "usb1_phy"; 228 resets = <&ccu RST_USB_PHY0>, 229 <&ccu RST_USB_PHY1>; 230 reset-names = "usb0_reset", 231 "usb1_reset"; 232 status = "disabled"; 233 #phy-cells = <1>; 234 }; 235 236 ehci0: usb@01c1a000 { 237 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 238 reg = <0x01c1a000 0x100>; 239 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&ccu CLK_BUS_EHCI>; 241 resets = <&ccu RST_BUS_EHCI>; 242 phys = <&usbphy 1>; 243 phy-names = "usb"; 244 status = "disabled"; 245 }; 246 247 ohci0: usb@01c1a400 { 248 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 249 reg = <0x01c1a400 0x100>; 250 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; 252 resets = <&ccu RST_BUS_OHCI>; 253 phys = <&usbphy 1>; 254 phy-names = "usb"; 255 status = "disabled"; 256 }; 257 258 ccu: clock@01c20000 { 259 reg = <0x01c20000 0x400>; 260 clocks = <&osc24M>, <&rtc 0>; 261 clock-names = "hosc", "losc"; 262 #clock-cells = <1>; 263 #reset-cells = <1>; 264 }; 265 266 pio: pinctrl@01c20800 { 267 /* compatible gets set in SoC specific dtsi file */ 268 reg = <0x01c20800 0x400>; 269 /* interrupts get set in SoC specific dtsi file */ 270 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 271 clock-names = "apb", "hosc", "losc"; 272 gpio-controller; 273 interrupt-controller; 274 #interrupt-cells = <3>; 275 #gpio-cells = <3>; 276 277 uart0_pins_a: uart0@0 { 278 pins = "PF2", "PF4"; 279 function = "uart0"; 280 }; 281 282 uart1_pins_a: uart1@0 { 283 pins = "PG6", "PG7"; 284 function = "uart1"; 285 }; 286 287 uart1_pins_cts_rts_a: uart1-cts-rts@0 { 288 pins = "PG8", "PG9"; 289 function = "uart1"; 290 }; 291 292 nand_pins_a: nand-base0@0 { 293 pins = "PC0", "PC1", "PC2", "PC5", 294 "PC8", "PC9", "PC10", "PC11", 295 "PC12", "PC13", "PC14", "PC15"; 296 function = "nand0"; 297 }; 298 299 nand_cs0_pins_a: nand-cs@0 { 300 pins = "PC4"; 301 function = "nand0"; 302 }; 303 304 nand_rb0_pins_a: nand-rb@0 { 305 pins = "PC6"; 306 function = "nand0"; 307 }; 308 309 mmc0_pins_a: mmc0@0 { 310 pins = "PF0", "PF1", "PF2", 311 "PF3", "PF4", "PF5"; 312 function = "mmc0"; 313 drive-strength = <30>; 314 bias-pull-up; 315 }; 316 317 mmc1_pins_a: mmc1@0 { 318 pins = "PG0", "PG1", "PG2", 319 "PG3", "PG4", "PG5"; 320 function = "mmc1"; 321 drive-strength = <30>; 322 bias-pull-up; 323 }; 324 325 mmc2_8bit_pins: mmc2_8bit { 326 pins = "PC5", "PC6", "PC8", 327 "PC9", "PC10", "PC11", 328 "PC12", "PC13", "PC14", 329 "PC15", "PC16"; 330 function = "mmc2"; 331 drive-strength = <30>; 332 bias-pull-up; 333 }; 334 335 pwm0_pins: pwm0 { 336 pins = "PH0"; 337 function = "pwm0"; 338 }; 339 340 i2c0_pins_a: i2c0@0 { 341 pins = "PH2", "PH3"; 342 function = "i2c0"; 343 }; 344 345 i2c1_pins_a: i2c1@0 { 346 pins = "PH4", "PH5"; 347 function = "i2c1"; 348 }; 349 350 i2c2_pins_a: i2c2@0 { 351 pins = "PE12", "PE13"; 352 function = "i2c2"; 353 }; 354 355 lcd_rgb666_pins: lcd-rgb666@0 { 356 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 357 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 358 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 359 "PD24", "PD25", "PD26", "PD27"; 360 function = "lcd0"; 361 }; 362 }; 363 364 timer@01c20c00 { 365 compatible = "allwinner,sun4i-a10-timer"; 366 reg = <0x01c20c00 0xa0>; 367 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&osc24M>; 370 }; 371 372 wdt0: watchdog@01c20ca0 { 373 compatible = "allwinner,sun6i-a31-wdt"; 374 reg = <0x01c20ca0 0x20>; 375 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 376 }; 377 378 pwm: pwm@01c21400 { 379 compatible = "allwinner,sun7i-a20-pwm"; 380 reg = <0x01c21400 0xc>; 381 clocks = <&osc24M>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 lradc: lradc@01c22800 { 387 compatible = "allwinner,sun4i-a10-lradc-keys"; 388 reg = <0x01c22800 0x100>; 389 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 390 status = "disabled"; 391 }; 392 393 uart0: serial@01c28000 { 394 compatible = "snps,dw-apb-uart"; 395 reg = <0x01c28000 0x400>; 396 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 397 reg-shift = <2>; 398 reg-io-width = <4>; 399 clocks = <&ccu CLK_BUS_UART0>; 400 resets = <&ccu RST_BUS_UART0>; 401 dmas = <&dma 6>, <&dma 6>; 402 dma-names = "rx", "tx"; 403 status = "disabled"; 404 }; 405 406 uart1: serial@01c28400 { 407 compatible = "snps,dw-apb-uart"; 408 reg = <0x01c28400 0x400>; 409 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 410 reg-shift = <2>; 411 reg-io-width = <4>; 412 clocks = <&ccu CLK_BUS_UART1>; 413 resets = <&ccu RST_BUS_UART1>; 414 dmas = <&dma 7>, <&dma 7>; 415 dma-names = "rx", "tx"; 416 status = "disabled"; 417 }; 418 419 uart2: serial@01c28800 { 420 compatible = "snps,dw-apb-uart"; 421 reg = <0x01c28800 0x400>; 422 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 423 reg-shift = <2>; 424 reg-io-width = <4>; 425 clocks = <&ccu CLK_BUS_UART2>; 426 resets = <&ccu RST_BUS_UART2>; 427 dmas = <&dma 8>, <&dma 8>; 428 dma-names = "rx", "tx"; 429 status = "disabled"; 430 }; 431 432 uart3: serial@01c28c00 { 433 compatible = "snps,dw-apb-uart"; 434 reg = <0x01c28c00 0x400>; 435 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 436 reg-shift = <2>; 437 reg-io-width = <4>; 438 clocks = <&ccu CLK_BUS_UART3>; 439 resets = <&ccu RST_BUS_UART3>; 440 dmas = <&dma 9>, <&dma 9>; 441 dma-names = "rx", "tx"; 442 status = "disabled"; 443 }; 444 445 uart4: serial@01c29000 { 446 compatible = "snps,dw-apb-uart"; 447 reg = <0x01c29000 0x400>; 448 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 449 reg-shift = <2>; 450 reg-io-width = <4>; 451 clocks = <&ccu CLK_BUS_UART4>; 452 resets = <&ccu RST_BUS_UART4>; 453 dmas = <&dma 10>, <&dma 10>; 454 dma-names = "rx", "tx"; 455 status = "disabled"; 456 }; 457 458 i2c0: i2c@01c2ac00 { 459 compatible = "allwinner,sun6i-a31-i2c"; 460 reg = <0x01c2ac00 0x400>; 461 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&ccu CLK_BUS_I2C0>; 463 resets = <&ccu RST_BUS_I2C0>; 464 status = "disabled"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 }; 468 469 i2c1: i2c@01c2b000 { 470 compatible = "allwinner,sun6i-a31-i2c"; 471 reg = <0x01c2b000 0x400>; 472 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&ccu CLK_BUS_I2C1>; 474 resets = <&ccu RST_BUS_I2C1>; 475 status = "disabled"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 }; 479 480 i2c2: i2c@01c2b400 { 481 compatible = "allwinner,sun6i-a31-i2c"; 482 reg = <0x01c2b400 0x400>; 483 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&ccu CLK_BUS_I2C2>; 485 resets = <&ccu RST_BUS_I2C2>; 486 status = "disabled"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 491 mali: gpu@1c40000 { 492 compatible = "allwinner,sun8i-a23-mali", 493 "allwinner,sun7i-a20-mali", "arm,mali-400"; 494 reg = <0x01c40000 0x10000>; 495 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "gp", 503 "gpmmu", 504 "pp0", 505 "ppmmu0", 506 "pp1", 507 "ppmmu1", 508 "pmu"; 509 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 510 clock-names = "bus", "core"; 511 resets = <&ccu RST_BUS_GPU>; 512 #cooling-cells = <2>; 513 514 assigned-clocks = <&ccu CLK_GPU>; 515 assigned-clock-rates = <384000000>; 516 }; 517 518 gic: interrupt-controller@01c81000 { 519 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 520 reg = <0x01c81000 0x1000>, 521 <0x01c82000 0x2000>, 522 <0x01c84000 0x2000>, 523 <0x01c86000 0x2000>; 524 interrupt-controller; 525 #interrupt-cells = <3>; 526 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 527 }; 528 529 rtc: rtc@01f00000 { 530 compatible = "allwinner,sun6i-a31-rtc"; 531 reg = <0x01f00000 0x54>; 532 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 534 clock-output-names = "osc32k"; 535 clocks = <&ext_osc32k>; 536 #clock-cells = <1>; 537 }; 538 539 nmi_intc: interrupt-controller@1f00c00 { 540 compatible = "allwinner,sun6i-a31-r-intc"; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 reg = <0x01f00c00 0x400>; 544 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 545 }; 546 547 prcm@01f01400 { 548 compatible = "allwinner,sun8i-a23-prcm"; 549 reg = <0x01f01400 0x200>; 550 551 ar100: ar100_clk { 552 compatible = "fixed-factor-clock"; 553 #clock-cells = <0>; 554 clock-div = <1>; 555 clock-mult = <1>; 556 clocks = <&osc24M>; 557 clock-output-names = "ar100"; 558 }; 559 560 ahb0: ahb0_clk { 561 compatible = "fixed-factor-clock"; 562 #clock-cells = <0>; 563 clock-div = <1>; 564 clock-mult = <1>; 565 clocks = <&ar100>; 566 clock-output-names = "ahb0"; 567 }; 568 569 apb0: apb0_clk { 570 compatible = "allwinner,sun8i-a23-apb0-clk"; 571 #clock-cells = <0>; 572 clocks = <&ahb0>; 573 clock-output-names = "apb0"; 574 }; 575 576 apb0_gates: apb0_gates_clk { 577 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 578 #clock-cells = <1>; 579 clocks = <&apb0>; 580 clock-output-names = "apb0_pio", "apb0_timer", 581 "apb0_rsb", "apb0_uart", 582 "apb0_i2c"; 583 }; 584 585 apb0_rst: apb0_rst { 586 compatible = "allwinner,sun6i-a31-clock-reset"; 587 #reset-cells = <1>; 588 }; 589 590 codec_analog: codec-analog { 591 compatible = "allwinner,sun8i-a23-codec-analog"; 592 }; 593 }; 594 595 cpucfg@01f01c00 { 596 compatible = "allwinner,sun8i-a23-cpuconfig"; 597 reg = <0x01f01c00 0x300>; 598 }; 599 600 r_uart: serial@01f02800 { 601 compatible = "snps,dw-apb-uart"; 602 reg = <0x01f02800 0x400>; 603 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 604 reg-shift = <2>; 605 reg-io-width = <4>; 606 clocks = <&apb0_gates 4>; 607 resets = <&apb0_rst 4>; 608 status = "disabled"; 609 }; 610 611 r_pio: pinctrl@01f02c00 { 612 compatible = "allwinner,sun8i-a23-r-pinctrl"; 613 reg = <0x01f02c00 0x400>; 614 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 616 clock-names = "apb", "hosc", "losc"; 617 resets = <&apb0_rst 0>; 618 gpio-controller; 619 interrupt-controller; 620 #interrupt-cells = <3>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 #gpio-cells = <3>; 624 625 r_rsb_pins: r_rsb { 626 pins = "PL0", "PL1"; 627 function = "s_rsb"; 628 drive-strength = <20>; 629 bias-pull-up; 630 }; 631 632 r_uart_pins_a: r_uart@0 { 633 pins = "PL2", "PL3"; 634 function = "s_uart"; 635 }; 636 }; 637 638 r_rsb: rsb@01f03400 { 639 compatible = "allwinner,sun8i-a23-rsb"; 640 reg = <0x01f03400 0x400>; 641 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&apb0_gates 3>; 643 clock-frequency = <3000000>; 644 resets = <&apb0_rst 3>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&r_rsb_pins>; 647 status = "disabled"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 }; 651 }; 652}; 653