1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/pinctrl/sun4i-a10.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 54 chosen { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 simplefb_lcd: framebuffer@0 { 60 compatible = "allwinner,simple-framebuffer", 61 "simple-framebuffer"; 62 allwinner,pipeline = "de_be0-lcd0"; 63 clocks = <&pll6 0>; 64 status = "disabled"; 65 }; 66 }; 67 68 timer { 69 compatible = "arm,armv7-timer"; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 74 clock-frequency = <24000000>; 75 arm,cpu-registers-not-fw-configured; 76 }; 77 78 cpus { 79 enable-method = "allwinner,sun8i-a23"; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 cpu@0 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0>; 87 }; 88 89 cpu@1 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <1>; 93 }; 94 }; 95 96 clocks { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 osc24M: osc24M_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <24000000>; 105 clock-output-names = "osc24M"; 106 }; 107 108 osc32k: osc32k_clk { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 clock-frequency = <32768>; 112 clock-output-names = "osc32k"; 113 }; 114 115 pll1: clk@01c20000 { 116 #clock-cells = <0>; 117 compatible = "allwinner,sun8i-a23-pll1-clk"; 118 reg = <0x01c20000 0x4>; 119 clocks = <&osc24M>; 120 clock-output-names = "pll1"; 121 }; 122 123 /* dummy clock until actually implemented */ 124 pll5: pll5_clk { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <0>; 128 clock-output-names = "pll5"; 129 }; 130 131 pll6: clk@01c20028 { 132 #clock-cells = <1>; 133 compatible = "allwinner,sun6i-a31-pll6-clk"; 134 reg = <0x01c20028 0x4>; 135 clocks = <&osc24M>; 136 clock-output-names = "pll6", "pll6x2"; 137 }; 138 139 cpu: cpu_clk@01c20050 { 140 #clock-cells = <0>; 141 compatible = "allwinner,sun4i-a10-cpu-clk"; 142 reg = <0x01c20050 0x4>; 143 144 /* 145 * PLL1 is listed twice here. 146 * While it looks suspicious, it's actually documented 147 * that way both in the datasheet and in the code from 148 * Allwinner. 149 */ 150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 151 clock-output-names = "cpu"; 152 }; 153 154 axi: axi_clk@01c20050 { 155 #clock-cells = <0>; 156 compatible = "allwinner,sun8i-a23-axi-clk"; 157 reg = <0x01c20050 0x4>; 158 clocks = <&cpu>; 159 clock-output-names = "axi"; 160 }; 161 162 ahb1: ahb1_clk@01c20054 { 163 #clock-cells = <0>; 164 compatible = "allwinner,sun6i-a31-ahb1-clk"; 165 reg = <0x01c20054 0x4>; 166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 167 clock-output-names = "ahb1"; 168 }; 169 170 apb1: apb1_clk@01c20054 { 171 #clock-cells = <0>; 172 compatible = "allwinner,sun4i-a10-apb0-clk"; 173 reg = <0x01c20054 0x4>; 174 clocks = <&ahb1>; 175 clock-output-names = "apb1"; 176 }; 177 178 apb1_gates: clk@01c20068 { 179 #clock-cells = <1>; 180 compatible = "allwinner,sun8i-a23-apb1-gates-clk"; 181 reg = <0x01c20068 0x4>; 182 clocks = <&apb1>; 183 clock-indices = <0>, <5>, 184 <12>, <13>; 185 clock-output-names = "apb1_codec", "apb1_pio", 186 "apb1_daudio0", "apb1_daudio1"; 187 }; 188 189 apb2: clk@01c20058 { 190 #clock-cells = <0>; 191 compatible = "allwinner,sun4i-a10-apb1-clk"; 192 reg = <0x01c20058 0x4>; 193 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 194 clock-output-names = "apb2"; 195 }; 196 197 apb2_gates: clk@01c2006c { 198 #clock-cells = <1>; 199 compatible = "allwinner,sun8i-a23-apb2-gates-clk"; 200 reg = <0x01c2006c 0x4>; 201 clocks = <&apb2>; 202 clock-indices = <0>, <1>, 203 <2>, <16>, 204 <17>, <18>, 205 <19>, <20>; 206 clock-output-names = "apb2_i2c0", "apb2_i2c1", 207 "apb2_i2c2", "apb2_uart0", 208 "apb2_uart1", "apb2_uart2", 209 "apb2_uart3", "apb2_uart4"; 210 }; 211 212 mmc0_clk: clk@01c20088 { 213 #clock-cells = <1>; 214 compatible = "allwinner,sun4i-a10-mmc-clk"; 215 reg = <0x01c20088 0x4>; 216 clocks = <&osc24M>, <&pll6 0>; 217 clock-output-names = "mmc0", 218 "mmc0_output", 219 "mmc0_sample"; 220 }; 221 222 mmc1_clk: clk@01c2008c { 223 #clock-cells = <1>; 224 compatible = "allwinner,sun4i-a10-mmc-clk"; 225 reg = <0x01c2008c 0x4>; 226 clocks = <&osc24M>, <&pll6 0>; 227 clock-output-names = "mmc1", 228 "mmc1_output", 229 "mmc1_sample"; 230 }; 231 232 mmc2_clk: clk@01c20090 { 233 #clock-cells = <1>; 234 compatible = "allwinner,sun4i-a10-mmc-clk"; 235 reg = <0x01c20090 0x4>; 236 clocks = <&osc24M>, <&pll6 0>; 237 clock-output-names = "mmc2", 238 "mmc2_output", 239 "mmc2_sample"; 240 }; 241 242 usb_clk: clk@01c200cc { 243 #clock-cells = <1>; 244 #reset-cells = <1>; 245 compatible = "allwinner,sun8i-a23-usb-clk"; 246 reg = <0x01c200cc 0x4>; 247 clocks = <&osc24M>; 248 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", 249 "usb_hsic_12M", "usb_ohci0"; 250 }; 251 }; 252 253 soc@01c00000 { 254 compatible = "simple-bus"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges; 258 259 dma: dma-controller@01c02000 { 260 compatible = "allwinner,sun8i-a23-dma"; 261 reg = <0x01c02000 0x1000>; 262 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&ahb1_gates 6>; 264 resets = <&ahb1_rst 6>; 265 #dma-cells = <1>; 266 }; 267 268 mmc0: mmc@01c0f000 { 269 compatible = "allwinner,sun7i-a20-mmc", 270 "allwinner,sun5i-a13-mmc"; 271 reg = <0x01c0f000 0x1000>; 272 clocks = <&ahb1_gates 8>, 273 <&mmc0_clk 0>, 274 <&mmc0_clk 1>, 275 <&mmc0_clk 2>; 276 clock-names = "ahb", 277 "mmc", 278 "output", 279 "sample"; 280 resets = <&ahb1_rst 8>; 281 reset-names = "ahb"; 282 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 283 status = "disabled"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 }; 287 288 mmc1: mmc@01c10000 { 289 compatible = "allwinner,sun7i-a20-mmc", 290 "allwinner,sun5i-a13-mmc"; 291 reg = <0x01c10000 0x1000>; 292 clocks = <&ahb1_gates 9>, 293 <&mmc1_clk 0>, 294 <&mmc1_clk 1>, 295 <&mmc1_clk 2>; 296 clock-names = "ahb", 297 "mmc", 298 "output", 299 "sample"; 300 resets = <&ahb1_rst 9>; 301 reset-names = "ahb"; 302 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 303 status = "disabled"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 }; 307 308 mmc2: mmc@01c11000 { 309 compatible = "allwinner,sun7i-a20-mmc", 310 "allwinner,sun5i-a13-mmc"; 311 reg = <0x01c11000 0x1000>; 312 clocks = <&ahb1_gates 10>, 313 <&mmc2_clk 0>, 314 <&mmc2_clk 1>, 315 <&mmc2_clk 2>; 316 clock-names = "ahb", 317 "mmc", 318 "output", 319 "sample"; 320 resets = <&ahb1_rst 10>; 321 reset-names = "ahb"; 322 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 328 ehci0: usb@01c1a000 { 329 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 330 reg = <0x01c1a000 0x100>; 331 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ahb1_gates 26>; 333 resets = <&ahb1_rst 26>; 334 phys = <&usbphy 1>; 335 phy-names = "usb"; 336 status = "disabled"; 337 }; 338 339 ohci0: usb@01c1a400 { 340 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 341 reg = <0x01c1a400 0x100>; 342 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 344 resets = <&ahb1_rst 29>; 345 phys = <&usbphy 1>; 346 phy-names = "usb"; 347 status = "disabled"; 348 }; 349 350 pio: pinctrl@01c20800 { 351 /* compatible gets set in SoC specific dtsi file */ 352 reg = <0x01c20800 0x400>; 353 /* interrupts get set in SoC specific dtsi file */ 354 clocks = <&apb1_gates 5>; 355 gpio-controller; 356 interrupt-controller; 357 #interrupt-cells = <3>; 358 #gpio-cells = <3>; 359 360 uart0_pins_a: uart0@0 { 361 allwinner,pins = "PF2", "PF4"; 362 allwinner,function = "uart0"; 363 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 364 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 365 }; 366 367 mmc0_pins_a: mmc0@0 { 368 allwinner,pins = "PF0", "PF1", "PF2", 369 "PF3", "PF4", "PF5"; 370 allwinner,function = "mmc0"; 371 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 372 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 373 }; 374 375 mmc1_pins_a: mmc1@0 { 376 allwinner,pins = "PG0", "PG1", "PG2", 377 "PG3", "PG4", "PG5"; 378 allwinner,function = "mmc1"; 379 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 380 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 381 }; 382 383 mmc2_8bit_pins: mmc2_8bit { 384 allwinner,pins = "PC5", "PC6", "PC8", 385 "PC9", "PC10", "PC11", 386 "PC12", "PC13", "PC14", 387 "PC15", "PC16"; 388 allwinner,function = "mmc2"; 389 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 390 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 391 }; 392 393 pwm0_pins: pwm0 { 394 allwinner,pins = "PH0"; 395 allwinner,function = "pwm0"; 396 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 397 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 398 }; 399 400 i2c0_pins_a: i2c0@0 { 401 allwinner,pins = "PH2", "PH3"; 402 allwinner,function = "i2c0"; 403 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 404 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 405 }; 406 407 i2c1_pins_a: i2c1@0 { 408 allwinner,pins = "PH4", "PH5"; 409 allwinner,function = "i2c1"; 410 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 411 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 412 }; 413 414 i2c2_pins_a: i2c2@0 { 415 allwinner,pins = "PE12", "PE13"; 416 allwinner,function = "i2c2"; 417 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 418 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 419 }; 420 }; 421 422 ahb1_rst: reset@01c202c0 { 423 #reset-cells = <1>; 424 compatible = "allwinner,sun6i-a31-clock-reset"; 425 reg = <0x01c202c0 0xc>; 426 }; 427 428 apb1_rst: reset@01c202d0 { 429 #reset-cells = <1>; 430 compatible = "allwinner,sun6i-a31-clock-reset"; 431 reg = <0x01c202d0 0x4>; 432 }; 433 434 apb2_rst: reset@01c202d8 { 435 #reset-cells = <1>; 436 compatible = "allwinner,sun6i-a31-clock-reset"; 437 reg = <0x01c202d8 0x4>; 438 }; 439 440 timer@01c20c00 { 441 compatible = "allwinner,sun4i-a10-timer"; 442 reg = <0x01c20c00 0xa0>; 443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&osc24M>; 446 }; 447 448 wdt0: watchdog@01c20ca0 { 449 compatible = "allwinner,sun6i-a31-wdt"; 450 reg = <0x01c20ca0 0x20>; 451 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 452 }; 453 454 pwm: pwm@01c21400 { 455 compatible = "allwinner,sun7i-a20-pwm"; 456 reg = <0x01c21400 0xc>; 457 clocks = <&osc24M>; 458 #pwm-cells = <3>; 459 status = "disabled"; 460 }; 461 462 lradc: lradc@01c22800 { 463 compatible = "allwinner,sun4i-a10-lradc-keys"; 464 reg = <0x01c22800 0x100>; 465 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 466 status = "disabled"; 467 }; 468 469 uart0: serial@01c28000 { 470 compatible = "snps,dw-apb-uart"; 471 reg = <0x01c28000 0x400>; 472 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 473 reg-shift = <2>; 474 reg-io-width = <4>; 475 clocks = <&apb2_gates 16>; 476 resets = <&apb2_rst 16>; 477 dmas = <&dma 6>, <&dma 6>; 478 dma-names = "rx", "tx"; 479 status = "disabled"; 480 }; 481 482 uart1: serial@01c28400 { 483 compatible = "snps,dw-apb-uart"; 484 reg = <0x01c28400 0x400>; 485 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 486 reg-shift = <2>; 487 reg-io-width = <4>; 488 clocks = <&apb2_gates 17>; 489 resets = <&apb2_rst 17>; 490 dmas = <&dma 7>, <&dma 7>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 uart2: serial@01c28800 { 496 compatible = "snps,dw-apb-uart"; 497 reg = <0x01c28800 0x400>; 498 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 499 reg-shift = <2>; 500 reg-io-width = <4>; 501 clocks = <&apb2_gates 18>; 502 resets = <&apb2_rst 18>; 503 dmas = <&dma 8>, <&dma 8>; 504 dma-names = "rx", "tx"; 505 status = "disabled"; 506 }; 507 508 uart3: serial@01c28c00 { 509 compatible = "snps,dw-apb-uart"; 510 reg = <0x01c28c00 0x400>; 511 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 512 reg-shift = <2>; 513 reg-io-width = <4>; 514 clocks = <&apb2_gates 19>; 515 resets = <&apb2_rst 19>; 516 dmas = <&dma 9>, <&dma 9>; 517 dma-names = "rx", "tx"; 518 status = "disabled"; 519 }; 520 521 uart4: serial@01c29000 { 522 compatible = "snps,dw-apb-uart"; 523 reg = <0x01c29000 0x400>; 524 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 525 reg-shift = <2>; 526 reg-io-width = <4>; 527 clocks = <&apb2_gates 20>; 528 resets = <&apb2_rst 20>; 529 dmas = <&dma 10>, <&dma 10>; 530 dma-names = "rx", "tx"; 531 status = "disabled"; 532 }; 533 534 i2c0: i2c@01c2ac00 { 535 compatible = "allwinner,sun6i-a31-i2c"; 536 reg = <0x01c2ac00 0x400>; 537 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&apb2_gates 0>; 539 resets = <&apb2_rst 0>; 540 status = "disabled"; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 }; 544 545 i2c1: i2c@01c2b000 { 546 compatible = "allwinner,sun6i-a31-i2c"; 547 reg = <0x01c2b000 0x400>; 548 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&apb2_gates 1>; 550 resets = <&apb2_rst 1>; 551 status = "disabled"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 i2c2: i2c@01c2b400 { 557 compatible = "allwinner,sun6i-a31-i2c"; 558 reg = <0x01c2b400 0x400>; 559 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&apb2_gates 2>; 561 resets = <&apb2_rst 2>; 562 status = "disabled"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 }; 566 567 gic: interrupt-controller@01c81000 { 568 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 569 reg = <0x01c81000 0x1000>, 570 <0x01c82000 0x1000>, 571 <0x01c84000 0x2000>, 572 <0x01c86000 0x2000>; 573 interrupt-controller; 574 #interrupt-cells = <3>; 575 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 576 }; 577 578 rtc: rtc@01f00000 { 579 compatible = "allwinner,sun6i-a31-rtc"; 580 reg = <0x01f00000 0x54>; 581 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 583 }; 584 585 nmi_intc: interrupt-controller@01f00c0c { 586 compatible = "allwinner,sun6i-a31-sc-nmi"; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 reg = <0x01f00c0c 0x38>; 590 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 591 }; 592 593 prcm@01f01400 { 594 compatible = "allwinner,sun8i-a23-prcm"; 595 reg = <0x01f01400 0x200>; 596 597 ar100: ar100_clk { 598 compatible = "fixed-factor-clock"; 599 #clock-cells = <0>; 600 clock-div = <1>; 601 clock-mult = <1>; 602 clocks = <&osc24M>; 603 clock-output-names = "ar100"; 604 }; 605 606 ahb0: ahb0_clk { 607 compatible = "fixed-factor-clock"; 608 #clock-cells = <0>; 609 clock-div = <1>; 610 clock-mult = <1>; 611 clocks = <&ar100>; 612 clock-output-names = "ahb0"; 613 }; 614 615 apb0: apb0_clk { 616 compatible = "allwinner,sun8i-a23-apb0-clk"; 617 #clock-cells = <0>; 618 clocks = <&ahb0>; 619 clock-output-names = "apb0"; 620 }; 621 622 apb0_gates: apb0_gates_clk { 623 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 624 #clock-cells = <1>; 625 clocks = <&apb0>; 626 clock-output-names = "apb0_pio", "apb0_timer", 627 "apb0_rsb", "apb0_uart", 628 "apb0_i2c"; 629 }; 630 631 apb0_rst: apb0_rst { 632 compatible = "allwinner,sun6i-a31-clock-reset"; 633 #reset-cells = <1>; 634 }; 635 }; 636 637 cpucfg@01f01c00 { 638 compatible = "allwinner,sun8i-a23-cpuconfig"; 639 reg = <0x01f01c00 0x300>; 640 }; 641 642 r_uart: serial@01f02800 { 643 compatible = "snps,dw-apb-uart"; 644 reg = <0x01f02800 0x400>; 645 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 646 reg-shift = <2>; 647 reg-io-width = <4>; 648 clocks = <&apb0_gates 4>; 649 resets = <&apb0_rst 4>; 650 status = "disabled"; 651 }; 652 653 r_pio: pinctrl@01f02c00 { 654 compatible = "allwinner,sun8i-a23-r-pinctrl"; 655 reg = <0x01f02c00 0x400>; 656 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&apb0_gates 0>; 658 resets = <&apb0_rst 0>; 659 gpio-controller; 660 interrupt-controller; 661 #interrupt-cells = <3>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 #gpio-cells = <3>; 665 666 r_rsb_pins: r_rsb { 667 allwinner,pins = "PL0", "PL1"; 668 allwinner,function = "s_rsb"; 669 allwinner,drive = <SUN4I_PINCTRL_20_MA>; 670 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 671 }; 672 673 r_uart_pins_a: r_uart@0 { 674 allwinner,pins = "PL2", "PL3"; 675 allwinner,function = "s_uart"; 676 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 677 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 678 }; 679 }; 680 681 r_rsb: rsb@01f03400 { 682 compatible = "allwinner,sun8i-a23-rsb"; 683 reg = <0x01f03400 0x400>; 684 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&apb0_gates 3>; 686 clock-frequency = <3000000>; 687 resets = <&apb0_rst 3>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&r_rsb_pins>; 690 status = "disabled"; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 }; 694 }; 695}; 696