1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48 49#include <dt-bindings/pinctrl/sun4i-a10.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 54 chosen { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges; 58 59 framebuffer@0 { 60 compatible = "allwinner,simple-framebuffer", 61 "simple-framebuffer"; 62 allwinner,pipeline = "de_be0-lcd0"; 63 clocks = <&pll6 0>; 64 status = "disabled"; 65 }; 66 }; 67 68 timer { 69 compatible = "arm,armv7-timer"; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 74 clock-frequency = <24000000>; 75 arm,cpu-registers-not-fw-configured; 76 }; 77 78 cpus { 79 enable-method = "allwinner,sun8i-a23"; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 cpu@0 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0>; 87 }; 88 89 cpu@1 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <1>; 93 }; 94 }; 95 96 clocks { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges; 100 101 osc24M: osc24M_clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 clock-frequency = <24000000>; 105 clock-output-names = "osc24M"; 106 }; 107 108 osc32k: osc32k_clk { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 clock-frequency = <32768>; 112 clock-output-names = "osc32k"; 113 }; 114 115 pll1: clk@01c20000 { 116 #clock-cells = <0>; 117 compatible = "allwinner,sun8i-a23-pll1-clk"; 118 reg = <0x01c20000 0x4>; 119 clocks = <&osc24M>; 120 clock-output-names = "pll1"; 121 }; 122 123 /* dummy clock until actually implemented */ 124 pll5: pll5_clk { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <0>; 128 clock-output-names = "pll5"; 129 }; 130 131 pll6: clk@01c20028 { 132 #clock-cells = <1>; 133 compatible = "allwinner,sun6i-a31-pll6-clk"; 134 reg = <0x01c20028 0x4>; 135 clocks = <&osc24M>; 136 clock-output-names = "pll6", "pll6x2"; 137 }; 138 139 cpu: cpu_clk@01c20050 { 140 #clock-cells = <0>; 141 compatible = "allwinner,sun4i-a10-cpu-clk"; 142 reg = <0x01c20050 0x4>; 143 144 /* 145 * PLL1 is listed twice here. 146 * While it looks suspicious, it's actually documented 147 * that way both in the datasheet and in the code from 148 * Allwinner. 149 */ 150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 151 clock-output-names = "cpu"; 152 }; 153 154 axi: axi_clk@01c20050 { 155 #clock-cells = <0>; 156 compatible = "allwinner,sun8i-a23-axi-clk"; 157 reg = <0x01c20050 0x4>; 158 clocks = <&cpu>; 159 clock-output-names = "axi"; 160 }; 161 162 ahb1: ahb1_clk@01c20054 { 163 #clock-cells = <0>; 164 compatible = "allwinner,sun6i-a31-ahb1-clk"; 165 reg = <0x01c20054 0x4>; 166 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 167 clock-output-names = "ahb1"; 168 }; 169 170 apb1: apb1_clk@01c20054 { 171 #clock-cells = <0>; 172 compatible = "allwinner,sun4i-a10-apb0-clk"; 173 reg = <0x01c20054 0x4>; 174 clocks = <&ahb1>; 175 clock-output-names = "apb1"; 176 }; 177 178 ahb1_gates: clk@01c20060 { 179 #clock-cells = <1>; 180 compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; 181 reg = <0x01c20060 0x8>; 182 clocks = <&ahb1>; 183 clock-output-names = "ahb1_mipidsi", "ahb1_dma", 184 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", 185 "ahb1_nand", "ahb1_sdram", 186 "ahb1_hstimer", "ahb1_spi0", 187 "ahb1_spi1", "ahb1_otg", "ahb1_ehci", 188 "ahb1_ohci", "ahb1_ve", "ahb1_lcd", 189 "ahb1_csi", "ahb1_be", "ahb1_fe", 190 "ahb1_gpu", "ahb1_spinlock", 191 "ahb1_drc"; 192 }; 193 194 apb1_gates: clk@01c20068 { 195 #clock-cells = <1>; 196 compatible = "allwinner,sun8i-a23-apb1-gates-clk"; 197 reg = <0x01c20068 0x4>; 198 clocks = <&apb1>; 199 clock-output-names = "apb1_codec", "apb1_pio", 200 "apb1_daudio0", "apb1_daudio1"; 201 }; 202 203 apb2: clk@01c20058 { 204 #clock-cells = <0>; 205 compatible = "allwinner,sun4i-a10-apb1-clk"; 206 reg = <0x01c20058 0x4>; 207 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 208 clock-output-names = "apb2"; 209 }; 210 211 apb2_gates: clk@01c2006c { 212 #clock-cells = <1>; 213 compatible = "allwinner,sun8i-a23-apb2-gates-clk"; 214 reg = <0x01c2006c 0x4>; 215 clocks = <&apb2>; 216 clock-output-names = "apb2_i2c0", "apb2_i2c1", 217 "apb2_i2c2", "apb2_uart0", 218 "apb2_uart1", "apb2_uart2", 219 "apb2_uart3", "apb2_uart4"; 220 }; 221 222 mmc0_clk: clk@01c20088 { 223 #clock-cells = <1>; 224 compatible = "allwinner,sun4i-a10-mmc-clk"; 225 reg = <0x01c20088 0x4>; 226 clocks = <&osc24M>, <&pll6 0>; 227 clock-output-names = "mmc0", 228 "mmc0_output", 229 "mmc0_sample"; 230 }; 231 232 mmc1_clk: clk@01c2008c { 233 #clock-cells = <1>; 234 compatible = "allwinner,sun4i-a10-mmc-clk"; 235 reg = <0x01c2008c 0x4>; 236 clocks = <&osc24M>, <&pll6 0>; 237 clock-output-names = "mmc1", 238 "mmc1_output", 239 "mmc1_sample"; 240 }; 241 242 mmc2_clk: clk@01c20090 { 243 #clock-cells = <1>; 244 compatible = "allwinner,sun4i-a10-mmc-clk"; 245 reg = <0x01c20090 0x4>; 246 clocks = <&osc24M>, <&pll6 0>; 247 clock-output-names = "mmc2", 248 "mmc2_output", 249 "mmc2_sample"; 250 }; 251 252 usb_clk: clk@01c200cc { 253 #clock-cells = <1>; 254 #reset-cells = <1>; 255 compatible = "allwinner,sun8i-a23-usb-clk"; 256 reg = <0x01c200cc 0x4>; 257 clocks = <&osc24M>; 258 clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", 259 "usb_hsic_12M", "usb_ohci0"; 260 }; 261 }; 262 263 soc@01c00000 { 264 compatible = "simple-bus"; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 269 dma: dma-controller@01c02000 { 270 compatible = "allwinner,sun8i-a23-dma"; 271 reg = <0x01c02000 0x1000>; 272 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&ahb1_gates 6>; 274 resets = <&ahb1_rst 6>; 275 #dma-cells = <1>; 276 }; 277 278 mmc0: mmc@01c0f000 { 279 compatible = "allwinner,sun5i-a13-mmc"; 280 reg = <0x01c0f000 0x1000>; 281 clocks = <&ahb1_gates 8>, 282 <&mmc0_clk 0>, 283 <&mmc0_clk 1>, 284 <&mmc0_clk 2>; 285 clock-names = "ahb", 286 "mmc", 287 "output", 288 "sample"; 289 resets = <&ahb1_rst 8>; 290 reset-names = "ahb"; 291 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 292 status = "disabled"; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 }; 296 297 mmc1: mmc@01c10000 { 298 compatible = "allwinner,sun5i-a13-mmc"; 299 reg = <0x01c10000 0x1000>; 300 clocks = <&ahb1_gates 9>, 301 <&mmc1_clk 0>, 302 <&mmc1_clk 1>, 303 <&mmc1_clk 2>; 304 clock-names = "ahb", 305 "mmc", 306 "output", 307 "sample"; 308 resets = <&ahb1_rst 9>; 309 reset-names = "ahb"; 310 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 311 status = "disabled"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 316 mmc2: mmc@01c11000 { 317 compatible = "allwinner,sun5i-a13-mmc"; 318 reg = <0x01c11000 0x1000>; 319 clocks = <&ahb1_gates 10>, 320 <&mmc2_clk 0>, 321 <&mmc2_clk 1>, 322 <&mmc2_clk 2>; 323 clock-names = "ahb", 324 "mmc", 325 "output", 326 "sample"; 327 resets = <&ahb1_rst 10>; 328 reset-names = "ahb"; 329 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 330 status = "disabled"; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 }; 334 335 ehci0: usb@01c1a000 { 336 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 337 reg = <0x01c1a000 0x100>; 338 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&ahb1_gates 26>; 340 resets = <&ahb1_rst 26>; 341 phys = <&usbphy 1>; 342 phy-names = "usb"; 343 status = "disabled"; 344 }; 345 346 ohci0: usb@01c1a400 { 347 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 348 reg = <0x01c1a400 0x100>; 349 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 351 resets = <&ahb1_rst 29>; 352 phys = <&usbphy 1>; 353 phy-names = "usb"; 354 status = "disabled"; 355 }; 356 357 pio: pinctrl@01c20800 { 358 /* compatible gets set in SoC specific dtsi file */ 359 reg = <0x01c20800 0x400>; 360 /* interrupts get set in SoC specific dtsi file */ 361 clocks = <&apb1_gates 5>; 362 gpio-controller; 363 interrupt-controller; 364 #interrupt-cells = <3>; 365 #gpio-cells = <3>; 366 367 uart0_pins_a: uart0@0 { 368 allwinner,pins = "PF2", "PF4"; 369 allwinner,function = "uart0"; 370 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 371 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 372 }; 373 374 mmc0_pins_a: mmc0@0 { 375 allwinner,pins = "PF0", "PF1", "PF2", 376 "PF3", "PF4", "PF5"; 377 allwinner,function = "mmc0"; 378 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 379 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 380 }; 381 382 mmc1_pins_a: mmc1@0 { 383 allwinner,pins = "PG0", "PG1", "PG2", 384 "PG3", "PG4", "PG5"; 385 allwinner,function = "mmc1"; 386 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 387 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 388 }; 389 390 mmc2_8bit_pins: mmc2_8bit { 391 allwinner,pins = "PC5", "PC6", "PC8", 392 "PC9", "PC10", "PC11", 393 "PC12", "PC13", "PC14", 394 "PC15"; 395 allwinner,function = "mmc2"; 396 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 397 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 398 }; 399 400 i2c0_pins_a: i2c0@0 { 401 allwinner,pins = "PH2", "PH3"; 402 allwinner,function = "i2c0"; 403 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 404 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 405 }; 406 407 i2c1_pins_a: i2c1@0 { 408 allwinner,pins = "PH4", "PH5"; 409 allwinner,function = "i2c1"; 410 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 411 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 412 }; 413 414 i2c2_pins_a: i2c2@0 { 415 allwinner,pins = "PE12", "PE13"; 416 allwinner,function = "i2c2"; 417 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 418 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 419 }; 420 }; 421 422 ahb1_rst: reset@01c202c0 { 423 #reset-cells = <1>; 424 compatible = "allwinner,sun6i-a31-clock-reset"; 425 reg = <0x01c202c0 0xc>; 426 }; 427 428 apb1_rst: reset@01c202d0 { 429 #reset-cells = <1>; 430 compatible = "allwinner,sun6i-a31-clock-reset"; 431 reg = <0x01c202d0 0x4>; 432 }; 433 434 apb2_rst: reset@01c202d8 { 435 #reset-cells = <1>; 436 compatible = "allwinner,sun6i-a31-clock-reset"; 437 reg = <0x01c202d8 0x4>; 438 }; 439 440 timer@01c20c00 { 441 compatible = "allwinner,sun4i-a10-timer"; 442 reg = <0x01c20c00 0xa0>; 443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&osc24M>; 446 }; 447 448 wdt0: watchdog@01c20ca0 { 449 compatible = "allwinner,sun6i-a31-wdt"; 450 reg = <0x01c20ca0 0x20>; 451 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 452 }; 453 454 lradc: lradc@01c22800 { 455 compatible = "allwinner,sun4i-a10-lradc-keys"; 456 reg = <0x01c22800 0x100>; 457 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 458 status = "disabled"; 459 }; 460 461 uart0: serial@01c28000 { 462 compatible = "snps,dw-apb-uart"; 463 reg = <0x01c28000 0x400>; 464 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 clocks = <&apb2_gates 16>; 468 resets = <&apb2_rst 16>; 469 dmas = <&dma 6>, <&dma 6>; 470 dma-names = "rx", "tx"; 471 status = "disabled"; 472 }; 473 474 uart1: serial@01c28400 { 475 compatible = "snps,dw-apb-uart"; 476 reg = <0x01c28400 0x400>; 477 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 478 reg-shift = <2>; 479 reg-io-width = <4>; 480 clocks = <&apb2_gates 17>; 481 resets = <&apb2_rst 17>; 482 dmas = <&dma 7>, <&dma 7>; 483 dma-names = "rx", "tx"; 484 status = "disabled"; 485 }; 486 487 uart2: serial@01c28800 { 488 compatible = "snps,dw-apb-uart"; 489 reg = <0x01c28800 0x400>; 490 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 491 reg-shift = <2>; 492 reg-io-width = <4>; 493 clocks = <&apb2_gates 18>; 494 resets = <&apb2_rst 18>; 495 dmas = <&dma 8>, <&dma 8>; 496 dma-names = "rx", "tx"; 497 status = "disabled"; 498 }; 499 500 uart3: serial@01c28c00 { 501 compatible = "snps,dw-apb-uart"; 502 reg = <0x01c28c00 0x400>; 503 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 504 reg-shift = <2>; 505 reg-io-width = <4>; 506 clocks = <&apb2_gates 19>; 507 resets = <&apb2_rst 19>; 508 dmas = <&dma 9>, <&dma 9>; 509 dma-names = "rx", "tx"; 510 status = "disabled"; 511 }; 512 513 uart4: serial@01c29000 { 514 compatible = "snps,dw-apb-uart"; 515 reg = <0x01c29000 0x400>; 516 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 517 reg-shift = <2>; 518 reg-io-width = <4>; 519 clocks = <&apb2_gates 20>; 520 resets = <&apb2_rst 20>; 521 dmas = <&dma 10>, <&dma 10>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 i2c0: i2c@01c2ac00 { 527 compatible = "allwinner,sun6i-a31-i2c"; 528 reg = <0x01c2ac00 0x400>; 529 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&apb2_gates 0>; 531 resets = <&apb2_rst 0>; 532 status = "disabled"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 }; 536 537 i2c1: i2c@01c2b000 { 538 compatible = "allwinner,sun6i-a31-i2c"; 539 reg = <0x01c2b000 0x400>; 540 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&apb2_gates 1>; 542 resets = <&apb2_rst 1>; 543 status = "disabled"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 }; 547 548 i2c2: i2c@01c2b400 { 549 compatible = "allwinner,sun6i-a31-i2c"; 550 reg = <0x01c2b400 0x400>; 551 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&apb2_gates 2>; 553 resets = <&apb2_rst 2>; 554 status = "disabled"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 559 gic: interrupt-controller@01c81000 { 560 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 561 reg = <0x01c81000 0x1000>, 562 <0x01c82000 0x1000>, 563 <0x01c84000 0x2000>, 564 <0x01c86000 0x2000>; 565 interrupt-controller; 566 #interrupt-cells = <3>; 567 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 568 }; 569 570 rtc: rtc@01f00000 { 571 compatible = "allwinner,sun6i-a31-rtc"; 572 reg = <0x01f00000 0x54>; 573 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 575 }; 576 577 prcm@01f01400 { 578 compatible = "allwinner,sun8i-a23-prcm"; 579 reg = <0x01f01400 0x200>; 580 581 ar100: ar100_clk { 582 compatible = "fixed-factor-clock"; 583 #clock-cells = <0>; 584 clock-div = <1>; 585 clock-mult = <1>; 586 clocks = <&osc24M>; 587 clock-output-names = "ar100"; 588 }; 589 590 ahb0: ahb0_clk { 591 compatible = "fixed-factor-clock"; 592 #clock-cells = <0>; 593 clock-div = <1>; 594 clock-mult = <1>; 595 clocks = <&ar100>; 596 clock-output-names = "ahb0"; 597 }; 598 599 apb0: apb0_clk { 600 compatible = "allwinner,sun8i-a23-apb0-clk"; 601 #clock-cells = <0>; 602 clocks = <&ahb0>; 603 clock-output-names = "apb0"; 604 }; 605 606 apb0_gates: apb0_gates_clk { 607 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 608 #clock-cells = <1>; 609 clocks = <&apb0>; 610 clock-output-names = "apb0_pio", "apb0_timer", 611 "apb0_rsb", "apb0_uart", 612 "apb0_i2c"; 613 }; 614 615 apb0_rst: apb0_rst { 616 compatible = "allwinner,sun6i-a31-clock-reset"; 617 #reset-cells = <1>; 618 }; 619 }; 620 621 cpucfg@01f01c00 { 622 compatible = "allwinner,sun8i-a23-cpuconfig"; 623 reg = <0x01f01c00 0x300>; 624 }; 625 626 r_uart: serial@01f02800 { 627 compatible = "snps,dw-apb-uart"; 628 reg = <0x01f02800 0x400>; 629 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 630 reg-shift = <2>; 631 reg-io-width = <4>; 632 clocks = <&apb0_gates 4>; 633 resets = <&apb0_rst 4>; 634 status = "disabled"; 635 }; 636 637 r_pio: pinctrl@01f02c00 { 638 compatible = "allwinner,sun8i-a23-r-pinctrl"; 639 reg = <0x01f02c00 0x400>; 640 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&apb0_gates 0>; 642 resets = <&apb0_rst 0>; 643 gpio-controller; 644 interrupt-controller; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 #gpio-cells = <3>; 648 649 r_uart_pins_a: r_uart@0 { 650 allwinner,pins = "PL2", "PL3"; 651 allwinner,function = "s_uart"; 652 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 653 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 654 }; 655 }; 656 }; 657}; 658