1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/thermal/thermal.h> 49 50#include <dt-bindings/clock/sun4i-a10-pll2.h> 51#include <dt-bindings/dma/sun4i-a10.h> 52#include <dt-bindings/pinctrl/sun4i-a10.h> 53 54/ { 55 interrupt-parent = <&gic>; 56 57 aliases { 58 ethernet0 = &gmac; 59 }; 60 61 chosen { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges; 65 66 framebuffer@0 { 67 compatible = "allwinner,simple-framebuffer", 68 "simple-framebuffer"; 69 allwinner,pipeline = "de_be0-lcd0-hdmi"; 70 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 71 <&ahb_gates 44>, <&dram_gates 26>; 72 status = "disabled"; 73 }; 74 75 framebuffer@1 { 76 compatible = "allwinner,simple-framebuffer", 77 "simple-framebuffer"; 78 allwinner,pipeline = "de_be0-lcd0"; 79 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, 80 <&dram_gates 26>; 81 status = "disabled"; 82 }; 83 84 framebuffer@2 { 85 compatible = "allwinner,simple-framebuffer", 86 "simple-framebuffer"; 87 allwinner,pipeline = "de_be0-lcd0-tve0"; 88 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, 89 <&ahb_gates 44>, <&dram_gates 26>; 90 status = "disabled"; 91 }; 92 }; 93 94 cpus { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 cpu0: cpu@0 { 99 compatible = "arm,cortex-a7"; 100 device_type = "cpu"; 101 reg = <0>; 102 clocks = <&cpu>; 103 clock-latency = <244144>; /* 8 32k periods */ 104 operating-points = < 105 /* kHz uV */ 106 960000 1400000 107 912000 1400000 108 864000 1300000 109 720000 1200000 110 528000 1100000 111 312000 1000000 112 144000 1000000 113 >; 114 #cooling-cells = <2>; 115 cooling-min-level = <0>; 116 cooling-max-level = <6>; 117 }; 118 119 cpu@1 { 120 compatible = "arm,cortex-a7"; 121 device_type = "cpu"; 122 reg = <1>; 123 }; 124 }; 125 126 thermal-zones { 127 cpu_thermal { 128 /* milliseconds */ 129 polling-delay-passive = <250>; 130 polling-delay = <1000>; 131 thermal-sensors = <&rtp>; 132 133 cooling-maps { 134 map0 { 135 trip = <&cpu_alert0>; 136 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 137 }; 138 }; 139 140 trips { 141 cpu_alert0: cpu_alert0 { 142 /* milliCelsius */ 143 temperature = <75000>; 144 hysteresis = <2000>; 145 type = "passive"; 146 }; 147 148 cpu_crit: cpu_crit { 149 /* milliCelsius */ 150 temperature = <100000>; 151 hysteresis = <2000>; 152 type = "critical"; 153 }; 154 }; 155 }; 156 }; 157 158 memory { 159 reg = <0x40000000 0x80000000>; 160 }; 161 162 timer { 163 compatible = "arm,armv7-timer"; 164 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 165 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 168 }; 169 170 pmu { 171 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 172 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 clocks { 177 #address-cells = <1>; 178 #size-cells = <1>; 179 ranges; 180 181 osc24M: clk@01c20050 { 182 #clock-cells = <0>; 183 compatible = "allwinner,sun4i-a10-osc-clk"; 184 reg = <0x01c20050 0x4>; 185 clock-frequency = <24000000>; 186 clock-output-names = "osc24M"; 187 }; 188 189 osc32k: clk@0 { 190 #clock-cells = <0>; 191 compatible = "fixed-clock"; 192 clock-frequency = <32768>; 193 clock-output-names = "osc32k"; 194 }; 195 196 pll1: clk@01c20000 { 197 #clock-cells = <0>; 198 compatible = "allwinner,sun4i-a10-pll1-clk"; 199 reg = <0x01c20000 0x4>; 200 clocks = <&osc24M>; 201 clock-output-names = "pll1"; 202 }; 203 204 pll2: clk@01c20008 { 205 #clock-cells = <1>; 206 compatible = "allwinner,sun4i-a10-pll2-clk"; 207 reg = <0x01c20008 0x8>; 208 clocks = <&osc24M>; 209 clock-output-names = "pll2-1x", "pll2-2x", 210 "pll2-4x", "pll2-8x"; 211 }; 212 213 pll4: clk@01c20018 { 214 #clock-cells = <0>; 215 compatible = "allwinner,sun7i-a20-pll4-clk"; 216 reg = <0x01c20018 0x4>; 217 clocks = <&osc24M>; 218 clock-output-names = "pll4"; 219 }; 220 221 pll5: clk@01c20020 { 222 #clock-cells = <1>; 223 compatible = "allwinner,sun4i-a10-pll5-clk"; 224 reg = <0x01c20020 0x4>; 225 clocks = <&osc24M>; 226 clock-output-names = "pll5_ddr", "pll5_other"; 227 }; 228 229 pll6: clk@01c20028 { 230 #clock-cells = <1>; 231 compatible = "allwinner,sun4i-a10-pll6-clk"; 232 reg = <0x01c20028 0x4>; 233 clocks = <&osc24M>; 234 clock-output-names = "pll6_sata", "pll6_other", "pll6", 235 "pll6_div_4"; 236 }; 237 238 pll8: clk@01c20040 { 239 #clock-cells = <0>; 240 compatible = "allwinner,sun7i-a20-pll4-clk"; 241 reg = <0x01c20040 0x4>; 242 clocks = <&osc24M>; 243 clock-output-names = "pll8"; 244 }; 245 246 cpu: cpu@01c20054 { 247 #clock-cells = <0>; 248 compatible = "allwinner,sun4i-a10-cpu-clk"; 249 reg = <0x01c20054 0x4>; 250 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 251 clock-output-names = "cpu"; 252 }; 253 254 axi: axi@01c20054 { 255 #clock-cells = <0>; 256 compatible = "allwinner,sun4i-a10-axi-clk"; 257 reg = <0x01c20054 0x4>; 258 clocks = <&cpu>; 259 clock-output-names = "axi"; 260 }; 261 262 ahb: ahb@01c20054 { 263 #clock-cells = <0>; 264 compatible = "allwinner,sun5i-a13-ahb-clk"; 265 reg = <0x01c20054 0x4>; 266 clocks = <&axi>, <&pll6 3>, <&pll6 1>; 267 clock-output-names = "ahb"; 268 /* 269 * Use PLL6 as parent, instead of CPU/AXI 270 * which has rate changes due to cpufreq 271 */ 272 assigned-clocks = <&ahb>; 273 assigned-clock-parents = <&pll6 3>; 274 }; 275 276 ahb_gates: clk@01c20060 { 277 #clock-cells = <1>; 278 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 279 reg = <0x01c20060 0x8>; 280 clocks = <&ahb>; 281 clock-indices = <0>, <1>, 282 <2>, <3>, <4>, 283 <5>, <6>, <7>, <8>, 284 <9>, <10>, <11>, <12>, 285 <13>, <14>, <16>, 286 <17>, <18>, <20>, <21>, 287 <22>, <23>, <25>, 288 <28>, <32>, <33>, <34>, 289 <35>, <36>, <37>, <40>, 290 <41>, <42>, <43>, 291 <44>, <45>, <46>, 292 <47>, <49>, <50>, 293 <52>; 294 clock-output-names = "ahb_usb0", "ahb_ehci0", 295 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", 296 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", 297 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", 298 "ahb_nand", "ahb_sdram", "ahb_ace", 299 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", 300 "ahb_spi2", "ahb_spi3", "ahb_sata", 301 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", 302 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", 303 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", 304 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", 305 "ahb_de_fe1", "ahb_gmac", "ahb_mp", 306 "ahb_mali"; 307 }; 308 309 apb0: apb0@01c20054 { 310 #clock-cells = <0>; 311 compatible = "allwinner,sun4i-a10-apb0-clk"; 312 reg = <0x01c20054 0x4>; 313 clocks = <&ahb>; 314 clock-output-names = "apb0"; 315 }; 316 317 apb0_gates: clk@01c20068 { 318 #clock-cells = <1>; 319 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 320 reg = <0x01c20068 0x4>; 321 clocks = <&apb0>; 322 clock-indices = <0>, <1>, 323 <2>, <3>, <4>, 324 <5>, <6>, <7>, 325 <8>, <10>; 326 clock-output-names = "apb0_codec", "apb0_spdif", 327 "apb0_ac97", "apb0_iis0", "apb0_iis1", 328 "apb0_pio", "apb0_ir0", "apb0_ir1", 329 "apb0_iis2", "apb0_keypad"; 330 }; 331 332 apb1: clk@01c20058 { 333 #clock-cells = <0>; 334 compatible = "allwinner,sun4i-a10-apb1-clk"; 335 reg = <0x01c20058 0x4>; 336 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 337 clock-output-names = "apb1"; 338 }; 339 340 apb1_gates: clk@01c2006c { 341 #clock-cells = <1>; 342 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 343 reg = <0x01c2006c 0x4>; 344 clocks = <&apb1>; 345 clock-indices = <0>, <1>, 346 <2>, <3>, <4>, 347 <5>, <6>, <7>, 348 <15>, <16>, <17>, 349 <18>, <19>, <20>, 350 <21>, <22>, <23>; 351 clock-output-names = "apb1_i2c0", "apb1_i2c1", 352 "apb1_i2c2", "apb1_i2c3", "apb1_can", 353 "apb1_scr", "apb1_ps20", "apb1_ps21", 354 "apb1_i2c4", "apb1_uart0", "apb1_uart1", 355 "apb1_uart2", "apb1_uart3", "apb1_uart4", 356 "apb1_uart5", "apb1_uart6", "apb1_uart7"; 357 }; 358 359 nand_clk: clk@01c20080 { 360 #clock-cells = <0>; 361 compatible = "allwinner,sun4i-a10-mod0-clk"; 362 reg = <0x01c20080 0x4>; 363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 364 clock-output-names = "nand"; 365 }; 366 367 ms_clk: clk@01c20084 { 368 #clock-cells = <0>; 369 compatible = "allwinner,sun4i-a10-mod0-clk"; 370 reg = <0x01c20084 0x4>; 371 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 372 clock-output-names = "ms"; 373 }; 374 375 mmc0_clk: clk@01c20088 { 376 #clock-cells = <1>; 377 compatible = "allwinner,sun4i-a10-mmc-clk"; 378 reg = <0x01c20088 0x4>; 379 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 380 clock-output-names = "mmc0", 381 "mmc0_output", 382 "mmc0_sample"; 383 }; 384 385 mmc1_clk: clk@01c2008c { 386 #clock-cells = <1>; 387 compatible = "allwinner,sun4i-a10-mmc-clk"; 388 reg = <0x01c2008c 0x4>; 389 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 390 clock-output-names = "mmc1", 391 "mmc1_output", 392 "mmc1_sample"; 393 }; 394 395 mmc2_clk: clk@01c20090 { 396 #clock-cells = <1>; 397 compatible = "allwinner,sun4i-a10-mmc-clk"; 398 reg = <0x01c20090 0x4>; 399 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 400 clock-output-names = "mmc2", 401 "mmc2_output", 402 "mmc2_sample"; 403 }; 404 405 mmc3_clk: clk@01c20094 { 406 #clock-cells = <1>; 407 compatible = "allwinner,sun4i-a10-mmc-clk"; 408 reg = <0x01c20094 0x4>; 409 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 410 clock-output-names = "mmc3", 411 "mmc3_output", 412 "mmc3_sample"; 413 }; 414 415 ts_clk: clk@01c20098 { 416 #clock-cells = <0>; 417 compatible = "allwinner,sun4i-a10-mod0-clk"; 418 reg = <0x01c20098 0x4>; 419 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 420 clock-output-names = "ts"; 421 }; 422 423 ss_clk: clk@01c2009c { 424 #clock-cells = <0>; 425 compatible = "allwinner,sun4i-a10-mod0-clk"; 426 reg = <0x01c2009c 0x4>; 427 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 428 clock-output-names = "ss"; 429 }; 430 431 spi0_clk: clk@01c200a0 { 432 #clock-cells = <0>; 433 compatible = "allwinner,sun4i-a10-mod0-clk"; 434 reg = <0x01c200a0 0x4>; 435 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 436 clock-output-names = "spi0"; 437 }; 438 439 spi1_clk: clk@01c200a4 { 440 #clock-cells = <0>; 441 compatible = "allwinner,sun4i-a10-mod0-clk"; 442 reg = <0x01c200a4 0x4>; 443 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 444 clock-output-names = "spi1"; 445 }; 446 447 spi2_clk: clk@01c200a8 { 448 #clock-cells = <0>; 449 compatible = "allwinner,sun4i-a10-mod0-clk"; 450 reg = <0x01c200a8 0x4>; 451 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 452 clock-output-names = "spi2"; 453 }; 454 455 pata_clk: clk@01c200ac { 456 #clock-cells = <0>; 457 compatible = "allwinner,sun4i-a10-mod0-clk"; 458 reg = <0x01c200ac 0x4>; 459 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 460 clock-output-names = "pata"; 461 }; 462 463 ir0_clk: clk@01c200b0 { 464 #clock-cells = <0>; 465 compatible = "allwinner,sun4i-a10-mod0-clk"; 466 reg = <0x01c200b0 0x4>; 467 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 468 clock-output-names = "ir0"; 469 }; 470 471 ir1_clk: clk@01c200b4 { 472 #clock-cells = <0>; 473 compatible = "allwinner,sun4i-a10-mod0-clk"; 474 reg = <0x01c200b4 0x4>; 475 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 476 clock-output-names = "ir1"; 477 }; 478 479 keypad_clk: clk@01c200c4 { 480 #clock-cells = <0>; 481 compatible = "allwinner,sun4i-a10-mod0-clk"; 482 reg = <0x01c200c4 0x4>; 483 clocks = <&osc24M>; 484 clock-output-names = "keypad"; 485 }; 486 487 usb_clk: clk@01c200cc { 488 #clock-cells = <1>; 489 #reset-cells = <1>; 490 compatible = "allwinner,sun4i-a10-usb-clk"; 491 reg = <0x01c200cc 0x4>; 492 clocks = <&pll6 1>; 493 clock-output-names = "usb_ohci0", "usb_ohci1", 494 "usb_phy"; 495 }; 496 497 spi3_clk: clk@01c200d4 { 498 #clock-cells = <0>; 499 compatible = "allwinner,sun4i-a10-mod0-clk"; 500 reg = <0x01c200d4 0x4>; 501 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 502 clock-output-names = "spi3"; 503 }; 504 505 dram_gates: clk@01c20100 { 506 #clock-cells = <1>; 507 compatible = "allwinner,sun4i-a10-dram-gates-clk"; 508 reg = <0x01c20100 0x4>; 509 clocks = <&pll5 0>; 510 clock-indices = <0>, 511 <1>, <2>, 512 <3>, 513 <4>, 514 <5>, <6>, 515 <15>, 516 <24>, <25>, 517 <26>, <27>, 518 <28>, <29>; 519 clock-output-names = "dram_ve", 520 "dram_csi0", "dram_csi1", 521 "dram_ts", 522 "dram_tvd", 523 "dram_tve0", "dram_tve1", 524 "dram_output", 525 "dram_de_fe1", "dram_de_fe0", 526 "dram_de_be0", "dram_de_be1", 527 "dram_de_mp", "dram_ace"; 528 }; 529 530 ve_clk: clk@01c2013c { 531 #clock-cells = <0>; 532 #reset-cells = <0>; 533 compatible = "allwinner,sun4i-a10-ve-clk"; 534 reg = <0x01c2013c 0x4>; 535 clocks = <&pll4>; 536 clock-output-names = "ve"; 537 }; 538 539 codec_clk: clk@01c20140 { 540 #clock-cells = <0>; 541 compatible = "allwinner,sun4i-a10-codec-clk"; 542 reg = <0x01c20140 0x4>; 543 clocks = <&pll2 SUN4I_A10_PLL2_1X>; 544 clock-output-names = "codec"; 545 }; 546 547 mbus_clk: clk@01c2015c { 548 #clock-cells = <0>; 549 compatible = "allwinner,sun5i-a13-mbus-clk"; 550 reg = <0x01c2015c 0x4>; 551 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 552 clock-output-names = "mbus"; 553 }; 554 555 /* 556 * The following two are dummy clocks, placeholders 557 * used in the gmac_tx clock. The gmac driver will 558 * choose one parent depending on the PHY interface 559 * mode, using clk_set_rate auto-reparenting. 560 * 561 * The actual TX clock rate is not controlled by the 562 * gmac_tx clock. 563 */ 564 mii_phy_tx_clk: clk@2 { 565 #clock-cells = <0>; 566 compatible = "fixed-clock"; 567 clock-frequency = <25000000>; 568 clock-output-names = "mii_phy_tx"; 569 }; 570 571 gmac_int_tx_clk: clk@3 { 572 #clock-cells = <0>; 573 compatible = "fixed-clock"; 574 clock-frequency = <125000000>; 575 clock-output-names = "gmac_int_tx"; 576 }; 577 578 gmac_tx_clk: clk@01c20164 { 579 #clock-cells = <0>; 580 compatible = "allwinner,sun7i-a20-gmac-clk"; 581 reg = <0x01c20164 0x4>; 582 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 583 clock-output-names = "gmac_tx"; 584 }; 585 586 /* 587 * Dummy clock used by output clocks 588 */ 589 osc24M_32k: clk@1 { 590 #clock-cells = <0>; 591 compatible = "fixed-factor-clock"; 592 clock-div = <750>; 593 clock-mult = <1>; 594 clocks = <&osc24M>; 595 clock-output-names = "osc24M_32k"; 596 }; 597 598 clk_out_a: clk@01c201f0 { 599 #clock-cells = <0>; 600 compatible = "allwinner,sun7i-a20-out-clk"; 601 reg = <0x01c201f0 0x4>; 602 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 603 clock-output-names = "clk_out_a"; 604 }; 605 606 clk_out_b: clk@01c201f4 { 607 #clock-cells = <0>; 608 compatible = "allwinner,sun7i-a20-out-clk"; 609 reg = <0x01c201f4 0x4>; 610 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 611 clock-output-names = "clk_out_b"; 612 }; 613 }; 614 615 soc@01c00000 { 616 compatible = "simple-bus"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges; 620 621 sram-controller@01c00000 { 622 compatible = "allwinner,sun4i-a10-sram-controller"; 623 reg = <0x01c00000 0x30>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges; 627 628 sram_a: sram@00000000 { 629 compatible = "mmio-sram"; 630 reg = <0x00000000 0xc000>; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges = <0 0x00000000 0xc000>; 634 635 emac_sram: sram-section@8000 { 636 compatible = "allwinner,sun4i-a10-sram-a3-a4"; 637 reg = <0x8000 0x4000>; 638 status = "disabled"; 639 }; 640 }; 641 642 sram_d: sram@00010000 { 643 compatible = "mmio-sram"; 644 reg = <0x00010000 0x1000>; 645 #address-cells = <1>; 646 #size-cells = <1>; 647 ranges = <0 0x00010000 0x1000>; 648 649 otg_sram: sram-section@0000 { 650 compatible = "allwinner,sun4i-a10-sram-d"; 651 reg = <0x0000 0x1000>; 652 status = "disabled"; 653 }; 654 }; 655 }; 656 657 nmi_intc: interrupt-controller@01c00030 { 658 compatible = "allwinner,sun7i-a20-sc-nmi"; 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 reg = <0x01c00030 0x0c>; 662 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 663 }; 664 665 dma: dma-controller@01c02000 { 666 compatible = "allwinner,sun4i-a10-dma"; 667 reg = <0x01c02000 0x1000>; 668 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&ahb_gates 6>; 670 #dma-cells = <2>; 671 }; 672 673 spi0: spi@01c05000 { 674 compatible = "allwinner,sun4i-a10-spi"; 675 reg = <0x01c05000 0x1000>; 676 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&ahb_gates 20>, <&spi0_clk>; 678 clock-names = "ahb", "mod"; 679 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 680 <&dma SUN4I_DMA_DEDICATED 26>; 681 dma-names = "rx", "tx"; 682 status = "disabled"; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 }; 686 687 spi1: spi@01c06000 { 688 compatible = "allwinner,sun4i-a10-spi"; 689 reg = <0x01c06000 0x1000>; 690 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&ahb_gates 21>, <&spi1_clk>; 692 clock-names = "ahb", "mod"; 693 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 694 <&dma SUN4I_DMA_DEDICATED 8>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 }; 700 701 emac: ethernet@01c0b000 { 702 compatible = "allwinner,sun4i-a10-emac"; 703 reg = <0x01c0b000 0x1000>; 704 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&ahb_gates 17>; 706 allwinner,sram = <&emac_sram 1>; 707 status = "disabled"; 708 }; 709 710 mdio: mdio@01c0b080 { 711 compatible = "allwinner,sun4i-a10-mdio"; 712 reg = <0x01c0b080 0x14>; 713 status = "disabled"; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 }; 717 718 mmc0: mmc@01c0f000 { 719 compatible = "allwinner,sun5i-a13-mmc"; 720 reg = <0x01c0f000 0x1000>; 721 clocks = <&ahb_gates 8>, 722 <&mmc0_clk 0>, 723 <&mmc0_clk 1>, 724 <&mmc0_clk 2>; 725 clock-names = "ahb", 726 "mmc", 727 "output", 728 "sample"; 729 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 730 status = "disabled"; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 }; 734 735 mmc1: mmc@01c10000 { 736 compatible = "allwinner,sun5i-a13-mmc"; 737 reg = <0x01c10000 0x1000>; 738 clocks = <&ahb_gates 9>, 739 <&mmc1_clk 0>, 740 <&mmc1_clk 1>, 741 <&mmc1_clk 2>; 742 clock-names = "ahb", 743 "mmc", 744 "output", 745 "sample"; 746 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 747 status = "disabled"; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 }; 751 752 mmc2: mmc@01c11000 { 753 compatible = "allwinner,sun5i-a13-mmc"; 754 reg = <0x01c11000 0x1000>; 755 clocks = <&ahb_gates 10>, 756 <&mmc2_clk 0>, 757 <&mmc2_clk 1>, 758 <&mmc2_clk 2>; 759 clock-names = "ahb", 760 "mmc", 761 "output", 762 "sample"; 763 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 764 status = "disabled"; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 }; 768 769 mmc3: mmc@01c12000 { 770 compatible = "allwinner,sun5i-a13-mmc"; 771 reg = <0x01c12000 0x1000>; 772 clocks = <&ahb_gates 11>, 773 <&mmc3_clk 0>, 774 <&mmc3_clk 1>, 775 <&mmc3_clk 2>; 776 clock-names = "ahb", 777 "mmc", 778 "output", 779 "sample"; 780 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 781 status = "disabled"; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 }; 785 786 usb_otg: usb@01c13000 { 787 compatible = "allwinner,sun4i-a10-musb"; 788 reg = <0x01c13000 0x0400>; 789 clocks = <&ahb_gates 0>; 790 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-names = "mc"; 792 phys = <&usbphy 0>; 793 phy-names = "usb"; 794 extcon = <&usbphy 0>; 795 allwinner,sram = <&otg_sram 1>; 796 status = "disabled"; 797 }; 798 799 usbphy: phy@01c13400 { 800 #phy-cells = <1>; 801 compatible = "allwinner,sun7i-a20-usb-phy"; 802 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 803 reg-names = "phy_ctrl", "pmu1", "pmu2"; 804 clocks = <&usb_clk 8>; 805 clock-names = "usb_phy"; 806 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; 807 reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; 808 status = "disabled"; 809 }; 810 811 ehci0: usb@01c14000 { 812 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 813 reg = <0x01c14000 0x100>; 814 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&ahb_gates 1>; 816 phys = <&usbphy 1>; 817 phy-names = "usb"; 818 status = "disabled"; 819 }; 820 821 ohci0: usb@01c14400 { 822 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 823 reg = <0x01c14400 0x100>; 824 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&usb_clk 6>, <&ahb_gates 2>; 826 phys = <&usbphy 1>; 827 phy-names = "usb"; 828 status = "disabled"; 829 }; 830 831 crypto: crypto-engine@01c15000 { 832 compatible = "allwinner,sun4i-a10-crypto"; 833 reg = <0x01c15000 0x1000>; 834 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&ahb_gates 5>, <&ss_clk>; 836 clock-names = "ahb", "mod"; 837 }; 838 839 spi2: spi@01c17000 { 840 compatible = "allwinner,sun4i-a10-spi"; 841 reg = <0x01c17000 0x1000>; 842 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&ahb_gates 22>, <&spi2_clk>; 844 clock-names = "ahb", "mod"; 845 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 846 <&dma SUN4I_DMA_DEDICATED 28>; 847 dma-names = "rx", "tx"; 848 status = "disabled"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 }; 852 853 ahci: sata@01c18000 { 854 compatible = "allwinner,sun4i-a10-ahci"; 855 reg = <0x01c18000 0x1000>; 856 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&pll6 0>, <&ahb_gates 25>; 858 status = "disabled"; 859 }; 860 861 ehci1: usb@01c1c000 { 862 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 863 reg = <0x01c1c000 0x100>; 864 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&ahb_gates 3>; 866 phys = <&usbphy 2>; 867 phy-names = "usb"; 868 status = "disabled"; 869 }; 870 871 ohci1: usb@01c1c400 { 872 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 873 reg = <0x01c1c400 0x100>; 874 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&usb_clk 7>, <&ahb_gates 4>; 876 phys = <&usbphy 2>; 877 phy-names = "usb"; 878 status = "disabled"; 879 }; 880 881 spi3: spi@01c1f000 { 882 compatible = "allwinner,sun4i-a10-spi"; 883 reg = <0x01c1f000 0x1000>; 884 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&ahb_gates 23>, <&spi3_clk>; 886 clock-names = "ahb", "mod"; 887 dmas = <&dma SUN4I_DMA_DEDICATED 31>, 888 <&dma SUN4I_DMA_DEDICATED 30>; 889 dma-names = "rx", "tx"; 890 status = "disabled"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 }; 894 895 pio: pinctrl@01c20800 { 896 compatible = "allwinner,sun7i-a20-pinctrl"; 897 reg = <0x01c20800 0x400>; 898 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&apb0_gates 5>; 900 gpio-controller; 901 interrupt-controller; 902 #interrupt-cells = <3>; 903 #gpio-cells = <3>; 904 905 pwm0_pins_a: pwm0@0 { 906 allwinner,pins = "PB2"; 907 allwinner,function = "pwm"; 908 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 909 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 910 }; 911 912 pwm1_pins_a: pwm1@0 { 913 allwinner,pins = "PI3"; 914 allwinner,function = "pwm"; 915 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 916 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 917 }; 918 919 uart0_pins_a: uart0@0 { 920 allwinner,pins = "PB22", "PB23"; 921 allwinner,function = "uart0"; 922 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 923 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 924 }; 925 926 uart2_pins_a: uart2@0 { 927 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 928 allwinner,function = "uart2"; 929 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 930 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 931 }; 932 933 uart3_pins_a: uart3@0 { 934 allwinner,pins = "PG6", "PG7", "PG8", "PG9"; 935 allwinner,function = "uart3"; 936 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 937 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 938 }; 939 940 uart3_pins_b: uart3@1 { 941 allwinner,pins = "PH0", "PH1"; 942 allwinner,function = "uart3"; 943 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 944 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 945 }; 946 947 uart4_pins_a: uart4@0 { 948 allwinner,pins = "PG10", "PG11"; 949 allwinner,function = "uart4"; 950 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 951 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 952 }; 953 954 uart4_pins_b: uart4@1 { 955 allwinner,pins = "PH4", "PH5"; 956 allwinner,function = "uart4"; 957 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 958 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 959 }; 960 961 uart5_pins_a: uart5@0 { 962 allwinner,pins = "PI10", "PI11"; 963 allwinner,function = "uart5"; 964 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 965 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 966 }; 967 968 uart6_pins_a: uart6@0 { 969 allwinner,pins = "PI12", "PI13"; 970 allwinner,function = "uart6"; 971 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 972 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 973 }; 974 975 uart7_pins_a: uart7@0 { 976 allwinner,pins = "PI20", "PI21"; 977 allwinner,function = "uart7"; 978 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 979 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 980 }; 981 982 i2c0_pins_a: i2c0@0 { 983 allwinner,pins = "PB0", "PB1"; 984 allwinner,function = "i2c0"; 985 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 986 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 987 }; 988 989 i2c1_pins_a: i2c1@0 { 990 allwinner,pins = "PB18", "PB19"; 991 allwinner,function = "i2c1"; 992 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 993 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 994 }; 995 996 i2c2_pins_a: i2c2@0 { 997 allwinner,pins = "PB20", "PB21"; 998 allwinner,function = "i2c2"; 999 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1000 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1001 }; 1002 1003 i2c3_pins_a: i2c3@0 { 1004 allwinner,pins = "PI0", "PI1"; 1005 allwinner,function = "i2c3"; 1006 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1007 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1008 }; 1009 1010 emac_pins_a: emac0@0 { 1011 allwinner,pins = "PA0", "PA1", "PA2", 1012 "PA3", "PA4", "PA5", "PA6", 1013 "PA7", "PA8", "PA9", "PA10", 1014 "PA11", "PA12", "PA13", "PA14", 1015 "PA15", "PA16"; 1016 allwinner,function = "emac"; 1017 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1018 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1019 }; 1020 1021 clk_out_a_pins_a: clk_out_a@0 { 1022 allwinner,pins = "PI12"; 1023 allwinner,function = "clk_out_a"; 1024 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1025 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1026 }; 1027 1028 clk_out_b_pins_a: clk_out_b@0 { 1029 allwinner,pins = "PI13"; 1030 allwinner,function = "clk_out_b"; 1031 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1032 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1033 }; 1034 1035 gmac_pins_mii_a: gmac_mii@0 { 1036 allwinner,pins = "PA0", "PA1", "PA2", 1037 "PA3", "PA4", "PA5", "PA6", 1038 "PA7", "PA8", "PA9", "PA10", 1039 "PA11", "PA12", "PA13", "PA14", 1040 "PA15", "PA16"; 1041 allwinner,function = "gmac"; 1042 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1043 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1044 }; 1045 1046 gmac_pins_rgmii_a: gmac_rgmii@0 { 1047 allwinner,pins = "PA0", "PA1", "PA2", 1048 "PA3", "PA4", "PA5", "PA6", 1049 "PA7", "PA8", "PA10", 1050 "PA11", "PA12", "PA13", 1051 "PA15", "PA16"; 1052 allwinner,function = "gmac"; 1053 /* 1054 * data lines in RGMII mode use DDR mode 1055 * and need a higher signal drive strength 1056 */ 1057 allwinner,drive = <SUN4I_PINCTRL_40_MA>; 1058 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1059 }; 1060 1061 spi0_pins_a: spi0@0 { 1062 allwinner,pins = "PI11", "PI12", "PI13"; 1063 allwinner,function = "spi0"; 1064 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1065 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1066 }; 1067 1068 spi0_cs0_pins_a: spi0_cs0@0 { 1069 allwinner,pins = "PI10"; 1070 allwinner,function = "spi0"; 1071 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1072 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1073 }; 1074 1075 spi0_cs1_pins_a: spi0_cs1@0 { 1076 allwinner,pins = "PI14"; 1077 allwinner,function = "spi0"; 1078 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1079 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1080 }; 1081 1082 spi1_pins_a: spi1@0 { 1083 allwinner,pins = "PI17", "PI18", "PI19"; 1084 allwinner,function = "spi1"; 1085 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1086 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1087 }; 1088 1089 spi1_cs0_pins_a: spi1_cs0@0 { 1090 allwinner,pins = "PI16"; 1091 allwinner,function = "spi1"; 1092 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1093 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1094 }; 1095 1096 spi2_pins_a: spi2@0 { 1097 allwinner,pins = "PC20", "PC21", "PC22"; 1098 allwinner,function = "spi2"; 1099 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1100 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1101 }; 1102 1103 spi2_pins_b: spi2@1 { 1104 allwinner,pins = "PB15", "PB16", "PB17"; 1105 allwinner,function = "spi2"; 1106 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1107 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1108 }; 1109 1110 spi2_cs0_pins_a: spi2_cs0@0 { 1111 allwinner,pins = "PC19"; 1112 allwinner,function = "spi2"; 1113 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1114 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1115 }; 1116 1117 spi2_cs0_pins_b: spi2_cs0@1 { 1118 allwinner,pins = "PB14"; 1119 allwinner,function = "spi2"; 1120 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1121 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1122 }; 1123 1124 mmc0_pins_a: mmc0@0 { 1125 allwinner,pins = "PF0", "PF1", "PF2", 1126 "PF3", "PF4", "PF5"; 1127 allwinner,function = "mmc0"; 1128 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 1129 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1130 }; 1131 1132 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 1133 allwinner,pins = "PH1"; 1134 allwinner,function = "gpio_in"; 1135 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1136 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 1137 }; 1138 1139 mmc2_pins_a: mmc2@0 { 1140 allwinner,pins = "PC6", "PC7", "PC8", 1141 "PC9", "PC10", "PC11"; 1142 allwinner,function = "mmc2"; 1143 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 1144 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 1145 }; 1146 1147 mmc3_pins_a: mmc3@0 { 1148 allwinner,pins = "PI4", "PI5", "PI6", 1149 "PI7", "PI8", "PI9"; 1150 allwinner,function = "mmc3"; 1151 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 1152 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1153 }; 1154 1155 ir0_rx_pins_a: ir0@0 { 1156 allwinner,pins = "PB4"; 1157 allwinner,function = "ir0"; 1158 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1159 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1160 }; 1161 1162 ir0_tx_pins_a: ir0@1 { 1163 allwinner,pins = "PB3"; 1164 allwinner,function = "ir0"; 1165 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1166 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1167 }; 1168 1169 ir1_rx_pins_a: ir1@0 { 1170 allwinner,pins = "PB23"; 1171 allwinner,function = "ir1"; 1172 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1173 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1174 }; 1175 1176 ir1_tx_pins_a: ir1@1 { 1177 allwinner,pins = "PB22"; 1178 allwinner,function = "ir1"; 1179 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1180 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1181 }; 1182 1183 ps20_pins_a: ps20@0 { 1184 allwinner,pins = "PI20", "PI21"; 1185 allwinner,function = "ps2"; 1186 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1187 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1188 }; 1189 1190 ps21_pins_a: ps21@0 { 1191 allwinner,pins = "PH12", "PH13"; 1192 allwinner,function = "ps2"; 1193 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1194 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1195 }; 1196 }; 1197 1198 timer@01c20c00 { 1199 compatible = "allwinner,sun4i-a10-timer"; 1200 reg = <0x01c20c00 0x90>; 1201 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&osc24M>; 1208 }; 1209 1210 wdt: watchdog@01c20c90 { 1211 compatible = "allwinner,sun4i-a10-wdt"; 1212 reg = <0x01c20c90 0x10>; 1213 }; 1214 1215 rtc: rtc@01c20d00 { 1216 compatible = "allwinner,sun7i-a20-rtc"; 1217 reg = <0x01c20d00 0x20>; 1218 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1219 }; 1220 1221 pwm: pwm@01c20e00 { 1222 compatible = "allwinner,sun7i-a20-pwm"; 1223 reg = <0x01c20e00 0xc>; 1224 clocks = <&osc24M>; 1225 #pwm-cells = <3>; 1226 status = "disabled"; 1227 }; 1228 1229 ir0: ir@01c21800 { 1230 compatible = "allwinner,sun4i-a10-ir"; 1231 clocks = <&apb0_gates 6>, <&ir0_clk>; 1232 clock-names = "apb", "ir"; 1233 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1234 reg = <0x01c21800 0x40>; 1235 status = "disabled"; 1236 }; 1237 1238 ir1: ir@01c21c00 { 1239 compatible = "allwinner,sun4i-a10-ir"; 1240 clocks = <&apb0_gates 7>, <&ir1_clk>; 1241 clock-names = "apb", "ir"; 1242 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1243 reg = <0x01c21c00 0x40>; 1244 status = "disabled"; 1245 }; 1246 1247 lradc: lradc@01c22800 { 1248 compatible = "allwinner,sun4i-a10-lradc-keys"; 1249 reg = <0x01c22800 0x100>; 1250 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1251 status = "disabled"; 1252 }; 1253 1254 codec: codec@01c22c00 { 1255 #sound-dai-cells = <0>; 1256 compatible = "allwinner,sun7i-a20-codec"; 1257 reg = <0x01c22c00 0x40>; 1258 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&apb0_gates 0>, <&codec_clk>; 1260 clock-names = "apb", "codec"; 1261 dmas = <&dma SUN4I_DMA_NORMAL 19>, 1262 <&dma SUN4I_DMA_NORMAL 19>; 1263 dma-names = "rx", "tx"; 1264 status = "disabled"; 1265 }; 1266 1267 sid: eeprom@01c23800 { 1268 compatible = "allwinner,sun7i-a20-sid"; 1269 reg = <0x01c23800 0x200>; 1270 }; 1271 1272 rtp: rtp@01c25000 { 1273 compatible = "allwinner,sun5i-a13-ts"; 1274 reg = <0x01c25000 0x100>; 1275 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1276 #thermal-sensor-cells = <0>; 1277 }; 1278 1279 uart0: serial@01c28000 { 1280 compatible = "snps,dw-apb-uart"; 1281 reg = <0x01c28000 0x400>; 1282 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1283 reg-shift = <2>; 1284 reg-io-width = <4>; 1285 clocks = <&apb1_gates 16>; 1286 status = "disabled"; 1287 }; 1288 1289 uart1: serial@01c28400 { 1290 compatible = "snps,dw-apb-uart"; 1291 reg = <0x01c28400 0x400>; 1292 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1293 reg-shift = <2>; 1294 reg-io-width = <4>; 1295 clocks = <&apb1_gates 17>; 1296 status = "disabled"; 1297 }; 1298 1299 uart2: serial@01c28800 { 1300 compatible = "snps,dw-apb-uart"; 1301 reg = <0x01c28800 0x400>; 1302 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1303 reg-shift = <2>; 1304 reg-io-width = <4>; 1305 clocks = <&apb1_gates 18>; 1306 status = "disabled"; 1307 }; 1308 1309 uart3: serial@01c28c00 { 1310 compatible = "snps,dw-apb-uart"; 1311 reg = <0x01c28c00 0x400>; 1312 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1313 reg-shift = <2>; 1314 reg-io-width = <4>; 1315 clocks = <&apb1_gates 19>; 1316 status = "disabled"; 1317 }; 1318 1319 uart4: serial@01c29000 { 1320 compatible = "snps,dw-apb-uart"; 1321 reg = <0x01c29000 0x400>; 1322 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1323 reg-shift = <2>; 1324 reg-io-width = <4>; 1325 clocks = <&apb1_gates 20>; 1326 status = "disabled"; 1327 }; 1328 1329 uart5: serial@01c29400 { 1330 compatible = "snps,dw-apb-uart"; 1331 reg = <0x01c29400 0x400>; 1332 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1333 reg-shift = <2>; 1334 reg-io-width = <4>; 1335 clocks = <&apb1_gates 21>; 1336 status = "disabled"; 1337 }; 1338 1339 uart6: serial@01c29800 { 1340 compatible = "snps,dw-apb-uart"; 1341 reg = <0x01c29800 0x400>; 1342 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1343 reg-shift = <2>; 1344 reg-io-width = <4>; 1345 clocks = <&apb1_gates 22>; 1346 status = "disabled"; 1347 }; 1348 1349 uart7: serial@01c29c00 { 1350 compatible = "snps,dw-apb-uart"; 1351 reg = <0x01c29c00 0x400>; 1352 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1353 reg-shift = <2>; 1354 reg-io-width = <4>; 1355 clocks = <&apb1_gates 23>; 1356 status = "disabled"; 1357 }; 1358 1359 i2c0: i2c@01c2ac00 { 1360 compatible = "allwinner,sun7i-a20-i2c", 1361 "allwinner,sun4i-a10-i2c"; 1362 reg = <0x01c2ac00 0x400>; 1363 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&apb1_gates 0>; 1365 status = "disabled"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 }; 1369 1370 i2c1: i2c@01c2b000 { 1371 compatible = "allwinner,sun7i-a20-i2c", 1372 "allwinner,sun4i-a10-i2c"; 1373 reg = <0x01c2b000 0x400>; 1374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&apb1_gates 1>; 1376 status = "disabled"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 }; 1380 1381 i2c2: i2c@01c2b400 { 1382 compatible = "allwinner,sun7i-a20-i2c", 1383 "allwinner,sun4i-a10-i2c"; 1384 reg = <0x01c2b400 0x400>; 1385 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&apb1_gates 2>; 1387 status = "disabled"; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 }; 1391 1392 i2c3: i2c@01c2b800 { 1393 compatible = "allwinner,sun7i-a20-i2c", 1394 "allwinner,sun4i-a10-i2c"; 1395 reg = <0x01c2b800 0x400>; 1396 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&apb1_gates 3>; 1398 status = "disabled"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 }; 1402 1403 i2c4: i2c@01c2c000 { 1404 compatible = "allwinner,sun7i-a20-i2c", 1405 "allwinner,sun4i-a10-i2c"; 1406 reg = <0x01c2c000 0x400>; 1407 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&apb1_gates 15>; 1409 status = "disabled"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 }; 1413 1414 gmac: ethernet@01c50000 { 1415 compatible = "allwinner,sun7i-a20-gmac"; 1416 reg = <0x01c50000 0x10000>; 1417 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1418 interrupt-names = "macirq"; 1419 clocks = <&ahb_gates 49>, <&gmac_tx_clk>; 1420 clock-names = "stmmaceth", "allwinner_gmac_tx"; 1421 snps,pbl = <2>; 1422 snps,fixed-burst; 1423 snps,force_sf_dma_mode; 1424 status = "disabled"; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 }; 1428 1429 hstimer@01c60000 { 1430 compatible = "allwinner,sun7i-a20-hstimer"; 1431 reg = <0x01c60000 0x1000>; 1432 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&ahb_gates 28>; 1437 }; 1438 1439 gic: interrupt-controller@01c81000 { 1440 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1441 reg = <0x01c81000 0x1000>, 1442 <0x01c82000 0x1000>, 1443 <0x01c84000 0x2000>, 1444 <0x01c86000 0x2000>; 1445 interrupt-controller; 1446 #interrupt-cells = <3>; 1447 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1448 }; 1449 1450 ps20: ps2@01c2a000 { 1451 compatible = "allwinner,sun4i-a10-ps2"; 1452 reg = <0x01c2a000 0x400>; 1453 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1454 clocks = <&apb1_gates 6>; 1455 status = "disabled"; 1456 }; 1457 1458 ps21: ps2@01c2a400 { 1459 compatible = "allwinner,sun4i-a10-ps2"; 1460 reg = <0x01c2a400 0x400>; 1461 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&apb1_gates 7>; 1463 status = "disabled"; 1464 }; 1465 }; 1466}; 1467