1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14/include/ "skeleton.dtsi" 15 16/ { 17 interrupt-parent = <&gic>; 18 19 aliases { 20 ethernet0 = &gmac; 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 serial5 = &uart5; 27 serial6 = &uart6; 28 serial7 = &uart7; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 compatible = "arm,cortex-a7"; 37 device_type = "cpu"; 38 reg = <0>; 39 }; 40 41 cpu@1 { 42 compatible = "arm,cortex-a7"; 43 device_type = "cpu"; 44 reg = <1>; 45 }; 46 }; 47 48 memory { 49 reg = <0x40000000 0x80000000>; 50 }; 51 52 timer { 53 compatible = "arm,armv7-timer"; 54 interrupts = <1 13 0xf08>, 55 <1 14 0xf08>, 56 <1 11 0xf08>, 57 <1 10 0xf08>; 58 }; 59 60 pmu { 61 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 62 interrupts = <0 120 4>, 63 <0 121 4>; 64 }; 65 66 clocks { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 osc24M: clk@01c20050 { 72 #clock-cells = <0>; 73 compatible = "allwinner,sun4i-a10-osc-clk"; 74 reg = <0x01c20050 0x4>; 75 clock-frequency = <24000000>; 76 clock-output-names = "osc24M"; 77 }; 78 79 osc32k: clk@0 { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <32768>; 83 clock-output-names = "osc32k"; 84 }; 85 86 pll1: clk@01c20000 { 87 #clock-cells = <0>; 88 compatible = "allwinner,sun4i-a10-pll1-clk"; 89 reg = <0x01c20000 0x4>; 90 clocks = <&osc24M>; 91 clock-output-names = "pll1"; 92 }; 93 94 pll4: clk@01c20018 { 95 #clock-cells = <0>; 96 compatible = "allwinner,sun7i-a20-pll4-clk"; 97 reg = <0x01c20018 0x4>; 98 clocks = <&osc24M>; 99 clock-output-names = "pll4"; 100 }; 101 102 pll5: clk@01c20020 { 103 #clock-cells = <1>; 104 compatible = "allwinner,sun4i-a10-pll5-clk"; 105 reg = <0x01c20020 0x4>; 106 clocks = <&osc24M>; 107 clock-output-names = "pll5_ddr", "pll5_other"; 108 }; 109 110 pll6: clk@01c20028 { 111 #clock-cells = <1>; 112 compatible = "allwinner,sun4i-a10-pll6-clk"; 113 reg = <0x01c20028 0x4>; 114 clocks = <&osc24M>; 115 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 116 }; 117 118 pll8: clk@01c20040 { 119 #clock-cells = <0>; 120 compatible = "allwinner,sun7i-a20-pll4-clk"; 121 reg = <0x01c20040 0x4>; 122 clocks = <&osc24M>; 123 clock-output-names = "pll8"; 124 }; 125 126 cpu: cpu@01c20054 { 127 #clock-cells = <0>; 128 compatible = "allwinner,sun4i-a10-cpu-clk"; 129 reg = <0x01c20054 0x4>; 130 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 131 clock-output-names = "cpu"; 132 }; 133 134 axi: axi@01c20054 { 135 #clock-cells = <0>; 136 compatible = "allwinner,sun4i-a10-axi-clk"; 137 reg = <0x01c20054 0x4>; 138 clocks = <&cpu>; 139 clock-output-names = "axi"; 140 }; 141 142 ahb: ahb@01c20054 { 143 #clock-cells = <0>; 144 compatible = "allwinner,sun4i-a10-ahb-clk"; 145 reg = <0x01c20054 0x4>; 146 clocks = <&axi>; 147 clock-output-names = "ahb"; 148 }; 149 150 ahb_gates: clk@01c20060 { 151 #clock-cells = <1>; 152 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 153 reg = <0x01c20060 0x8>; 154 clocks = <&ahb>; 155 clock-output-names = "ahb_usb0", "ahb_ehci0", 156 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", 157 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", 158 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", 159 "ahb_nand", "ahb_sdram", "ahb_ace", 160 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", 161 "ahb_spi2", "ahb_spi3", "ahb_sata", 162 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0", 163 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", 164 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0", 165 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", 166 "ahb_de_fe1", "ahb_gmac", "ahb_mp", 167 "ahb_mali"; 168 }; 169 170 apb0: apb0@01c20054 { 171 #clock-cells = <0>; 172 compatible = "allwinner,sun4i-a10-apb0-clk"; 173 reg = <0x01c20054 0x4>; 174 clocks = <&ahb>; 175 clock-output-names = "apb0"; 176 }; 177 178 apb0_gates: clk@01c20068 { 179 #clock-cells = <1>; 180 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 181 reg = <0x01c20068 0x4>; 182 clocks = <&apb0>; 183 clock-output-names = "apb0_codec", "apb0_spdif", 184 "apb0_ac97", "apb0_iis0", "apb0_iis1", 185 "apb0_pio", "apb0_ir0", "apb0_ir1", 186 "apb0_iis2", "apb0_keypad"; 187 }; 188 189 apb1_mux: apb1_mux@01c20058 { 190 #clock-cells = <0>; 191 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 192 reg = <0x01c20058 0x4>; 193 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 194 clock-output-names = "apb1_mux"; 195 }; 196 197 apb1: apb1@01c20058 { 198 #clock-cells = <0>; 199 compatible = "allwinner,sun4i-a10-apb1-clk"; 200 reg = <0x01c20058 0x4>; 201 clocks = <&apb1_mux>; 202 clock-output-names = "apb1"; 203 }; 204 205 apb1_gates: clk@01c2006c { 206 #clock-cells = <1>; 207 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 208 reg = <0x01c2006c 0x4>; 209 clocks = <&apb1>; 210 clock-output-names = "apb1_i2c0", "apb1_i2c1", 211 "apb1_i2c2", "apb1_i2c3", "apb1_can", 212 "apb1_scr", "apb1_ps20", "apb1_ps21", 213 "apb1_i2c4", "apb1_uart0", "apb1_uart1", 214 "apb1_uart2", "apb1_uart3", "apb1_uart4", 215 "apb1_uart5", "apb1_uart6", "apb1_uart7"; 216 }; 217 218 nand_clk: clk@01c20080 { 219 #clock-cells = <0>; 220 compatible = "allwinner,sun4i-a10-mod0-clk"; 221 reg = <0x01c20080 0x4>; 222 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 223 clock-output-names = "nand"; 224 }; 225 226 ms_clk: clk@01c20084 { 227 #clock-cells = <0>; 228 compatible = "allwinner,sun4i-a10-mod0-clk"; 229 reg = <0x01c20084 0x4>; 230 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 231 clock-output-names = "ms"; 232 }; 233 234 mmc0_clk: clk@01c20088 { 235 #clock-cells = <0>; 236 compatible = "allwinner,sun4i-a10-mod0-clk"; 237 reg = <0x01c20088 0x4>; 238 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 239 clock-output-names = "mmc0"; 240 }; 241 242 mmc1_clk: clk@01c2008c { 243 #clock-cells = <0>; 244 compatible = "allwinner,sun4i-a10-mod0-clk"; 245 reg = <0x01c2008c 0x4>; 246 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 247 clock-output-names = "mmc1"; 248 }; 249 250 mmc2_clk: clk@01c20090 { 251 #clock-cells = <0>; 252 compatible = "allwinner,sun4i-a10-mod0-clk"; 253 reg = <0x01c20090 0x4>; 254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 255 clock-output-names = "mmc2"; 256 }; 257 258 mmc3_clk: clk@01c20094 { 259 #clock-cells = <0>; 260 compatible = "allwinner,sun4i-a10-mod0-clk"; 261 reg = <0x01c20094 0x4>; 262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 263 clock-output-names = "mmc3"; 264 }; 265 266 ts_clk: clk@01c20098 { 267 #clock-cells = <0>; 268 compatible = "allwinner,sun4i-a10-mod0-clk"; 269 reg = <0x01c20098 0x4>; 270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 271 clock-output-names = "ts"; 272 }; 273 274 ss_clk: clk@01c2009c { 275 #clock-cells = <0>; 276 compatible = "allwinner,sun4i-a10-mod0-clk"; 277 reg = <0x01c2009c 0x4>; 278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 279 clock-output-names = "ss"; 280 }; 281 282 spi0_clk: clk@01c200a0 { 283 #clock-cells = <0>; 284 compatible = "allwinner,sun4i-a10-mod0-clk"; 285 reg = <0x01c200a0 0x4>; 286 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 287 clock-output-names = "spi0"; 288 }; 289 290 spi1_clk: clk@01c200a4 { 291 #clock-cells = <0>; 292 compatible = "allwinner,sun4i-a10-mod0-clk"; 293 reg = <0x01c200a4 0x4>; 294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 295 clock-output-names = "spi1"; 296 }; 297 298 spi2_clk: clk@01c200a8 { 299 #clock-cells = <0>; 300 compatible = "allwinner,sun4i-a10-mod0-clk"; 301 reg = <0x01c200a8 0x4>; 302 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 303 clock-output-names = "spi2"; 304 }; 305 306 pata_clk: clk@01c200ac { 307 #clock-cells = <0>; 308 compatible = "allwinner,sun4i-a10-mod0-clk"; 309 reg = <0x01c200ac 0x4>; 310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 311 clock-output-names = "pata"; 312 }; 313 314 ir0_clk: clk@01c200b0 { 315 #clock-cells = <0>; 316 compatible = "allwinner,sun4i-a10-mod0-clk"; 317 reg = <0x01c200b0 0x4>; 318 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 319 clock-output-names = "ir0"; 320 }; 321 322 ir1_clk: clk@01c200b4 { 323 #clock-cells = <0>; 324 compatible = "allwinner,sun4i-a10-mod0-clk"; 325 reg = <0x01c200b4 0x4>; 326 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 327 clock-output-names = "ir1"; 328 }; 329 330 usb_clk: clk@01c200cc { 331 #clock-cells = <1>; 332 #reset-cells = <1>; 333 compatible = "allwinner,sun4i-a10-usb-clk"; 334 reg = <0x01c200cc 0x4>; 335 clocks = <&pll6 1>; 336 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; 337 }; 338 339 spi3_clk: clk@01c200d4 { 340 #clock-cells = <0>; 341 compatible = "allwinner,sun4i-a10-mod0-clk"; 342 reg = <0x01c200d4 0x4>; 343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 344 clock-output-names = "spi3"; 345 }; 346 347 mbus_clk: clk@01c2015c { 348 #clock-cells = <0>; 349 compatible = "allwinner,sun4i-a10-mod0-clk"; 350 reg = <0x01c2015c 0x4>; 351 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 352 clock-output-names = "mbus"; 353 }; 354 355 /* 356 * The following two are dummy clocks, placeholders used in the gmac_tx 357 * clock. The gmac driver will choose one parent depending on the PHY 358 * interface mode, using clk_set_rate auto-reparenting. 359 * The actual TX clock rate is not controlled by the gmac_tx clock. 360 */ 361 mii_phy_tx_clk: clk@2 { 362 #clock-cells = <0>; 363 compatible = "fixed-clock"; 364 clock-frequency = <25000000>; 365 clock-output-names = "mii_phy_tx"; 366 }; 367 368 gmac_int_tx_clk: clk@3 { 369 #clock-cells = <0>; 370 compatible = "fixed-clock"; 371 clock-frequency = <125000000>; 372 clock-output-names = "gmac_int_tx"; 373 }; 374 375 gmac_tx_clk: clk@01c20164 { 376 #clock-cells = <0>; 377 compatible = "allwinner,sun7i-a20-gmac-clk"; 378 reg = <0x01c20164 0x4>; 379 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 380 clock-output-names = "gmac_tx"; 381 }; 382 383 /* 384 * Dummy clock used by output clocks 385 */ 386 osc24M_32k: clk@1 { 387 #clock-cells = <0>; 388 compatible = "fixed-factor-clock"; 389 clock-div = <750>; 390 clock-mult = <1>; 391 clocks = <&osc24M>; 392 clock-output-names = "osc24M_32k"; 393 }; 394 395 clk_out_a: clk@01c201f0 { 396 #clock-cells = <0>; 397 compatible = "allwinner,sun7i-a20-out-clk"; 398 reg = <0x01c201f0 0x4>; 399 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 400 clock-output-names = "clk_out_a"; 401 }; 402 403 clk_out_b: clk@01c201f4 { 404 #clock-cells = <0>; 405 compatible = "allwinner,sun7i-a20-out-clk"; 406 reg = <0x01c201f4 0x4>; 407 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; 408 clock-output-names = "clk_out_b"; 409 }; 410 }; 411 412 soc@01c00000 { 413 compatible = "simple-bus"; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 ranges; 417 418 nmi_intc: interrupt-controller@01c00030 { 419 compatible = "allwinner,sun7i-a20-sc-nmi"; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 reg = <0x01c00030 0x0c>; 423 interrupts = <0 0 4>; 424 }; 425 426 spi0: spi@01c05000 { 427 compatible = "allwinner,sun4i-a10-spi"; 428 reg = <0x01c05000 0x1000>; 429 interrupts = <0 10 4>; 430 clocks = <&ahb_gates 20>, <&spi0_clk>; 431 clock-names = "ahb", "mod"; 432 status = "disabled"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 }; 436 437 spi1: spi@01c06000 { 438 compatible = "allwinner,sun4i-a10-spi"; 439 reg = <0x01c06000 0x1000>; 440 interrupts = <0 11 4>; 441 clocks = <&ahb_gates 21>, <&spi1_clk>; 442 clock-names = "ahb", "mod"; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 emac: ethernet@01c0b000 { 449 compatible = "allwinner,sun4i-a10-emac"; 450 reg = <0x01c0b000 0x1000>; 451 interrupts = <0 55 4>; 452 clocks = <&ahb_gates 17>; 453 status = "disabled"; 454 }; 455 456 mdio@01c0b080 { 457 compatible = "allwinner,sun4i-a10-mdio"; 458 reg = <0x01c0b080 0x14>; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 }; 463 464 mmc0: mmc@01c0f000 { 465 compatible = "allwinner,sun5i-a13-mmc"; 466 reg = <0x01c0f000 0x1000>; 467 clocks = <&ahb_gates 8>, <&mmc0_clk>; 468 clock-names = "ahb", "mmc"; 469 interrupts = <0 32 4>; 470 status = "disabled"; 471 }; 472 473 mmc1: mmc@01c10000 { 474 compatible = "allwinner,sun5i-a13-mmc"; 475 reg = <0x01c10000 0x1000>; 476 clocks = <&ahb_gates 9>, <&mmc1_clk>; 477 clock-names = "ahb", "mmc"; 478 interrupts = <0 33 4>; 479 status = "disabled"; 480 }; 481 482 mmc2: mmc@01c11000 { 483 compatible = "allwinner,sun5i-a13-mmc"; 484 reg = <0x01c11000 0x1000>; 485 clocks = <&ahb_gates 10>, <&mmc2_clk>; 486 clock-names = "ahb", "mmc"; 487 interrupts = <0 34 4>; 488 status = "disabled"; 489 }; 490 491 mmc3: mmc@01c12000 { 492 compatible = "allwinner,sun5i-a13-mmc"; 493 reg = <0x01c12000 0x1000>; 494 clocks = <&ahb_gates 11>, <&mmc3_clk>; 495 clock-names = "ahb", "mmc"; 496 interrupts = <0 35 4>; 497 status = "disabled"; 498 }; 499 500 usbphy: phy@01c13400 { 501 #phy-cells = <1>; 502 compatible = "allwinner,sun7i-a20-usb-phy"; 503 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; 504 reg-names = "phy_ctrl", "pmu1", "pmu2"; 505 clocks = <&usb_clk 8>; 506 clock-names = "usb_phy"; 507 resets = <&usb_clk 1>, <&usb_clk 2>; 508 reset-names = "usb1_reset", "usb2_reset"; 509 status = "disabled"; 510 }; 511 512 ehci0: usb@01c14000 { 513 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 514 reg = <0x01c14000 0x100>; 515 interrupts = <0 39 4>; 516 clocks = <&ahb_gates 1>; 517 phys = <&usbphy 1>; 518 phy-names = "usb"; 519 status = "disabled"; 520 }; 521 522 ohci0: usb@01c14400 { 523 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 524 reg = <0x01c14400 0x100>; 525 interrupts = <0 64 4>; 526 clocks = <&usb_clk 6>, <&ahb_gates 2>; 527 phys = <&usbphy 1>; 528 phy-names = "usb"; 529 status = "disabled"; 530 }; 531 532 spi2: spi@01c17000 { 533 compatible = "allwinner,sun4i-a10-spi"; 534 reg = <0x01c17000 0x1000>; 535 interrupts = <0 12 4>; 536 clocks = <&ahb_gates 22>, <&spi2_clk>; 537 clock-names = "ahb", "mod"; 538 status = "disabled"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 }; 542 543 ahci: sata@01c18000 { 544 compatible = "allwinner,sun4i-a10-ahci"; 545 reg = <0x01c18000 0x1000>; 546 interrupts = <0 56 4>; 547 clocks = <&pll6 0>, <&ahb_gates 25>; 548 status = "disabled"; 549 }; 550 551 ehci1: usb@01c1c000 { 552 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; 553 reg = <0x01c1c000 0x100>; 554 interrupts = <0 40 4>; 555 clocks = <&ahb_gates 3>; 556 phys = <&usbphy 2>; 557 phy-names = "usb"; 558 status = "disabled"; 559 }; 560 561 ohci1: usb@01c1c400 { 562 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; 563 reg = <0x01c1c400 0x100>; 564 interrupts = <0 65 4>; 565 clocks = <&usb_clk 7>, <&ahb_gates 4>; 566 phys = <&usbphy 2>; 567 phy-names = "usb"; 568 status = "disabled"; 569 }; 570 571 spi3: spi@01c1f000 { 572 compatible = "allwinner,sun4i-a10-spi"; 573 reg = <0x01c1f000 0x1000>; 574 interrupts = <0 50 4>; 575 clocks = <&ahb_gates 23>, <&spi3_clk>; 576 clock-names = "ahb", "mod"; 577 status = "disabled"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 }; 581 582 pio: pinctrl@01c20800 { 583 compatible = "allwinner,sun7i-a20-pinctrl"; 584 reg = <0x01c20800 0x400>; 585 interrupts = <0 28 4>; 586 clocks = <&apb0_gates 5>; 587 gpio-controller; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 #size-cells = <0>; 591 #gpio-cells = <3>; 592 593 pwm0_pins_a: pwm0@0 { 594 allwinner,pins = "PB2"; 595 allwinner,function = "pwm"; 596 allwinner,drive = <0>; 597 allwinner,pull = <0>; 598 }; 599 600 pwm1_pins_a: pwm1@0 { 601 allwinner,pins = "PI3"; 602 allwinner,function = "pwm"; 603 allwinner,drive = <0>; 604 allwinner,pull = <0>; 605 }; 606 607 uart0_pins_a: uart0@0 { 608 allwinner,pins = "PB22", "PB23"; 609 allwinner,function = "uart0"; 610 allwinner,drive = <0>; 611 allwinner,pull = <0>; 612 }; 613 614 uart2_pins_a: uart2@0 { 615 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 616 allwinner,function = "uart2"; 617 allwinner,drive = <0>; 618 allwinner,pull = <0>; 619 }; 620 621 uart6_pins_a: uart6@0 { 622 allwinner,pins = "PI12", "PI13"; 623 allwinner,function = "uart6"; 624 allwinner,drive = <0>; 625 allwinner,pull = <0>; 626 }; 627 628 uart7_pins_a: uart7@0 { 629 allwinner,pins = "PI20", "PI21"; 630 allwinner,function = "uart7"; 631 allwinner,drive = <0>; 632 allwinner,pull = <0>; 633 }; 634 635 i2c0_pins_a: i2c0@0 { 636 allwinner,pins = "PB0", "PB1"; 637 allwinner,function = "i2c0"; 638 allwinner,drive = <0>; 639 allwinner,pull = <0>; 640 }; 641 642 i2c1_pins_a: i2c1@0 { 643 allwinner,pins = "PB18", "PB19"; 644 allwinner,function = "i2c1"; 645 allwinner,drive = <0>; 646 allwinner,pull = <0>; 647 }; 648 649 i2c2_pins_a: i2c2@0 { 650 allwinner,pins = "PB20", "PB21"; 651 allwinner,function = "i2c2"; 652 allwinner,drive = <0>; 653 allwinner,pull = <0>; 654 }; 655 656 emac_pins_a: emac0@0 { 657 allwinner,pins = "PA0", "PA1", "PA2", 658 "PA3", "PA4", "PA5", "PA6", 659 "PA7", "PA8", "PA9", "PA10", 660 "PA11", "PA12", "PA13", "PA14", 661 "PA15", "PA16"; 662 allwinner,function = "emac"; 663 allwinner,drive = <0>; 664 allwinner,pull = <0>; 665 }; 666 667 clk_out_a_pins_a: clk_out_a@0 { 668 allwinner,pins = "PI12"; 669 allwinner,function = "clk_out_a"; 670 allwinner,drive = <0>; 671 allwinner,pull = <0>; 672 }; 673 674 clk_out_b_pins_a: clk_out_b@0 { 675 allwinner,pins = "PI13"; 676 allwinner,function = "clk_out_b"; 677 allwinner,drive = <0>; 678 allwinner,pull = <0>; 679 }; 680 681 gmac_pins_mii_a: gmac_mii@0 { 682 allwinner,pins = "PA0", "PA1", "PA2", 683 "PA3", "PA4", "PA5", "PA6", 684 "PA7", "PA8", "PA9", "PA10", 685 "PA11", "PA12", "PA13", "PA14", 686 "PA15", "PA16"; 687 allwinner,function = "gmac"; 688 allwinner,drive = <0>; 689 allwinner,pull = <0>; 690 }; 691 692 gmac_pins_rgmii_a: gmac_rgmii@0 { 693 allwinner,pins = "PA0", "PA1", "PA2", 694 "PA3", "PA4", "PA5", "PA6", 695 "PA7", "PA8", "PA10", 696 "PA11", "PA12", "PA13", 697 "PA15", "PA16"; 698 allwinner,function = "gmac"; 699 /* 700 * data lines in RGMII mode use DDR mode 701 * and need a higher signal drive strength 702 */ 703 allwinner,drive = <3>; 704 allwinner,pull = <0>; 705 }; 706 707 spi1_pins_a: spi1@0 { 708 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 709 allwinner,function = "spi1"; 710 allwinner,drive = <0>; 711 allwinner,pull = <0>; 712 }; 713 714 spi2_pins_a: spi2@0 { 715 allwinner,pins = "PC19", "PC20", "PC21", "PC22"; 716 allwinner,function = "spi2"; 717 allwinner,drive = <0>; 718 allwinner,pull = <0>; 719 }; 720 721 mmc0_pins_a: mmc0@0 { 722 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 723 allwinner,function = "mmc0"; 724 allwinner,drive = <2>; 725 allwinner,pull = <0>; 726 }; 727 728 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { 729 allwinner,pins = "PH1"; 730 allwinner,function = "gpio_in"; 731 allwinner,drive = <0>; 732 allwinner,pull = <1>; 733 }; 734 735 mmc3_pins_a: mmc3@0 { 736 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 737 allwinner,function = "mmc3"; 738 allwinner,drive = <2>; 739 allwinner,pull = <0>; 740 }; 741 742 ir0_pins_a: ir0@0 { 743 allwinner,pins = "PB3","PB4"; 744 allwinner,function = "ir0"; 745 allwinner,drive = <0>; 746 allwinner,pull = <0>; 747 }; 748 749 ir1_pins_a: ir1@0 { 750 allwinner,pins = "PB22","PB23"; 751 allwinner,function = "ir1"; 752 allwinner,drive = <0>; 753 allwinner,pull = <0>; 754 }; 755 }; 756 757 timer@01c20c00 { 758 compatible = "allwinner,sun4i-a10-timer"; 759 reg = <0x01c20c00 0x90>; 760 interrupts = <0 22 4>, 761 <0 23 4>, 762 <0 24 4>, 763 <0 25 4>, 764 <0 67 4>, 765 <0 68 4>; 766 clocks = <&osc24M>; 767 }; 768 769 wdt: watchdog@01c20c90 { 770 compatible = "allwinner,sun4i-a10-wdt"; 771 reg = <0x01c20c90 0x10>; 772 }; 773 774 rtc: rtc@01c20d00 { 775 compatible = "allwinner,sun7i-a20-rtc"; 776 reg = <0x01c20d00 0x20>; 777 interrupts = <0 24 4>; 778 }; 779 780 pwm: pwm@01c20e00 { 781 compatible = "allwinner,sun7i-a20-pwm"; 782 reg = <0x01c20e00 0xc>; 783 clocks = <&osc24M>; 784 #pwm-cells = <3>; 785 status = "disabled"; 786 }; 787 788 ir0: ir@01c21800 { 789 compatible = "allwinner,sun4i-a10-ir"; 790 clocks = <&apb0_gates 6>, <&ir0_clk>; 791 clock-names = "apb", "ir"; 792 interrupts = <0 5 4>; 793 reg = <0x01c21800 0x40>; 794 status = "disabled"; 795 }; 796 797 ir1: ir@01c21c00 { 798 compatible = "allwinner,sun4i-a10-ir"; 799 clocks = <&apb0_gates 7>, <&ir1_clk>; 800 clock-names = "apb", "ir"; 801 interrupts = <0 6 4>; 802 reg = <0x01c21c00 0x40>; 803 status = "disabled"; 804 }; 805 806 sid: eeprom@01c23800 { 807 compatible = "allwinner,sun7i-a20-sid"; 808 reg = <0x01c23800 0x200>; 809 }; 810 811 rtp: rtp@01c25000 { 812 compatible = "allwinner,sun4i-a10-ts"; 813 reg = <0x01c25000 0x100>; 814 interrupts = <0 29 4>; 815 }; 816 817 uart0: serial@01c28000 { 818 compatible = "snps,dw-apb-uart"; 819 reg = <0x01c28000 0x400>; 820 interrupts = <0 1 4>; 821 reg-shift = <2>; 822 reg-io-width = <4>; 823 clocks = <&apb1_gates 16>; 824 status = "disabled"; 825 }; 826 827 uart1: serial@01c28400 { 828 compatible = "snps,dw-apb-uart"; 829 reg = <0x01c28400 0x400>; 830 interrupts = <0 2 4>; 831 reg-shift = <2>; 832 reg-io-width = <4>; 833 clocks = <&apb1_gates 17>; 834 status = "disabled"; 835 }; 836 837 uart2: serial@01c28800 { 838 compatible = "snps,dw-apb-uart"; 839 reg = <0x01c28800 0x400>; 840 interrupts = <0 3 4>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 clocks = <&apb1_gates 18>; 844 status = "disabled"; 845 }; 846 847 uart3: serial@01c28c00 { 848 compatible = "snps,dw-apb-uart"; 849 reg = <0x01c28c00 0x400>; 850 interrupts = <0 4 4>; 851 reg-shift = <2>; 852 reg-io-width = <4>; 853 clocks = <&apb1_gates 19>; 854 status = "disabled"; 855 }; 856 857 uart4: serial@01c29000 { 858 compatible = "snps,dw-apb-uart"; 859 reg = <0x01c29000 0x400>; 860 interrupts = <0 17 4>; 861 reg-shift = <2>; 862 reg-io-width = <4>; 863 clocks = <&apb1_gates 20>; 864 status = "disabled"; 865 }; 866 867 uart5: serial@01c29400 { 868 compatible = "snps,dw-apb-uart"; 869 reg = <0x01c29400 0x400>; 870 interrupts = <0 18 4>; 871 reg-shift = <2>; 872 reg-io-width = <4>; 873 clocks = <&apb1_gates 21>; 874 status = "disabled"; 875 }; 876 877 uart6: serial@01c29800 { 878 compatible = "snps,dw-apb-uart"; 879 reg = <0x01c29800 0x400>; 880 interrupts = <0 19 4>; 881 reg-shift = <2>; 882 reg-io-width = <4>; 883 clocks = <&apb1_gates 22>; 884 status = "disabled"; 885 }; 886 887 uart7: serial@01c29c00 { 888 compatible = "snps,dw-apb-uart"; 889 reg = <0x01c29c00 0x400>; 890 interrupts = <0 20 4>; 891 reg-shift = <2>; 892 reg-io-width = <4>; 893 clocks = <&apb1_gates 23>; 894 status = "disabled"; 895 }; 896 897 i2c0: i2c@01c2ac00 { 898 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 899 reg = <0x01c2ac00 0x400>; 900 interrupts = <0 7 4>; 901 clocks = <&apb1_gates 0>; 902 clock-frequency = <100000>; 903 status = "disabled"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 }; 907 908 i2c1: i2c@01c2b000 { 909 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 910 reg = <0x01c2b000 0x400>; 911 interrupts = <0 8 4>; 912 clocks = <&apb1_gates 1>; 913 clock-frequency = <100000>; 914 status = "disabled"; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 }; 918 919 i2c2: i2c@01c2b400 { 920 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 921 reg = <0x01c2b400 0x400>; 922 interrupts = <0 9 4>; 923 clocks = <&apb1_gates 2>; 924 clock-frequency = <100000>; 925 status = "disabled"; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 }; 929 930 i2c3: i2c@01c2b800 { 931 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 932 reg = <0x01c2b800 0x400>; 933 interrupts = <0 88 4>; 934 clocks = <&apb1_gates 3>; 935 clock-frequency = <100000>; 936 status = "disabled"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 }; 940 941 i2c4: i2c@01c2c000 { 942 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; 943 reg = <0x01c2c000 0x400>; 944 interrupts = <0 89 4>; 945 clocks = <&apb1_gates 15>; 946 clock-frequency = <100000>; 947 status = "disabled"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 }; 951 952 gmac: ethernet@01c50000 { 953 compatible = "allwinner,sun7i-a20-gmac"; 954 reg = <0x01c50000 0x10000>; 955 interrupts = <0 85 4>; 956 interrupt-names = "macirq"; 957 clocks = <&ahb_gates 49>, <&gmac_tx_clk>; 958 clock-names = "stmmaceth", "allwinner_gmac_tx"; 959 snps,pbl = <2>; 960 snps,fixed-burst; 961 snps,force_sf_dma_mode; 962 status = "disabled"; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 }; 966 967 hstimer@01c60000 { 968 compatible = "allwinner,sun7i-a20-hstimer"; 969 reg = <0x01c60000 0x1000>; 970 interrupts = <0 81 4>, 971 <0 82 4>, 972 <0 83 4>, 973 <0 84 4>; 974 clocks = <&ahb_gates 28>; 975 }; 976 977 gic: interrupt-controller@01c81000 { 978 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 979 reg = <0x01c81000 0x1000>, 980 <0x01c82000 0x1000>, 981 <0x01c84000 0x2000>, 982 <0x01c86000 0x2000>; 983 interrupt-controller; 984 #interrupt-cells = <3>; 985 interrupts = <1 9 0xf04>; 986 }; 987 }; 988}; 989