1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public 22 * License along with this file; if not, write to the Free 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 * 26 * Or, alternatively, 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use, 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50#include "skeleton.dtsi" 51 52#include <dt-bindings/interrupt-controller/arm-gic.h> 53#include <dt-bindings/thermal/thermal.h> 54 55#include <dt-bindings/pinctrl/sun4i-a10.h> 56 57/ { 58 interrupt-parent = <&gic>; 59 60 aliases { 61 ethernet0 = &gmac; 62 }; 63 64 chosen { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges; 68 69 framebuffer@0 { 70 compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; 71 allwinner,pipeline = "de_be0-lcd0-hdmi"; 72 clocks = <&pll6 0>; 73 status = "disabled"; 74 }; 75 76 framebuffer@1 { 77 compatible = "allwinner,simple-framebuffer", 78 "simple-framebuffer"; 79 allwinner,pipeline = "de_be0-lcd0"; 80 clocks = <&pll6 0>; 81 status = "disabled"; 82 }; 83 }; 84 85 timer { 86 compatible = "arm,armv7-timer"; 87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 91 clock-frequency = <24000000>; 92 arm,cpu-registers-not-fw-configured; 93 }; 94 95 cpus { 96 enable-method = "allwinner,sun6i-a31"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 100 cpu0: cpu@0 { 101 compatible = "arm,cortex-a7"; 102 device_type = "cpu"; 103 reg = <0>; 104 clocks = <&cpu>; 105 clock-latency = <244144>; /* 8 32k periods */ 106 operating-points = < 107 /* kHz uV */ 108 1008000 1200000 109 864000 1200000 110 720000 1100000 111 480000 1000000 112 >; 113 #cooling-cells = <2>; 114 cooling-min-level = <0>; 115 cooling-max-level = <3>; 116 }; 117 118 cpu@1 { 119 compatible = "arm,cortex-a7"; 120 device_type = "cpu"; 121 reg = <1>; 122 }; 123 124 cpu@2 { 125 compatible = "arm,cortex-a7"; 126 device_type = "cpu"; 127 reg = <2>; 128 }; 129 130 cpu@3 { 131 compatible = "arm,cortex-a7"; 132 device_type = "cpu"; 133 reg = <3>; 134 }; 135 }; 136 137 thermal-zones { 138 cpu_thermal { 139 /* milliseconds */ 140 polling-delay-passive = <250>; 141 polling-delay = <1000>; 142 thermal-sensors = <&rtp>; 143 144 cooling-maps { 145 map0 { 146 trip = <&cpu_alert0>; 147 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 148 }; 149 }; 150 151 trips { 152 cpu_alert0: cpu_alert0 { 153 /* milliCelsius */ 154 temperature = <70000>; 155 hysteresis = <2000>; 156 type = "passive"; 157 }; 158 159 cpu_crit: cpu_crit { 160 /* milliCelsius */ 161 temperature = <100000>; 162 hysteresis = <2000>; 163 type = "critical"; 164 }; 165 }; 166 }; 167 }; 168 169 memory { 170 reg = <0x40000000 0x80000000>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 175 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 clocks { 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges; 185 186 osc24M: osc24M { 187 #clock-cells = <0>; 188 compatible = "fixed-clock"; 189 clock-frequency = <24000000>; 190 }; 191 192 osc32k: clk@0 { 193 #clock-cells = <0>; 194 compatible = "fixed-clock"; 195 clock-frequency = <32768>; 196 clock-output-names = "osc32k"; 197 }; 198 199 pll1: clk@01c20000 { 200 #clock-cells = <0>; 201 compatible = "allwinner,sun6i-a31-pll1-clk"; 202 reg = <0x01c20000 0x4>; 203 clocks = <&osc24M>; 204 clock-output-names = "pll1"; 205 }; 206 207 pll6: clk@01c20028 { 208 #clock-cells = <1>; 209 compatible = "allwinner,sun6i-a31-pll6-clk"; 210 reg = <0x01c20028 0x4>; 211 clocks = <&osc24M>; 212 clock-output-names = "pll6", "pll6x2"; 213 }; 214 215 cpu: cpu@01c20050 { 216 #clock-cells = <0>; 217 compatible = "allwinner,sun4i-a10-cpu-clk"; 218 reg = <0x01c20050 0x4>; 219 220 /* 221 * PLL1 is listed twice here. 222 * While it looks suspicious, it's actually documented 223 * that way both in the datasheet and in the code from 224 * Allwinner. 225 */ 226 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 227 clock-output-names = "cpu"; 228 }; 229 230 axi: axi@01c20050 { 231 #clock-cells = <0>; 232 compatible = "allwinner,sun4i-a10-axi-clk"; 233 reg = <0x01c20050 0x4>; 234 clocks = <&cpu>; 235 clock-output-names = "axi"; 236 }; 237 238 ahb1: ahb1@01c20054 { 239 #clock-cells = <0>; 240 compatible = "allwinner,sun6i-a31-ahb1-clk"; 241 reg = <0x01c20054 0x4>; 242 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 243 clock-output-names = "ahb1"; 244 }; 245 246 ahb1_gates: clk@01c20060 { 247 #clock-cells = <1>; 248 compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; 249 reg = <0x01c20060 0x8>; 250 clocks = <&ahb1>; 251 clock-output-names = "ahb1_mipidsi", "ahb1_ss", 252 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", 253 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", 254 "ahb1_nand0", "ahb1_sdram", 255 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", 256 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", 257 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", 258 "ahb1_ehci1", "ahb1_ohci0", 259 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", 260 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", 261 "ahb1_hdmi", "ahb1_de0", "ahb1_de1", 262 "ahb1_fe0", "ahb1_fe1", "ahb1_mp", 263 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", 264 "ahb1_drc0", "ahb1_drc1"; 265 }; 266 267 apb1: apb1@01c20054 { 268 #clock-cells = <0>; 269 compatible = "allwinner,sun4i-a10-apb0-clk"; 270 reg = <0x01c20054 0x4>; 271 clocks = <&ahb1>; 272 clock-output-names = "apb1"; 273 }; 274 275 apb1_gates: clk@01c20068 { 276 #clock-cells = <1>; 277 compatible = "allwinner,sun6i-a31-apb1-gates-clk"; 278 reg = <0x01c20068 0x4>; 279 clocks = <&apb1>; 280 clock-output-names = "apb1_codec", "apb1_digital_mic", 281 "apb1_pio", "apb1_daudio0", 282 "apb1_daudio1"; 283 }; 284 285 apb2: clk@01c20058 { 286 #clock-cells = <0>; 287 compatible = "allwinner,sun4i-a10-apb1-clk"; 288 reg = <0x01c20058 0x4>; 289 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 290 clock-output-names = "apb2"; 291 }; 292 293 apb2_gates: clk@01c2006c { 294 #clock-cells = <1>; 295 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 296 reg = <0x01c2006c 0x4>; 297 clocks = <&apb2>; 298 clock-output-names = "apb2_i2c0", "apb2_i2c1", 299 "apb2_i2c2", "apb2_i2c3", "apb2_uart0", 300 "apb2_uart1", "apb2_uart2", "apb2_uart3", 301 "apb2_uart4", "apb2_uart5"; 302 }; 303 304 mmc0_clk: clk@01c20088 { 305 #clock-cells = <1>; 306 compatible = "allwinner,sun4i-a10-mmc-clk"; 307 reg = <0x01c20088 0x4>; 308 clocks = <&osc24M>, <&pll6 0>; 309 clock-output-names = "mmc0", 310 "mmc0_output", 311 "mmc0_sample"; 312 }; 313 314 mmc1_clk: clk@01c2008c { 315 #clock-cells = <1>; 316 compatible = "allwinner,sun4i-a10-mmc-clk"; 317 reg = <0x01c2008c 0x4>; 318 clocks = <&osc24M>, <&pll6 0>; 319 clock-output-names = "mmc1", 320 "mmc1_output", 321 "mmc1_sample"; 322 }; 323 324 mmc2_clk: clk@01c20090 { 325 #clock-cells = <1>; 326 compatible = "allwinner,sun4i-a10-mmc-clk"; 327 reg = <0x01c20090 0x4>; 328 clocks = <&osc24M>, <&pll6 0>; 329 clock-output-names = "mmc2", 330 "mmc2_output", 331 "mmc2_sample"; 332 }; 333 334 mmc3_clk: clk@01c20094 { 335 #clock-cells = <1>; 336 compatible = "allwinner,sun4i-a10-mmc-clk"; 337 reg = <0x01c20094 0x4>; 338 clocks = <&osc24M>, <&pll6 0>; 339 clock-output-names = "mmc3", 340 "mmc3_output", 341 "mmc3_sample"; 342 }; 343 344 spi0_clk: clk@01c200a0 { 345 #clock-cells = <0>; 346 compatible = "allwinner,sun4i-a10-mod0-clk"; 347 reg = <0x01c200a0 0x4>; 348 clocks = <&osc24M>, <&pll6 0>; 349 clock-output-names = "spi0"; 350 }; 351 352 spi1_clk: clk@01c200a4 { 353 #clock-cells = <0>; 354 compatible = "allwinner,sun4i-a10-mod0-clk"; 355 reg = <0x01c200a4 0x4>; 356 clocks = <&osc24M>, <&pll6 0>; 357 clock-output-names = "spi1"; 358 }; 359 360 spi2_clk: clk@01c200a8 { 361 #clock-cells = <0>; 362 compatible = "allwinner,sun4i-a10-mod0-clk"; 363 reg = <0x01c200a8 0x4>; 364 clocks = <&osc24M>, <&pll6 0>; 365 clock-output-names = "spi2"; 366 }; 367 368 spi3_clk: clk@01c200ac { 369 #clock-cells = <0>; 370 compatible = "allwinner,sun4i-a10-mod0-clk"; 371 reg = <0x01c200ac 0x4>; 372 clocks = <&osc24M>, <&pll6 0>; 373 clock-output-names = "spi3"; 374 }; 375 376 usb_clk: clk@01c200cc { 377 #clock-cells = <1>; 378 #reset-cells = <1>; 379 compatible = "allwinner,sun6i-a31-usb-clk"; 380 reg = <0x01c200cc 0x4>; 381 clocks = <&osc24M>; 382 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", 383 "usb_ohci0", "usb_ohci1", 384 "usb_ohci2"; 385 }; 386 387 /* 388 * The following two are dummy clocks, placeholders used in the gmac_tx 389 * clock. The gmac driver will choose one parent depending on the PHY 390 * interface mode, using clk_set_rate auto-reparenting. 391 * The actual TX clock rate is not controlled by the gmac_tx clock. 392 */ 393 mii_phy_tx_clk: clk@1 { 394 #clock-cells = <0>; 395 compatible = "fixed-clock"; 396 clock-frequency = <25000000>; 397 clock-output-names = "mii_phy_tx"; 398 }; 399 400 gmac_int_tx_clk: clk@2 { 401 #clock-cells = <0>; 402 compatible = "fixed-clock"; 403 clock-frequency = <125000000>; 404 clock-output-names = "gmac_int_tx"; 405 }; 406 407 gmac_tx_clk: clk@01c200d0 { 408 #clock-cells = <0>; 409 compatible = "allwinner,sun7i-a20-gmac-clk"; 410 reg = <0x01c200d0 0x4>; 411 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 412 clock-output-names = "gmac_tx"; 413 }; 414 }; 415 416 soc@01c00000 { 417 compatible = "simple-bus"; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges; 421 422 dma: dma-controller@01c02000 { 423 compatible = "allwinner,sun6i-a31-dma"; 424 reg = <0x01c02000 0x1000>; 425 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&ahb1_gates 6>; 427 resets = <&ahb1_rst 6>; 428 #dma-cells = <1>; 429 430 /* DMA controller requires AHB1 clocked from PLL6 */ 431 assigned-clocks = <&ahb1>; 432 assigned-clock-parents = <&pll6 0>; 433 }; 434 435 mmc0: mmc@01c0f000 { 436 compatible = "allwinner,sun5i-a13-mmc"; 437 reg = <0x01c0f000 0x1000>; 438 clocks = <&ahb1_gates 8>, 439 <&mmc0_clk 0>, 440 <&mmc0_clk 1>, 441 <&mmc0_clk 2>; 442 clock-names = "ahb", 443 "mmc", 444 "output", 445 "sample"; 446 resets = <&ahb1_rst 8>; 447 reset-names = "ahb"; 448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 449 status = "disabled"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 }; 453 454 mmc1: mmc@01c10000 { 455 compatible = "allwinner,sun5i-a13-mmc"; 456 reg = <0x01c10000 0x1000>; 457 clocks = <&ahb1_gates 9>, 458 <&mmc1_clk 0>, 459 <&mmc1_clk 1>, 460 <&mmc1_clk 2>; 461 clock-names = "ahb", 462 "mmc", 463 "output", 464 "sample"; 465 resets = <&ahb1_rst 9>; 466 reset-names = "ahb"; 467 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 468 status = "disabled"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 }; 472 473 mmc2: mmc@01c11000 { 474 compatible = "allwinner,sun5i-a13-mmc"; 475 reg = <0x01c11000 0x1000>; 476 clocks = <&ahb1_gates 10>, 477 <&mmc2_clk 0>, 478 <&mmc2_clk 1>, 479 <&mmc2_clk 2>; 480 clock-names = "ahb", 481 "mmc", 482 "output", 483 "sample"; 484 resets = <&ahb1_rst 10>; 485 reset-names = "ahb"; 486 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 487 status = "disabled"; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 }; 491 492 mmc3: mmc@01c12000 { 493 compatible = "allwinner,sun5i-a13-mmc"; 494 reg = <0x01c12000 0x1000>; 495 clocks = <&ahb1_gates 11>, 496 <&mmc3_clk 0>, 497 <&mmc3_clk 1>, 498 <&mmc3_clk 2>; 499 clock-names = "ahb", 500 "mmc", 501 "output", 502 "sample"; 503 resets = <&ahb1_rst 11>; 504 reset-names = "ahb"; 505 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 506 status = "disabled"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 }; 510 511 usbphy: phy@01c19400 { 512 compatible = "allwinner,sun6i-a31-usb-phy"; 513 reg = <0x01c19400 0x10>, 514 <0x01c1a800 0x4>, 515 <0x01c1b800 0x4>; 516 reg-names = "phy_ctrl", 517 "pmu1", 518 "pmu2"; 519 clocks = <&usb_clk 8>, 520 <&usb_clk 9>, 521 <&usb_clk 10>; 522 clock-names = "usb0_phy", 523 "usb1_phy", 524 "usb2_phy"; 525 resets = <&usb_clk 0>, 526 <&usb_clk 1>, 527 <&usb_clk 2>; 528 reset-names = "usb0_reset", 529 "usb1_reset", 530 "usb2_reset"; 531 status = "disabled"; 532 #phy-cells = <1>; 533 }; 534 535 ehci0: usb@01c1a000 { 536 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 537 reg = <0x01c1a000 0x100>; 538 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&ahb1_gates 26>; 540 resets = <&ahb1_rst 26>; 541 phys = <&usbphy 1>; 542 phy-names = "usb"; 543 status = "disabled"; 544 }; 545 546 ohci0: usb@01c1a400 { 547 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 548 reg = <0x01c1a400 0x100>; 549 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 551 resets = <&ahb1_rst 29>; 552 phys = <&usbphy 1>; 553 phy-names = "usb"; 554 status = "disabled"; 555 }; 556 557 ehci1: usb@01c1b000 { 558 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 559 reg = <0x01c1b000 0x100>; 560 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&ahb1_gates 27>; 562 resets = <&ahb1_rst 27>; 563 phys = <&usbphy 2>; 564 phy-names = "usb"; 565 status = "disabled"; 566 }; 567 568 ohci1: usb@01c1b400 { 569 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 570 reg = <0x01c1b400 0x100>; 571 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&ahb1_gates 30>, <&usb_clk 17>; 573 resets = <&ahb1_rst 30>; 574 phys = <&usbphy 2>; 575 phy-names = "usb"; 576 status = "disabled"; 577 }; 578 579 ohci2: usb@01c1c400 { 580 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 581 reg = <0x01c1c400 0x100>; 582 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&ahb1_gates 31>, <&usb_clk 18>; 584 resets = <&ahb1_rst 31>; 585 status = "disabled"; 586 }; 587 588 pio: pinctrl@01c20800 { 589 compatible = "allwinner,sun6i-a31-pinctrl"; 590 reg = <0x01c20800 0x400>; 591 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&apb1_gates 5>; 596 gpio-controller; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 #size-cells = <0>; 600 #gpio-cells = <3>; 601 602 uart0_pins_a: uart0@0 { 603 allwinner,pins = "PH20", "PH21"; 604 allwinner,function = "uart0"; 605 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 606 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 607 }; 608 609 i2c0_pins_a: i2c0@0 { 610 allwinner,pins = "PH14", "PH15"; 611 allwinner,function = "i2c0"; 612 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 613 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 614 }; 615 616 i2c1_pins_a: i2c1@0 { 617 allwinner,pins = "PH16", "PH17"; 618 allwinner,function = "i2c1"; 619 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 620 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 621 }; 622 623 i2c2_pins_a: i2c2@0 { 624 allwinner,pins = "PH18", "PH19"; 625 allwinner,function = "i2c2"; 626 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 627 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 628 }; 629 630 mmc0_pins_a: mmc0@0 { 631 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 632 allwinner,function = "mmc0"; 633 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 634 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 635 }; 636 637 mmc1_pins_a: mmc1@0 { 638 allwinner,pins = "PG0", "PG1", "PG2", "PG3", 639 "PG4", "PG5"; 640 allwinner,function = "mmc1"; 641 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 642 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 643 }; 644 645 gmac_pins_mii_a: gmac_mii@0 { 646 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 647 "PA8", "PA9", "PA11", 648 "PA12", "PA13", "PA14", "PA19", 649 "PA20", "PA21", "PA22", "PA23", 650 "PA24", "PA26", "PA27"; 651 allwinner,function = "gmac"; 652 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 653 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 654 }; 655 656 gmac_pins_gmii_a: gmac_gmii@0 { 657 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 658 "PA4", "PA5", "PA6", "PA7", 659 "PA8", "PA9", "PA10", "PA11", 660 "PA12", "PA13", "PA14", "PA15", 661 "PA16", "PA17", "PA18", "PA19", 662 "PA20", "PA21", "PA22", "PA23", 663 "PA24", "PA25", "PA26", "PA27"; 664 allwinner,function = "gmac"; 665 /* 666 * data lines in GMII mode run at 125MHz and 667 * might need a higher signal drive strength 668 */ 669 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 670 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 671 }; 672 673 gmac_pins_rgmii_a: gmac_rgmii@0 { 674 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 675 "PA9", "PA10", "PA11", 676 "PA12", "PA13", "PA14", "PA19", 677 "PA20", "PA25", "PA26", "PA27"; 678 allwinner,function = "gmac"; 679 /* 680 * data lines in RGMII mode use DDR mode 681 * and need a higher signal drive strength 682 */ 683 allwinner,drive = <SUN4I_PINCTRL_40_MA>; 684 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 685 }; 686 }; 687 688 ahb1_rst: reset@01c202c0 { 689 #reset-cells = <1>; 690 compatible = "allwinner,sun6i-a31-ahb1-reset"; 691 reg = <0x01c202c0 0xc>; 692 }; 693 694 apb1_rst: reset@01c202d0 { 695 #reset-cells = <1>; 696 compatible = "allwinner,sun6i-a31-clock-reset"; 697 reg = <0x01c202d0 0x4>; 698 }; 699 700 apb2_rst: reset@01c202d8 { 701 #reset-cells = <1>; 702 compatible = "allwinner,sun6i-a31-clock-reset"; 703 reg = <0x01c202d8 0x4>; 704 }; 705 706 timer@01c20c00 { 707 compatible = "allwinner,sun4i-a10-timer"; 708 reg = <0x01c20c00 0xa0>; 709 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&osc24M>; 715 }; 716 717 wdt1: watchdog@01c20ca0 { 718 compatible = "allwinner,sun6i-a31-wdt"; 719 reg = <0x01c20ca0 0x20>; 720 }; 721 722 rtp: rtp@01c25000 { 723 compatible = "allwinner,sun6i-a31-ts"; 724 reg = <0x01c25000 0x100>; 725 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 726 #thermal-sensor-cells = <0>; 727 }; 728 729 uart0: serial@01c28000 { 730 compatible = "snps,dw-apb-uart"; 731 reg = <0x01c28000 0x400>; 732 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 733 reg-shift = <2>; 734 reg-io-width = <4>; 735 clocks = <&apb2_gates 16>; 736 resets = <&apb2_rst 16>; 737 dmas = <&dma 6>, <&dma 6>; 738 dma-names = "rx", "tx"; 739 status = "disabled"; 740 }; 741 742 uart1: serial@01c28400 { 743 compatible = "snps,dw-apb-uart"; 744 reg = <0x01c28400 0x400>; 745 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 746 reg-shift = <2>; 747 reg-io-width = <4>; 748 clocks = <&apb2_gates 17>; 749 resets = <&apb2_rst 17>; 750 dmas = <&dma 7>, <&dma 7>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 uart2: serial@01c28800 { 756 compatible = "snps,dw-apb-uart"; 757 reg = <0x01c28800 0x400>; 758 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 759 reg-shift = <2>; 760 reg-io-width = <4>; 761 clocks = <&apb2_gates 18>; 762 resets = <&apb2_rst 18>; 763 dmas = <&dma 8>, <&dma 8>; 764 dma-names = "rx", "tx"; 765 status = "disabled"; 766 }; 767 768 uart3: serial@01c28c00 { 769 compatible = "snps,dw-apb-uart"; 770 reg = <0x01c28c00 0x400>; 771 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 772 reg-shift = <2>; 773 reg-io-width = <4>; 774 clocks = <&apb2_gates 19>; 775 resets = <&apb2_rst 19>; 776 dmas = <&dma 9>, <&dma 9>; 777 dma-names = "rx", "tx"; 778 status = "disabled"; 779 }; 780 781 uart4: serial@01c29000 { 782 compatible = "snps,dw-apb-uart"; 783 reg = <0x01c29000 0x400>; 784 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 785 reg-shift = <2>; 786 reg-io-width = <4>; 787 clocks = <&apb2_gates 20>; 788 resets = <&apb2_rst 20>; 789 dmas = <&dma 10>, <&dma 10>; 790 dma-names = "rx", "tx"; 791 status = "disabled"; 792 }; 793 794 uart5: serial@01c29400 { 795 compatible = "snps,dw-apb-uart"; 796 reg = <0x01c29400 0x400>; 797 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 798 reg-shift = <2>; 799 reg-io-width = <4>; 800 clocks = <&apb2_gates 21>; 801 resets = <&apb2_rst 21>; 802 dmas = <&dma 22>, <&dma 22>; 803 dma-names = "rx", "tx"; 804 status = "disabled"; 805 }; 806 807 i2c0: i2c@01c2ac00 { 808 compatible = "allwinner,sun6i-a31-i2c"; 809 reg = <0x01c2ac00 0x400>; 810 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&apb2_gates 0>; 812 resets = <&apb2_rst 0>; 813 status = "disabled"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 }; 817 818 i2c1: i2c@01c2b000 { 819 compatible = "allwinner,sun6i-a31-i2c"; 820 reg = <0x01c2b000 0x400>; 821 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&apb2_gates 1>; 823 resets = <&apb2_rst 1>; 824 status = "disabled"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 }; 828 829 i2c2: i2c@01c2b400 { 830 compatible = "allwinner,sun6i-a31-i2c"; 831 reg = <0x01c2b400 0x400>; 832 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&apb2_gates 2>; 834 resets = <&apb2_rst 2>; 835 status = "disabled"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 }; 839 840 i2c3: i2c@01c2b800 { 841 compatible = "allwinner,sun6i-a31-i2c"; 842 reg = <0x01c2b800 0x400>; 843 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&apb2_gates 3>; 845 resets = <&apb2_rst 3>; 846 status = "disabled"; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 }; 850 851 gmac: ethernet@01c30000 { 852 compatible = "allwinner,sun7i-a20-gmac"; 853 reg = <0x01c30000 0x1054>; 854 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "macirq"; 856 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; 857 clock-names = "stmmaceth", "allwinner_gmac_tx"; 858 resets = <&ahb1_rst 17>; 859 reset-names = "stmmaceth"; 860 snps,pbl = <2>; 861 snps,fixed-burst; 862 snps,force_sf_dma_mode; 863 status = "disabled"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 }; 867 868 timer@01c60000 { 869 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; 870 reg = <0x01c60000 0x1000>; 871 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&ahb1_gates 19>; 876 resets = <&ahb1_rst 19>; 877 }; 878 879 spi0: spi@01c68000 { 880 compatible = "allwinner,sun6i-a31-spi"; 881 reg = <0x01c68000 0x1000>; 882 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&ahb1_gates 20>, <&spi0_clk>; 884 clock-names = "ahb", "mod"; 885 dmas = <&dma 23>, <&dma 23>; 886 dma-names = "rx", "tx"; 887 resets = <&ahb1_rst 20>; 888 status = "disabled"; 889 }; 890 891 spi1: spi@01c69000 { 892 compatible = "allwinner,sun6i-a31-spi"; 893 reg = <0x01c69000 0x1000>; 894 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&ahb1_gates 21>, <&spi1_clk>; 896 clock-names = "ahb", "mod"; 897 dmas = <&dma 24>, <&dma 24>; 898 dma-names = "rx", "tx"; 899 resets = <&ahb1_rst 21>; 900 status = "disabled"; 901 }; 902 903 spi2: spi@01c6a000 { 904 compatible = "allwinner,sun6i-a31-spi"; 905 reg = <0x01c6a000 0x1000>; 906 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&ahb1_gates 22>, <&spi2_clk>; 908 clock-names = "ahb", "mod"; 909 dmas = <&dma 25>, <&dma 25>; 910 dma-names = "rx", "tx"; 911 resets = <&ahb1_rst 22>; 912 status = "disabled"; 913 }; 914 915 spi3: spi@01c6b000 { 916 compatible = "allwinner,sun6i-a31-spi"; 917 reg = <0x01c6b000 0x1000>; 918 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&ahb1_gates 23>, <&spi3_clk>; 920 clock-names = "ahb", "mod"; 921 dmas = <&dma 26>, <&dma 26>; 922 dma-names = "rx", "tx"; 923 resets = <&ahb1_rst 23>; 924 status = "disabled"; 925 }; 926 927 gic: interrupt-controller@01c81000 { 928 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 929 reg = <0x01c81000 0x1000>, 930 <0x01c82000 0x1000>, 931 <0x01c84000 0x2000>, 932 <0x01c86000 0x2000>; 933 interrupt-controller; 934 #interrupt-cells = <3>; 935 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 936 }; 937 938 rtc: rtc@01f00000 { 939 compatible = "allwinner,sun6i-a31-rtc"; 940 reg = <0x01f00000 0x54>; 941 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 943 }; 944 945 nmi_intc: interrupt-controller@01f00c0c { 946 compatible = "allwinner,sun6i-a31-sc-nmi"; 947 interrupt-controller; 948 #interrupt-cells = <2>; 949 reg = <0x01f00c0c 0x38>; 950 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 951 }; 952 953 prcm@01f01400 { 954 compatible = "allwinner,sun6i-a31-prcm"; 955 reg = <0x01f01400 0x200>; 956 957 ar100: ar100_clk { 958 compatible = "allwinner,sun6i-a31-ar100-clk"; 959 #clock-cells = <0>; 960 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 961 clock-output-names = "ar100"; 962 }; 963 964 ahb0: ahb0_clk { 965 compatible = "fixed-factor-clock"; 966 #clock-cells = <0>; 967 clock-div = <1>; 968 clock-mult = <1>; 969 clocks = <&ar100>; 970 clock-output-names = "ahb0"; 971 }; 972 973 apb0: apb0_clk { 974 compatible = "allwinner,sun6i-a31-apb0-clk"; 975 #clock-cells = <0>; 976 clocks = <&ahb0>; 977 clock-output-names = "apb0"; 978 }; 979 980 apb0_gates: apb0_gates_clk { 981 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 982 #clock-cells = <1>; 983 clocks = <&apb0>; 984 clock-output-names = "apb0_pio", "apb0_ir", 985 "apb0_timer", "apb0_p2wi", 986 "apb0_uart", "apb0_1wire", 987 "apb0_i2c"; 988 }; 989 990 ir_clk: ir_clk { 991 #clock-cells = <0>; 992 compatible = "allwinner,sun4i-a10-mod0-clk"; 993 clocks = <&osc32k>, <&osc24M>; 994 clock-output-names = "ir"; 995 }; 996 997 apb0_rst: apb0_rst { 998 compatible = "allwinner,sun6i-a31-clock-reset"; 999 #reset-cells = <1>; 1000 }; 1001 }; 1002 1003 cpucfg@01f01c00 { 1004 compatible = "allwinner,sun6i-a31-cpuconfig"; 1005 reg = <0x01f01c00 0x300>; 1006 }; 1007 1008 ir: ir@01f02000 { 1009 compatible = "allwinner,sun5i-a13-ir"; 1010 clocks = <&apb0_gates 1>, <&ir_clk>; 1011 clock-names = "apb", "ir"; 1012 resets = <&apb0_rst 1>; 1013 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1014 reg = <0x01f02000 0x40>; 1015 status = "disabled"; 1016 }; 1017 1018 r_pio: pinctrl@01f02c00 { 1019 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1020 reg = <0x01f02c00 0x400>; 1021 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&apb0_gates 0>; 1024 resets = <&apb0_rst 0>; 1025 gpio-controller; 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 #size-cells = <0>; 1029 #gpio-cells = <3>; 1030 1031 ir_pins_a: ir@0 { 1032 allwinner,pins = "PL4"; 1033 allwinner,function = "s_ir"; 1034 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1035 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1036 }; 1037 1038 p2wi_pins: p2wi { 1039 allwinner,pins = "PL0", "PL1"; 1040 allwinner,function = "s_p2wi"; 1041 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1042 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1043 }; 1044 }; 1045 1046 p2wi: i2c@01f03400 { 1047 compatible = "allwinner,sun6i-a31-p2wi"; 1048 reg = <0x01f03400 0x400>; 1049 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&apb0_gates 3>; 1051 clock-frequency = <100000>; 1052 resets = <&apb0_rst 3>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&p2wi_pins>; 1055 status = "disabled"; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 }; 1059 }; 1060}; 1061