1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/thermal/thermal.h> 49 50#include <dt-bindings/pinctrl/sun4i-a10.h> 51 52/ { 53 interrupt-parent = <&gic>; 54 55 aliases { 56 ethernet0 = &gmac; 57 }; 58 59 chosen { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 64 simplefb_hdmi: framebuffer@0 { 65 compatible = "allwinner,simple-framebuffer", 66 "simple-framebuffer"; 67 allwinner,pipeline = "de_be0-lcd0-hdmi"; 68 clocks = <&pll6 0>; 69 status = "disabled"; 70 }; 71 72 simplefb_lcd: framebuffer@1 { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "de_be0-lcd0"; 76 clocks = <&pll6 0>; 77 status = "disabled"; 78 }; 79 }; 80 81 timer { 82 compatible = "arm,armv7-timer"; 83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 87 clock-frequency = <24000000>; 88 arm,cpu-registers-not-fw-configured; 89 }; 90 91 cpus { 92 enable-method = "allwinner,sun6i-a31"; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 cpu0: cpu@0 { 97 compatible = "arm,cortex-a7"; 98 device_type = "cpu"; 99 reg = <0>; 100 clocks = <&cpu>; 101 clock-latency = <244144>; /* 8 32k periods */ 102 operating-points = < 103 /* kHz uV */ 104 1008000 1200000 105 864000 1200000 106 720000 1100000 107 480000 1000000 108 >; 109 #cooling-cells = <2>; 110 cooling-min-level = <0>; 111 cooling-max-level = <3>; 112 }; 113 114 cpu@1 { 115 compatible = "arm,cortex-a7"; 116 device_type = "cpu"; 117 reg = <1>; 118 }; 119 120 cpu@2 { 121 compatible = "arm,cortex-a7"; 122 device_type = "cpu"; 123 reg = <2>; 124 }; 125 126 cpu@3 { 127 compatible = "arm,cortex-a7"; 128 device_type = "cpu"; 129 reg = <3>; 130 }; 131 }; 132 133 thermal-zones { 134 cpu_thermal { 135 /* milliseconds */ 136 polling-delay-passive = <250>; 137 polling-delay = <1000>; 138 thermal-sensors = <&rtp>; 139 140 cooling-maps { 141 map0 { 142 trip = <&cpu_alert0>; 143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 144 }; 145 }; 146 147 trips { 148 cpu_alert0: cpu_alert0 { 149 /* milliCelsius */ 150 temperature = <70000>; 151 hysteresis = <2000>; 152 type = "passive"; 153 }; 154 155 cpu_crit: cpu_crit { 156 /* milliCelsius */ 157 temperature = <100000>; 158 hysteresis = <2000>; 159 type = "critical"; 160 }; 161 }; 162 }; 163 }; 164 165 memory { 166 reg = <0x40000000 0x80000000>; 167 }; 168 169 pmu { 170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 clocks { 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges; 181 182 osc24M: osc24M { 183 #clock-cells = <0>; 184 compatible = "fixed-clock"; 185 clock-frequency = <24000000>; 186 }; 187 188 osc32k: clk@0 { 189 #clock-cells = <0>; 190 compatible = "fixed-clock"; 191 clock-frequency = <32768>; 192 clock-output-names = "osc32k"; 193 }; 194 195 pll1: clk@01c20000 { 196 #clock-cells = <0>; 197 compatible = "allwinner,sun6i-a31-pll1-clk"; 198 reg = <0x01c20000 0x4>; 199 clocks = <&osc24M>; 200 clock-output-names = "pll1"; 201 }; 202 203 pll6: clk@01c20028 { 204 #clock-cells = <1>; 205 compatible = "allwinner,sun6i-a31-pll6-clk"; 206 reg = <0x01c20028 0x4>; 207 clocks = <&osc24M>; 208 clock-output-names = "pll6", "pll6x2"; 209 }; 210 211 cpu: cpu@01c20050 { 212 #clock-cells = <0>; 213 compatible = "allwinner,sun4i-a10-cpu-clk"; 214 reg = <0x01c20050 0x4>; 215 216 /* 217 * PLL1 is listed twice here. 218 * While it looks suspicious, it's actually documented 219 * that way both in the datasheet and in the code from 220 * Allwinner. 221 */ 222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 223 clock-output-names = "cpu"; 224 }; 225 226 axi: axi@01c20050 { 227 #clock-cells = <0>; 228 compatible = "allwinner,sun4i-a10-axi-clk"; 229 reg = <0x01c20050 0x4>; 230 clocks = <&cpu>; 231 clock-output-names = "axi"; 232 }; 233 234 ahb1: ahb1@01c20054 { 235 #clock-cells = <0>; 236 compatible = "allwinner,sun6i-a31-ahb1-clk"; 237 reg = <0x01c20054 0x4>; 238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 239 clock-output-names = "ahb1"; 240 241 /* 242 * Clock AHB1 from PLL6, instead of CPU/AXI which 243 * has rate changes due to cpufreq. Also the DMA 244 * controller requires AHB1 clocked from PLL6. 245 */ 246 assigned-clocks = <&ahb1>; 247 assigned-clock-parents = <&pll6 0>; 248 }; 249 250 ahb1_gates: clk@01c20060 { 251 #clock-cells = <1>; 252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; 253 reg = <0x01c20060 0x8>; 254 clocks = <&ahb1>; 255 clock-indices = <1>, <5>, 256 <6>, <8>, <9>, 257 <10>, <11>, <12>, 258 <13>, <14>, 259 <17>, <18>, <19>, 260 <20>, <21>, <22>, 261 <23>, <24>, <26>, 262 <27>, <29>, 263 <30>, <31>, <32>, 264 <36>, <37>, <40>, 265 <43>, <44>, <45>, 266 <46>, <47>, <50>, 267 <52>, <55>, <56>, 268 <57>, <58>; 269 clock-output-names = "ahb1_mipidsi", "ahb1_ss", 270 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1", 271 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1", 272 "ahb1_nand0", "ahb1_sdram", 273 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer", 274 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2", 275 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0", 276 "ahb1_ehci1", "ahb1_ohci0", 277 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve", 278 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi", 279 "ahb1_hdmi", "ahb1_de0", "ahb1_de1", 280 "ahb1_fe0", "ahb1_fe1", "ahb1_mp", 281 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1", 282 "ahb1_drc0", "ahb1_drc1"; 283 }; 284 285 apb1: apb1@01c20054 { 286 #clock-cells = <0>; 287 compatible = "allwinner,sun4i-a10-apb0-clk"; 288 reg = <0x01c20054 0x4>; 289 clocks = <&ahb1>; 290 clock-output-names = "apb1"; 291 }; 292 293 apb1_gates: clk@01c20068 { 294 #clock-cells = <1>; 295 compatible = "allwinner,sun6i-a31-apb1-gates-clk"; 296 reg = <0x01c20068 0x4>; 297 clocks = <&apb1>; 298 clock-indices = <0>, <4>, 299 <5>, <12>, 300 <13>; 301 clock-output-names = "apb1_codec", "apb1_digital_mic", 302 "apb1_pio", "apb1_daudio0", 303 "apb1_daudio1"; 304 }; 305 306 apb2: clk@01c20058 { 307 #clock-cells = <0>; 308 compatible = "allwinner,sun4i-a10-apb1-clk"; 309 reg = <0x01c20058 0x4>; 310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 311 clock-output-names = "apb2"; 312 }; 313 314 apb2_gates: clk@01c2006c { 315 #clock-cells = <1>; 316 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 317 reg = <0x01c2006c 0x4>; 318 clocks = <&apb2>; 319 clock-indices = <0>, <1>, 320 <2>, <3>, <16>, 321 <17>, <18>, <19>, 322 <20>, <21>; 323 clock-output-names = "apb2_i2c0", "apb2_i2c1", 324 "apb2_i2c2", "apb2_i2c3", 325 "apb2_uart0", "apb2_uart1", 326 "apb2_uart2", "apb2_uart3", 327 "apb2_uart4", "apb2_uart5"; 328 }; 329 330 mmc0_clk: clk@01c20088 { 331 #clock-cells = <1>; 332 compatible = "allwinner,sun4i-a10-mmc-clk"; 333 reg = <0x01c20088 0x4>; 334 clocks = <&osc24M>, <&pll6 0>; 335 clock-output-names = "mmc0", 336 "mmc0_output", 337 "mmc0_sample"; 338 }; 339 340 mmc1_clk: clk@01c2008c { 341 #clock-cells = <1>; 342 compatible = "allwinner,sun4i-a10-mmc-clk"; 343 reg = <0x01c2008c 0x4>; 344 clocks = <&osc24M>, <&pll6 0>; 345 clock-output-names = "mmc1", 346 "mmc1_output", 347 "mmc1_sample"; 348 }; 349 350 mmc2_clk: clk@01c20090 { 351 #clock-cells = <1>; 352 compatible = "allwinner,sun4i-a10-mmc-clk"; 353 reg = <0x01c20090 0x4>; 354 clocks = <&osc24M>, <&pll6 0>; 355 clock-output-names = "mmc2", 356 "mmc2_output", 357 "mmc2_sample"; 358 }; 359 360 mmc3_clk: clk@01c20094 { 361 #clock-cells = <1>; 362 compatible = "allwinner,sun4i-a10-mmc-clk"; 363 reg = <0x01c20094 0x4>; 364 clocks = <&osc24M>, <&pll6 0>; 365 clock-output-names = "mmc3", 366 "mmc3_output", 367 "mmc3_sample"; 368 }; 369 370 ss_clk: clk@01c2009c { 371 #clock-cells = <0>; 372 compatible = "allwinner,sun4i-a10-mod0-clk"; 373 reg = <0x01c2009c 0x4>; 374 clocks = <&osc24M>, <&pll6 0>; 375 clock-output-names = "ss"; 376 }; 377 378 spi0_clk: clk@01c200a0 { 379 #clock-cells = <0>; 380 compatible = "allwinner,sun4i-a10-mod0-clk"; 381 reg = <0x01c200a0 0x4>; 382 clocks = <&osc24M>, <&pll6 0>; 383 clock-output-names = "spi0"; 384 }; 385 386 spi1_clk: clk@01c200a4 { 387 #clock-cells = <0>; 388 compatible = "allwinner,sun4i-a10-mod0-clk"; 389 reg = <0x01c200a4 0x4>; 390 clocks = <&osc24M>, <&pll6 0>; 391 clock-output-names = "spi1"; 392 }; 393 394 spi2_clk: clk@01c200a8 { 395 #clock-cells = <0>; 396 compatible = "allwinner,sun4i-a10-mod0-clk"; 397 reg = <0x01c200a8 0x4>; 398 clocks = <&osc24M>, <&pll6 0>; 399 clock-output-names = "spi2"; 400 }; 401 402 spi3_clk: clk@01c200ac { 403 #clock-cells = <0>; 404 compatible = "allwinner,sun4i-a10-mod0-clk"; 405 reg = <0x01c200ac 0x4>; 406 clocks = <&osc24M>, <&pll6 0>; 407 clock-output-names = "spi3"; 408 }; 409 410 usb_clk: clk@01c200cc { 411 #clock-cells = <1>; 412 #reset-cells = <1>; 413 compatible = "allwinner,sun6i-a31-usb-clk"; 414 reg = <0x01c200cc 0x4>; 415 clocks = <&osc24M>; 416 clock-indices = <8>, <9>, <10>, 417 <16>, <17>, 418 <18>; 419 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", 420 "usb_ohci0", "usb_ohci1", 421 "usb_ohci2"; 422 }; 423 424 /* 425 * The following two are dummy clocks, placeholders 426 * used in the gmac_tx clock. The gmac driver will 427 * choose one parent depending on the PHY interface 428 * mode, using clk_set_rate auto-reparenting. 429 * 430 * The actual TX clock rate is not controlled by the 431 * gmac_tx clock. 432 */ 433 mii_phy_tx_clk: clk@1 { 434 #clock-cells = <0>; 435 compatible = "fixed-clock"; 436 clock-frequency = <25000000>; 437 clock-output-names = "mii_phy_tx"; 438 }; 439 440 gmac_int_tx_clk: clk@2 { 441 #clock-cells = <0>; 442 compatible = "fixed-clock"; 443 clock-frequency = <125000000>; 444 clock-output-names = "gmac_int_tx"; 445 }; 446 447 gmac_tx_clk: clk@01c200d0 { 448 #clock-cells = <0>; 449 compatible = "allwinner,sun7i-a20-gmac-clk"; 450 reg = <0x01c200d0 0x4>; 451 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 452 clock-output-names = "gmac_tx"; 453 }; 454 }; 455 456 soc@01c00000 { 457 compatible = "simple-bus"; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges; 461 462 dma: dma-controller@01c02000 { 463 compatible = "allwinner,sun6i-a31-dma"; 464 reg = <0x01c02000 0x1000>; 465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&ahb1_gates 6>; 467 resets = <&ahb1_rst 6>; 468 #dma-cells = <1>; 469 }; 470 471 mmc0: mmc@01c0f000 { 472 compatible = "allwinner,sun7i-a20-mmc", 473 "allwinner,sun5i-a13-mmc"; 474 reg = <0x01c0f000 0x1000>; 475 clocks = <&ahb1_gates 8>, 476 <&mmc0_clk 0>, 477 <&mmc0_clk 1>, 478 <&mmc0_clk 2>; 479 clock-names = "ahb", 480 "mmc", 481 "output", 482 "sample"; 483 resets = <&ahb1_rst 8>; 484 reset-names = "ahb"; 485 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 486 status = "disabled"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 491 mmc1: mmc@01c10000 { 492 compatible = "allwinner,sun7i-a20-mmc", 493 "allwinner,sun5i-a13-mmc"; 494 reg = <0x01c10000 0x1000>; 495 clocks = <&ahb1_gates 9>, 496 <&mmc1_clk 0>, 497 <&mmc1_clk 1>, 498 <&mmc1_clk 2>; 499 clock-names = "ahb", 500 "mmc", 501 "output", 502 "sample"; 503 resets = <&ahb1_rst 9>; 504 reset-names = "ahb"; 505 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 506 status = "disabled"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 }; 510 511 mmc2: mmc@01c11000 { 512 compatible = "allwinner,sun7i-a20-mmc", 513 "allwinner,sun5i-a13-mmc"; 514 reg = <0x01c11000 0x1000>; 515 clocks = <&ahb1_gates 10>, 516 <&mmc2_clk 0>, 517 <&mmc2_clk 1>, 518 <&mmc2_clk 2>; 519 clock-names = "ahb", 520 "mmc", 521 "output", 522 "sample"; 523 resets = <&ahb1_rst 10>; 524 reset-names = "ahb"; 525 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 526 status = "disabled"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 }; 530 531 mmc3: mmc@01c12000 { 532 compatible = "allwinner,sun7i-a20-mmc", 533 "allwinner,sun5i-a13-mmc"; 534 reg = <0x01c12000 0x1000>; 535 clocks = <&ahb1_gates 11>, 536 <&mmc3_clk 0>, 537 <&mmc3_clk 1>, 538 <&mmc3_clk 2>; 539 clock-names = "ahb", 540 "mmc", 541 "output", 542 "sample"; 543 resets = <&ahb1_rst 11>; 544 reset-names = "ahb"; 545 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 546 status = "disabled"; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 }; 550 551 usb_otg: usb@01c19000 { 552 compatible = "allwinner,sun6i-a31-musb"; 553 reg = <0x01c19000 0x0400>; 554 clocks = <&ahb1_gates 24>; 555 resets = <&ahb1_rst 24>; 556 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "mc"; 558 phys = <&usbphy 0>; 559 phy-names = "usb"; 560 extcon = <&usbphy 0>; 561 status = "disabled"; 562 }; 563 564 usbphy: phy@01c19400 { 565 compatible = "allwinner,sun6i-a31-usb-phy"; 566 reg = <0x01c19400 0x10>, 567 <0x01c1a800 0x4>, 568 <0x01c1b800 0x4>; 569 reg-names = "phy_ctrl", 570 "pmu1", 571 "pmu2"; 572 clocks = <&usb_clk 8>, 573 <&usb_clk 9>, 574 <&usb_clk 10>; 575 clock-names = "usb0_phy", 576 "usb1_phy", 577 "usb2_phy"; 578 resets = <&usb_clk 0>, 579 <&usb_clk 1>, 580 <&usb_clk 2>; 581 reset-names = "usb0_reset", 582 "usb1_reset", 583 "usb2_reset"; 584 status = "disabled"; 585 #phy-cells = <1>; 586 }; 587 588 ehci0: usb@01c1a000 { 589 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 590 reg = <0x01c1a000 0x100>; 591 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&ahb1_gates 26>; 593 resets = <&ahb1_rst 26>; 594 phys = <&usbphy 1>; 595 phy-names = "usb"; 596 status = "disabled"; 597 }; 598 599 ohci0: usb@01c1a400 { 600 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 601 reg = <0x01c1a400 0x100>; 602 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 604 resets = <&ahb1_rst 29>; 605 phys = <&usbphy 1>; 606 phy-names = "usb"; 607 status = "disabled"; 608 }; 609 610 ehci1: usb@01c1b000 { 611 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 612 reg = <0x01c1b000 0x100>; 613 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&ahb1_gates 27>; 615 resets = <&ahb1_rst 27>; 616 phys = <&usbphy 2>; 617 phy-names = "usb"; 618 status = "disabled"; 619 }; 620 621 ohci1: usb@01c1b400 { 622 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 623 reg = <0x01c1b400 0x100>; 624 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&ahb1_gates 30>, <&usb_clk 17>; 626 resets = <&ahb1_rst 30>; 627 phys = <&usbphy 2>; 628 phy-names = "usb"; 629 status = "disabled"; 630 }; 631 632 ohci2: usb@01c1c400 { 633 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 634 reg = <0x01c1c400 0x100>; 635 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&ahb1_gates 31>, <&usb_clk 18>; 637 resets = <&ahb1_rst 31>; 638 status = "disabled"; 639 }; 640 641 pio: pinctrl@01c20800 { 642 compatible = "allwinner,sun6i-a31-pinctrl"; 643 reg = <0x01c20800 0x400>; 644 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&apb1_gates 5>; 649 gpio-controller; 650 interrupt-controller; 651 #interrupt-cells = <3>; 652 #gpio-cells = <3>; 653 654 uart0_pins_a: uart0@0 { 655 allwinner,pins = "PH20", "PH21"; 656 allwinner,function = "uart0"; 657 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 658 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 659 }; 660 661 i2c0_pins_a: i2c0@0 { 662 allwinner,pins = "PH14", "PH15"; 663 allwinner,function = "i2c0"; 664 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 665 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 666 }; 667 668 i2c1_pins_a: i2c1@0 { 669 allwinner,pins = "PH16", "PH17"; 670 allwinner,function = "i2c1"; 671 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 672 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 673 }; 674 675 i2c2_pins_a: i2c2@0 { 676 allwinner,pins = "PH18", "PH19"; 677 allwinner,function = "i2c2"; 678 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 679 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 680 }; 681 682 mmc0_pins_a: mmc0@0 { 683 allwinner,pins = "PF0", "PF1", "PF2", 684 "PF3", "PF4", "PF5"; 685 allwinner,function = "mmc0"; 686 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 687 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 688 }; 689 690 mmc1_pins_a: mmc1@0 { 691 allwinner,pins = "PG0", "PG1", "PG2", "PG3", 692 "PG4", "PG5"; 693 allwinner,function = "mmc1"; 694 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 696 }; 697 698 mmc2_pins_a: mmc2@0 { 699 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 700 "PC10", "PC11"; 701 allwinner,function = "mmc2"; 702 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 703 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 704 }; 705 706 mmc2_8bit_emmc_pins: mmc2@1 { 707 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 708 "PC10", "PC11", "PC12", 709 "PC13", "PC14", "PC15", 710 "PC24"; 711 allwinner,function = "mmc2"; 712 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 713 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 714 }; 715 716 mmc3_8bit_emmc_pins: mmc3@1 { 717 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 718 "PC10", "PC11", "PC12", 719 "PC13", "PC14", "PC15", 720 "PC24"; 721 allwinner,function = "mmc3"; 722 allwinner,drive = <SUN4I_PINCTRL_40_MA>; 723 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 724 }; 725 726 gmac_pins_mii_a: gmac_mii@0 { 727 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 728 "PA8", "PA9", "PA11", 729 "PA12", "PA13", "PA14", "PA19", 730 "PA20", "PA21", "PA22", "PA23", 731 "PA24", "PA26", "PA27"; 732 allwinner,function = "gmac"; 733 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 734 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 735 }; 736 737 gmac_pins_gmii_a: gmac_gmii@0 { 738 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 739 "PA4", "PA5", "PA6", "PA7", 740 "PA8", "PA9", "PA10", "PA11", 741 "PA12", "PA13", "PA14", "PA15", 742 "PA16", "PA17", "PA18", "PA19", 743 "PA20", "PA21", "PA22", "PA23", 744 "PA24", "PA25", "PA26", "PA27"; 745 allwinner,function = "gmac"; 746 /* 747 * data lines in GMII mode run at 125MHz and 748 * might need a higher signal drive strength 749 */ 750 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 751 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 752 }; 753 754 gmac_pins_rgmii_a: gmac_rgmii@0 { 755 allwinner,pins = "PA0", "PA1", "PA2", "PA3", 756 "PA9", "PA10", "PA11", 757 "PA12", "PA13", "PA14", "PA19", 758 "PA20", "PA25", "PA26", "PA27"; 759 allwinner,function = "gmac"; 760 /* 761 * data lines in RGMII mode use DDR mode 762 * and need a higher signal drive strength 763 */ 764 allwinner,drive = <SUN4I_PINCTRL_40_MA>; 765 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 766 }; 767 }; 768 769 ahb1_rst: reset@01c202c0 { 770 #reset-cells = <1>; 771 compatible = "allwinner,sun6i-a31-ahb1-reset"; 772 reg = <0x01c202c0 0xc>; 773 }; 774 775 apb1_rst: reset@01c202d0 { 776 #reset-cells = <1>; 777 compatible = "allwinner,sun6i-a31-clock-reset"; 778 reg = <0x01c202d0 0x4>; 779 }; 780 781 apb2_rst: reset@01c202d8 { 782 #reset-cells = <1>; 783 compatible = "allwinner,sun6i-a31-clock-reset"; 784 reg = <0x01c202d8 0x4>; 785 }; 786 787 timer@01c20c00 { 788 compatible = "allwinner,sun4i-a10-timer"; 789 reg = <0x01c20c00 0xa0>; 790 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&osc24M>; 796 }; 797 798 wdt1: watchdog@01c20ca0 { 799 compatible = "allwinner,sun6i-a31-wdt"; 800 reg = <0x01c20ca0 0x20>; 801 }; 802 803 lradc: lradc@01c22800 { 804 compatible = "allwinner,sun4i-a10-lradc-keys"; 805 reg = <0x01c22800 0x100>; 806 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 807 status = "disabled"; 808 }; 809 810 rtp: rtp@01c25000 { 811 compatible = "allwinner,sun6i-a31-ts"; 812 reg = <0x01c25000 0x100>; 813 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 814 #thermal-sensor-cells = <0>; 815 }; 816 817 uart0: serial@01c28000 { 818 compatible = "snps,dw-apb-uart"; 819 reg = <0x01c28000 0x400>; 820 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 821 reg-shift = <2>; 822 reg-io-width = <4>; 823 clocks = <&apb2_gates 16>; 824 resets = <&apb2_rst 16>; 825 dmas = <&dma 6>, <&dma 6>; 826 dma-names = "rx", "tx"; 827 status = "disabled"; 828 }; 829 830 uart1: serial@01c28400 { 831 compatible = "snps,dw-apb-uart"; 832 reg = <0x01c28400 0x400>; 833 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 834 reg-shift = <2>; 835 reg-io-width = <4>; 836 clocks = <&apb2_gates 17>; 837 resets = <&apb2_rst 17>; 838 dmas = <&dma 7>, <&dma 7>; 839 dma-names = "rx", "tx"; 840 status = "disabled"; 841 }; 842 843 uart2: serial@01c28800 { 844 compatible = "snps,dw-apb-uart"; 845 reg = <0x01c28800 0x400>; 846 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 847 reg-shift = <2>; 848 reg-io-width = <4>; 849 clocks = <&apb2_gates 18>; 850 resets = <&apb2_rst 18>; 851 dmas = <&dma 8>, <&dma 8>; 852 dma-names = "rx", "tx"; 853 status = "disabled"; 854 }; 855 856 uart3: serial@01c28c00 { 857 compatible = "snps,dw-apb-uart"; 858 reg = <0x01c28c00 0x400>; 859 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 860 reg-shift = <2>; 861 reg-io-width = <4>; 862 clocks = <&apb2_gates 19>; 863 resets = <&apb2_rst 19>; 864 dmas = <&dma 9>, <&dma 9>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 uart4: serial@01c29000 { 870 compatible = "snps,dw-apb-uart"; 871 reg = <0x01c29000 0x400>; 872 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 873 reg-shift = <2>; 874 reg-io-width = <4>; 875 clocks = <&apb2_gates 20>; 876 resets = <&apb2_rst 20>; 877 dmas = <&dma 10>, <&dma 10>; 878 dma-names = "rx", "tx"; 879 status = "disabled"; 880 }; 881 882 uart5: serial@01c29400 { 883 compatible = "snps,dw-apb-uart"; 884 reg = <0x01c29400 0x400>; 885 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 886 reg-shift = <2>; 887 reg-io-width = <4>; 888 clocks = <&apb2_gates 21>; 889 resets = <&apb2_rst 21>; 890 dmas = <&dma 22>, <&dma 22>; 891 dma-names = "rx", "tx"; 892 status = "disabled"; 893 }; 894 895 i2c0: i2c@01c2ac00 { 896 compatible = "allwinner,sun6i-a31-i2c"; 897 reg = <0x01c2ac00 0x400>; 898 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&apb2_gates 0>; 900 resets = <&apb2_rst 0>; 901 status = "disabled"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 }; 905 906 i2c1: i2c@01c2b000 { 907 compatible = "allwinner,sun6i-a31-i2c"; 908 reg = <0x01c2b000 0x400>; 909 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&apb2_gates 1>; 911 resets = <&apb2_rst 1>; 912 status = "disabled"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 }; 916 917 i2c2: i2c@01c2b400 { 918 compatible = "allwinner,sun6i-a31-i2c"; 919 reg = <0x01c2b400 0x400>; 920 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&apb2_gates 2>; 922 resets = <&apb2_rst 2>; 923 status = "disabled"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 }; 927 928 i2c3: i2c@01c2b800 { 929 compatible = "allwinner,sun6i-a31-i2c"; 930 reg = <0x01c2b800 0x400>; 931 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&apb2_gates 3>; 933 resets = <&apb2_rst 3>; 934 status = "disabled"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 }; 938 939 gmac: ethernet@01c30000 { 940 compatible = "allwinner,sun7i-a20-gmac"; 941 reg = <0x01c30000 0x1054>; 942 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "macirq"; 944 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; 945 clock-names = "stmmaceth", "allwinner_gmac_tx"; 946 resets = <&ahb1_rst 17>; 947 reset-names = "stmmaceth"; 948 snps,pbl = <2>; 949 snps,fixed-burst; 950 snps,force_sf_dma_mode; 951 status = "disabled"; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 }; 955 956 crypto: crypto-engine@01c15000 { 957 compatible = "allwinner,sun4i-a10-crypto"; 958 reg = <0x01c15000 0x1000>; 959 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&ahb1_gates 5>, <&ss_clk>; 961 clock-names = "ahb", "mod"; 962 resets = <&ahb1_rst 5>; 963 reset-names = "ahb"; 964 }; 965 966 timer@01c60000 { 967 compatible = "allwinner,sun6i-a31-hstimer", 968 "allwinner,sun7i-a20-hstimer"; 969 reg = <0x01c60000 0x1000>; 970 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&ahb1_gates 19>; 975 resets = <&ahb1_rst 19>; 976 }; 977 978 spi0: spi@01c68000 { 979 compatible = "allwinner,sun6i-a31-spi"; 980 reg = <0x01c68000 0x1000>; 981 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&ahb1_gates 20>, <&spi0_clk>; 983 clock-names = "ahb", "mod"; 984 dmas = <&dma 23>, <&dma 23>; 985 dma-names = "rx", "tx"; 986 resets = <&ahb1_rst 20>; 987 status = "disabled"; 988 }; 989 990 spi1: spi@01c69000 { 991 compatible = "allwinner,sun6i-a31-spi"; 992 reg = <0x01c69000 0x1000>; 993 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&ahb1_gates 21>, <&spi1_clk>; 995 clock-names = "ahb", "mod"; 996 dmas = <&dma 24>, <&dma 24>; 997 dma-names = "rx", "tx"; 998 resets = <&ahb1_rst 21>; 999 status = "disabled"; 1000 }; 1001 1002 spi2: spi@01c6a000 { 1003 compatible = "allwinner,sun6i-a31-spi"; 1004 reg = <0x01c6a000 0x1000>; 1005 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&ahb1_gates 22>, <&spi2_clk>; 1007 clock-names = "ahb", "mod"; 1008 dmas = <&dma 25>, <&dma 25>; 1009 dma-names = "rx", "tx"; 1010 resets = <&ahb1_rst 22>; 1011 status = "disabled"; 1012 }; 1013 1014 spi3: spi@01c6b000 { 1015 compatible = "allwinner,sun6i-a31-spi"; 1016 reg = <0x01c6b000 0x1000>; 1017 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&ahb1_gates 23>, <&spi3_clk>; 1019 clock-names = "ahb", "mod"; 1020 dmas = <&dma 26>, <&dma 26>; 1021 dma-names = "rx", "tx"; 1022 resets = <&ahb1_rst 23>; 1023 status = "disabled"; 1024 }; 1025 1026 gic: interrupt-controller@01c81000 { 1027 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1028 reg = <0x01c81000 0x1000>, 1029 <0x01c82000 0x1000>, 1030 <0x01c84000 0x2000>, 1031 <0x01c86000 0x2000>; 1032 interrupt-controller; 1033 #interrupt-cells = <3>; 1034 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1035 }; 1036 1037 rtc: rtc@01f00000 { 1038 compatible = "allwinner,sun6i-a31-rtc"; 1039 reg = <0x01f00000 0x54>; 1040 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1042 }; 1043 1044 nmi_intc: interrupt-controller@01f00c0c { 1045 compatible = "allwinner,sun6i-a31-sc-nmi"; 1046 interrupt-controller; 1047 #interrupt-cells = <2>; 1048 reg = <0x01f00c0c 0x38>; 1049 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1050 }; 1051 1052 prcm@01f01400 { 1053 compatible = "allwinner,sun6i-a31-prcm"; 1054 reg = <0x01f01400 0x200>; 1055 1056 ar100: ar100_clk { 1057 compatible = "allwinner,sun6i-a31-ar100-clk"; 1058 #clock-cells = <0>; 1059 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, 1060 <&pll6 0>; 1061 clock-output-names = "ar100"; 1062 }; 1063 1064 ahb0: ahb0_clk { 1065 compatible = "fixed-factor-clock"; 1066 #clock-cells = <0>; 1067 clock-div = <1>; 1068 clock-mult = <1>; 1069 clocks = <&ar100>; 1070 clock-output-names = "ahb0"; 1071 }; 1072 1073 apb0: apb0_clk { 1074 compatible = "allwinner,sun6i-a31-apb0-clk"; 1075 #clock-cells = <0>; 1076 clocks = <&ahb0>; 1077 clock-output-names = "apb0"; 1078 }; 1079 1080 apb0_gates: apb0_gates_clk { 1081 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 1082 #clock-cells = <1>; 1083 clocks = <&apb0>; 1084 clock-output-names = "apb0_pio", "apb0_ir", 1085 "apb0_timer", "apb0_p2wi", 1086 "apb0_uart", "apb0_1wire", 1087 "apb0_i2c"; 1088 }; 1089 1090 ir_clk: ir_clk { 1091 #clock-cells = <0>; 1092 compatible = "allwinner,sun4i-a10-mod0-clk"; 1093 clocks = <&osc32k>, <&osc24M>; 1094 clock-output-names = "ir"; 1095 }; 1096 1097 apb0_rst: apb0_rst { 1098 compatible = "allwinner,sun6i-a31-clock-reset"; 1099 #reset-cells = <1>; 1100 }; 1101 }; 1102 1103 cpucfg@01f01c00 { 1104 compatible = "allwinner,sun6i-a31-cpuconfig"; 1105 reg = <0x01f01c00 0x300>; 1106 }; 1107 1108 ir: ir@01f02000 { 1109 compatible = "allwinner,sun5i-a13-ir"; 1110 clocks = <&apb0_gates 1>, <&ir_clk>; 1111 clock-names = "apb", "ir"; 1112 resets = <&apb0_rst 1>; 1113 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1114 reg = <0x01f02000 0x40>; 1115 status = "disabled"; 1116 }; 1117 1118 r_pio: pinctrl@01f02c00 { 1119 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1120 reg = <0x01f02c00 0x400>; 1121 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&apb0_gates 0>; 1124 resets = <&apb0_rst 0>; 1125 gpio-controller; 1126 interrupt-controller; 1127 #interrupt-cells = <3>; 1128 #size-cells = <0>; 1129 #gpio-cells = <3>; 1130 1131 ir_pins_a: ir@0 { 1132 allwinner,pins = "PL4"; 1133 allwinner,function = "s_ir"; 1134 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1135 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1136 }; 1137 1138 p2wi_pins: p2wi { 1139 allwinner,pins = "PL0", "PL1"; 1140 allwinner,function = "s_p2wi"; 1141 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 1142 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 1143 }; 1144 }; 1145 1146 p2wi: i2c@01f03400 { 1147 compatible = "allwinner,sun6i-a31-p2wi"; 1148 reg = <0x01f03400 0x400>; 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&apb0_gates 3>; 1151 clock-frequency = <100000>; 1152 resets = <&apb0_rst 3>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&p2wi_pins>; 1155 status = "disabled"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 }; 1159 }; 1160}; 1161