1/* 2 * Copyright 2012-2015 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/clock/sun5i-ccu.h> 48#include <dt-bindings/dma/sun4i-a10.h> 49#include <dt-bindings/reset/sun5i-ccu.h> 50 51/ { 52 interrupt-parent = <&intc>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a8"; 61 reg = <0x0>; 62 clocks = <&ccu CLK_CPU>; 63 }; 64 }; 65 66 chosen { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 framebuffer@0 { 72 compatible = "allwinner,simple-framebuffer", 73 "simple-framebuffer"; 74 allwinner,pipeline = "de_be0-lcd0"; 75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; 77 status = "disabled"; 78 }; 79 80 framebuffer@1 { 81 compatible = "allwinner,simple-framebuffer", 82 "simple-framebuffer"; 83 allwinner,pipeline = "de_be0-lcd0-tve0"; 84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, 85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; 87 status = "disabled"; 88 }; 89 }; 90 91 clocks { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 96 osc24M: clk@1c20050 { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 clock-output-names = "osc24M"; 101 }; 102 103 osc32k: clk@0 { 104 #clock-cells = <0>; 105 compatible = "fixed-clock"; 106 clock-frequency = <32768>; 107 clock-output-names = "osc32k"; 108 }; 109 }; 110 111 soc@1c00000 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges; 116 117 sram-controller@1c00000 { 118 compatible = "allwinner,sun4i-a10-sram-controller"; 119 reg = <0x01c00000 0x30>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 sram_a: sram@0 { 125 compatible = "mmio-sram"; 126 reg = <0x00000000 0xc000>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0 0x00000000 0xc000>; 130 }; 131 132 emac_sram: sram-section@8000 { 133 compatible = "allwinner,sun4i-a10-sram-a3-a4"; 134 reg = <0x8000 0x4000>; 135 status = "disabled"; 136 }; 137 138 sram_d: sram@10000 { 139 compatible = "mmio-sram"; 140 reg = <0x00010000 0x1000>; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0 0x00010000 0x1000>; 144 145 otg_sram: sram-section@0 { 146 compatible = "allwinner,sun4i-a10-sram-d"; 147 reg = <0x0000 0x1000>; 148 status = "disabled"; 149 }; 150 }; 151 }; 152 153 dma: dma-controller@1c02000 { 154 compatible = "allwinner,sun4i-a10-dma"; 155 reg = <0x01c02000 0x1000>; 156 interrupts = <27>; 157 clocks = <&ccu CLK_AHB_DMA>; 158 #dma-cells = <2>; 159 }; 160 161 nfc: nand@1c03000 { 162 compatible = "allwinner,sun4i-a10-nand"; 163 reg = <0x01c03000 0x1000>; 164 interrupts = <37>; 165 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 166 clock-names = "ahb", "mod"; 167 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 168 dma-names = "rxtx"; 169 status = "disabled"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 }; 173 174 spi0: spi@1c05000 { 175 compatible = "allwinner,sun4i-a10-spi"; 176 reg = <0x01c05000 0x1000>; 177 interrupts = <10>; 178 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 179 clock-names = "ahb", "mod"; 180 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 181 <&dma SUN4I_DMA_DEDICATED 26>; 182 dma-names = "rx", "tx"; 183 status = "disabled"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 }; 187 188 spi1: spi@1c06000 { 189 compatible = "allwinner,sun4i-a10-spi"; 190 reg = <0x01c06000 0x1000>; 191 interrupts = <11>; 192 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 193 clock-names = "ahb", "mod"; 194 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 195 <&dma SUN4I_DMA_DEDICATED 8>; 196 dma-names = "rx", "tx"; 197 status = "disabled"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 }; 201 202 tve0: tv-encoder@1c0a000 { 203 compatible = "allwinner,sun4i-a10-tv-encoder"; 204 reg = <0x01c0a000 0x1000>; 205 clocks = <&ccu CLK_AHB_TVE>; 206 resets = <&ccu RST_TVE>; 207 status = "disabled"; 208 209 port { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 tve0_in_tcon0: endpoint@0 { 214 reg = <0>; 215 remote-endpoint = <&tcon0_out_tve0>; 216 }; 217 }; 218 }; 219 220 emac: ethernet@1c0b000 { 221 compatible = "allwinner,sun4i-a10-emac"; 222 reg = <0x01c0b000 0x1000>; 223 interrupts = <55>; 224 clocks = <&ccu CLK_AHB_EMAC>; 225 allwinner,sram = <&emac_sram 1>; 226 status = "disabled"; 227 }; 228 229 mdio: mdio@1c0b080 { 230 compatible = "allwinner,sun4i-a10-mdio"; 231 reg = <0x01c0b080 0x14>; 232 status = "disabled"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 }; 236 237 tcon0: lcd-controller@1c0c000 { 238 compatible = "allwinner,sun5i-a13-tcon"; 239 reg = <0x01c0c000 0x1000>; 240 interrupts = <44>; 241 resets = <&ccu RST_LCD>; 242 reset-names = "lcd"; 243 clocks = <&ccu CLK_AHB_LCD>, 244 <&ccu CLK_TCON_CH0>, 245 <&ccu CLK_TCON_CH1>; 246 clock-names = "ahb", 247 "tcon-ch0", 248 "tcon-ch1"; 249 clock-output-names = "tcon-pixel-clock"; 250 status = "disabled"; 251 252 ports { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 tcon0_in: port@0 { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <0>; 260 261 tcon0_in_be0: endpoint@0 { 262 reg = <0>; 263 remote-endpoint = <&be0_out_tcon0>; 264 }; 265 }; 266 267 tcon0_out: port@1 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <1>; 271 272 tcon0_out_tve0: endpoint@1 { 273 reg = <1>; 274 remote-endpoint = <&tve0_in_tcon0>; 275 allwinner,tcon-channel = <1>; 276 }; 277 }; 278 }; 279 }; 280 281 mmc0: mmc@1c0f000 { 282 compatible = "allwinner,sun5i-a13-mmc"; 283 reg = <0x01c0f000 0x1000>; 284 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; 285 clock-names = "ahb", "mmc"; 286 interrupts = <32>; 287 status = "disabled"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 }; 291 292 mmc1: mmc@1c10000 { 293 compatible = "allwinner,sun5i-a13-mmc"; 294 reg = <0x01c10000 0x1000>; 295 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; 296 clock-names = "ahb", "mmc"; 297 interrupts = <33>; 298 status = "disabled"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 }; 302 303 mmc2: mmc@1c11000 { 304 compatible = "allwinner,sun5i-a13-mmc"; 305 reg = <0x01c11000 0x1000>; 306 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; 307 clock-names = "ahb", "mmc"; 308 interrupts = <34>; 309 status = "disabled"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 314 usb_otg: usb@1c13000 { 315 compatible = "allwinner,sun4i-a10-musb"; 316 reg = <0x01c13000 0x0400>; 317 clocks = <&ccu CLK_AHB_OTG>; 318 interrupts = <38>; 319 interrupt-names = "mc"; 320 phys = <&usbphy 0>; 321 phy-names = "usb"; 322 extcon = <&usbphy 0>; 323 allwinner,sram = <&otg_sram 1>; 324 status = "disabled"; 325 }; 326 327 usbphy: phy@1c13400 { 328 #phy-cells = <1>; 329 compatible = "allwinner,sun5i-a13-usb-phy"; 330 reg = <0x01c13400 0x10 0x01c14800 0x4>; 331 reg-names = "phy_ctrl", "pmu1"; 332 clocks = <&ccu CLK_USB_PHY0>; 333 clock-names = "usb_phy"; 334 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; 335 reset-names = "usb0_reset", "usb1_reset"; 336 status = "disabled"; 337 }; 338 339 ehci0: usb@1c14000 { 340 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 341 reg = <0x01c14000 0x100>; 342 interrupts = <39>; 343 clocks = <&ccu CLK_AHB_EHCI>; 344 phys = <&usbphy 1>; 345 phy-names = "usb"; 346 status = "disabled"; 347 }; 348 349 ohci0: usb@1c14400 { 350 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 351 reg = <0x01c14400 0x100>; 352 interrupts = <40>; 353 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; 354 phys = <&usbphy 1>; 355 phy-names = "usb"; 356 status = "disabled"; 357 }; 358 359 crypto: crypto-engine@1c15000 { 360 compatible = "allwinner,sun5i-a13-crypto", 361 "allwinner,sun4i-a10-crypto"; 362 reg = <0x01c15000 0x1000>; 363 interrupts = <54>; 364 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 365 clock-names = "ahb", "mod"; 366 }; 367 368 spi2: spi@1c17000 { 369 compatible = "allwinner,sun4i-a10-spi"; 370 reg = <0x01c17000 0x1000>; 371 interrupts = <12>; 372 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 373 clock-names = "ahb", "mod"; 374 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 375 <&dma SUN4I_DMA_DEDICATED 28>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 }; 381 382 ccu: clock@1c20000 { 383 reg = <0x01c20000 0x400>; 384 clocks = <&osc24M>, <&osc32k>; 385 clock-names = "hosc", "losc"; 386 #clock-cells = <1>; 387 #reset-cells = <1>; 388 }; 389 390 intc: interrupt-controller@1c20400 { 391 compatible = "allwinner,sun4i-a10-ic"; 392 reg = <0x01c20400 0x400>; 393 interrupt-controller; 394 #interrupt-cells = <1>; 395 }; 396 397 pio: pinctrl@1c20800 { 398 reg = <0x01c20800 0x400>; 399 interrupts = <28>; 400 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 401 clock-names = "apb", "hosc", "losc"; 402 gpio-controller; 403 interrupt-controller; 404 #interrupt-cells = <3>; 405 #gpio-cells = <3>; 406 407 emac_pins_a: emac0@0 { 408 pins = "PD6", "PD7", "PD10", 409 "PD11", "PD12", "PD13", "PD14", 410 "PD15", "PD18", "PD19", "PD20", 411 "PD21", "PD22", "PD23", "PD24", 412 "PD25", "PD26", "PD27"; 413 function = "emac"; 414 }; 415 416 i2c0_pins_a: i2c0@0 { 417 pins = "PB0", "PB1"; 418 function = "i2c0"; 419 }; 420 421 i2c1_pins_a: i2c1@0 { 422 pins = "PB15", "PB16"; 423 function = "i2c1"; 424 }; 425 426 i2c2_pins_a: i2c2@0 { 427 pins = "PB17", "PB18"; 428 function = "i2c2"; 429 }; 430 431 ir0_rx_pins_a: ir0@0 { 432 pins = "PB4"; 433 function = "ir0"; 434 }; 435 436 lcd_rgb565_pins: lcd_rgb565@0 { 437 pins = "PD3", "PD4", "PD5", "PD6", "PD7", 438 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 439 "PD19", "PD20", "PD21", "PD22", "PD23", 440 "PD24", "PD25", "PD26", "PD27"; 441 function = "lcd0"; 442 }; 443 444 lcd_rgb666_pins: lcd_rgb666@0 { 445 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 446 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 447 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 448 "PD24", "PD25", "PD26", "PD27"; 449 function = "lcd0"; 450 }; 451 452 mmc0_pins_a: mmc0@0 { 453 pins = "PF0", "PF1", "PF2", "PF3", 454 "PF4", "PF5"; 455 function = "mmc0"; 456 drive-strength = <30>; 457 bias-pull-up; 458 }; 459 460 mmc2_pins_a: mmc2@0 { 461 pins = "PC6", "PC7", "PC8", "PC9", 462 "PC10", "PC11", "PC12", "PC13", 463 "PC14", "PC15"; 464 function = "mmc2"; 465 drive-strength = <30>; 466 bias-pull-up; 467 }; 468 469 mmc2_4bit_pins_a: mmc2-4bit@0 { 470 pins = "PC6", "PC7", "PC8", "PC9", 471 "PC10", "PC11"; 472 function = "mmc2"; 473 drive-strength = <30>; 474 bias-pull-up; 475 }; 476 477 nand_pins_a: nand-base0@0 { 478 pins = "PC0", "PC1", "PC2", 479 "PC5", "PC8", "PC9", "PC10", 480 "PC11", "PC12", "PC13", "PC14", 481 "PC15"; 482 function = "nand0"; 483 }; 484 485 nand_cs0_pins_a: nand-cs@0 { 486 pins = "PC4"; 487 function = "nand0"; 488 }; 489 490 nand_rb0_pins_a: nand-rb@0 { 491 pins = "PC6"; 492 function = "nand0"; 493 }; 494 495 spi2_pins_a: spi2@0 { 496 pins = "PE1", "PE2", "PE3"; 497 function = "spi2"; 498 }; 499 500 spi2_cs0_pins_a: spi2-cs0@0 { 501 pins = "PE0"; 502 function = "spi2"; 503 }; 504 505 uart1_pins_a: uart1@0 { 506 pins = "PE10", "PE11"; 507 function = "uart1"; 508 }; 509 510 uart1_pins_b: uart1@1 { 511 pins = "PG3", "PG4"; 512 function = "uart1"; 513 }; 514 515 uart2_pins_a: uart2@0 { 516 pins = "PD2", "PD3"; 517 function = "uart2"; 518 }; 519 520 uart2_cts_rts_pins_a: uart2-cts-rts@0 { 521 pins = "PD4", "PD5"; 522 function = "uart2"; 523 }; 524 525 uart3_pins_a: uart3@0 { 526 pins = "PG9", "PG10"; 527 function = "uart3"; 528 }; 529 530 uart3_cts_rts_pins_a: uart3-cts-rts@0 { 531 pins = "PG11", "PG12"; 532 function = "uart3"; 533 }; 534 535 pwm0_pins: pwm0 { 536 pins = "PB2"; 537 function = "pwm"; 538 }; 539 }; 540 541 timer@1c20c00 { 542 compatible = "allwinner,sun4i-a10-timer"; 543 reg = <0x01c20c00 0x90>; 544 interrupts = <22>; 545 clocks = <&ccu CLK_HOSC>; 546 }; 547 548 wdt: watchdog@1c20c90 { 549 compatible = "allwinner,sun4i-a10-wdt"; 550 reg = <0x01c20c90 0x10>; 551 }; 552 553 ir0: ir@1c21800 { 554 compatible = "allwinner,sun4i-a10-ir"; 555 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; 556 clock-names = "apb", "ir"; 557 interrupts = <5>; 558 reg = <0x01c21800 0x40>; 559 status = "disabled"; 560 }; 561 562 lradc: lradc@1c22800 { 563 compatible = "allwinner,sun4i-a10-lradc-keys"; 564 reg = <0x01c22800 0x100>; 565 interrupts = <31>; 566 status = "disabled"; 567 }; 568 569 codec: codec@1c22c00 { 570 #sound-dai-cells = <0>; 571 compatible = "allwinner,sun4i-a10-codec"; 572 reg = <0x01c22c00 0x40>; 573 interrupts = <30>; 574 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 575 clock-names = "apb", "codec"; 576 dmas = <&dma SUN4I_DMA_NORMAL 19>, 577 <&dma SUN4I_DMA_NORMAL 19>; 578 dma-names = "rx", "tx"; 579 status = "disabled"; 580 }; 581 582 sid: eeprom@1c23800 { 583 compatible = "allwinner,sun4i-a10-sid"; 584 reg = <0x01c23800 0x10>; 585 }; 586 587 rtp: rtp@1c25000 { 588 compatible = "allwinner,sun5i-a13-ts"; 589 reg = <0x01c25000 0x100>; 590 interrupts = <29>; 591 #thermal-sensor-cells = <0>; 592 }; 593 594 uart0: serial@1c28000 { 595 compatible = "snps,dw-apb-uart"; 596 reg = <0x01c28000 0x400>; 597 interrupts = <1>; 598 reg-shift = <2>; 599 reg-io-width = <4>; 600 clocks = <&ccu CLK_APB1_UART0>; 601 status = "disabled"; 602 }; 603 604 uart1: serial@1c28400 { 605 compatible = "snps,dw-apb-uart"; 606 reg = <0x01c28400 0x400>; 607 interrupts = <2>; 608 reg-shift = <2>; 609 reg-io-width = <4>; 610 clocks = <&ccu CLK_APB1_UART1>; 611 status = "disabled"; 612 }; 613 614 uart2: serial@1c28800 { 615 compatible = "snps,dw-apb-uart"; 616 reg = <0x01c28800 0x400>; 617 interrupts = <3>; 618 reg-shift = <2>; 619 reg-io-width = <4>; 620 clocks = <&ccu CLK_APB1_UART2>; 621 status = "disabled"; 622 }; 623 624 uart3: serial@1c28c00 { 625 compatible = "snps,dw-apb-uart"; 626 reg = <0x01c28c00 0x400>; 627 interrupts = <4>; 628 reg-shift = <2>; 629 reg-io-width = <4>; 630 clocks = <&ccu CLK_APB1_UART3>; 631 status = "disabled"; 632 }; 633 634 i2c0: i2c@1c2ac00 { 635 compatible = "allwinner,sun4i-a10-i2c"; 636 reg = <0x01c2ac00 0x400>; 637 interrupts = <7>; 638 clocks = <&ccu CLK_APB1_I2C0>; 639 status = "disabled"; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 }; 643 644 i2c1: i2c@1c2b000 { 645 compatible = "allwinner,sun4i-a10-i2c"; 646 reg = <0x01c2b000 0x400>; 647 interrupts = <8>; 648 clocks = <&ccu CLK_APB1_I2C1>; 649 status = "disabled"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 }; 653 654 i2c2: i2c@1c2b400 { 655 compatible = "allwinner,sun4i-a10-i2c"; 656 reg = <0x01c2b400 0x400>; 657 interrupts = <9>; 658 clocks = <&ccu CLK_APB1_I2C2>; 659 status = "disabled"; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 }; 663 664 timer@1c60000 { 665 compatible = "allwinner,sun5i-a13-hstimer"; 666 reg = <0x01c60000 0x1000>; 667 interrupts = <82>, <83>; 668 clocks = <&ccu CLK_AHB_HSTIMER>; 669 }; 670 671 fe0: display-frontend@1e00000 { 672 compatible = "allwinner,sun5i-a13-display-frontend"; 673 reg = <0x01e00000 0x20000>; 674 interrupts = <47>; 675 clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, 676 <&ccu CLK_DRAM_DE_FE>; 677 clock-names = "ahb", "mod", 678 "ram"; 679 resets = <&ccu RST_DE_FE>; 680 status = "disabled"; 681 682 ports { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 686 fe0_out: port@1 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 reg = <1>; 690 691 fe0_out_be0: endpoint@0 { 692 reg = <0>; 693 remote-endpoint = <&be0_in_fe0>; 694 }; 695 }; 696 }; 697 }; 698 699 be0: display-backend@1e60000 { 700 compatible = "allwinner,sun5i-a13-display-backend"; 701 reg = <0x01e60000 0x10000>; 702 interrupts = <47>; 703 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 704 <&ccu CLK_DRAM_DE_BE>; 705 clock-names = "ahb", "mod", 706 "ram"; 707 resets = <&ccu RST_DE_BE>; 708 status = "disabled"; 709 710 assigned-clocks = <&ccu CLK_DE_BE>; 711 assigned-clock-rates = <300000000>; 712 713 ports { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 be0_in: port@0 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 reg = <0>; 721 722 be0_in_fe0: endpoint@0 { 723 reg = <0>; 724 remote-endpoint = <&fe0_out_be0>; 725 }; 726 }; 727 728 be0_out: port@1 { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 reg = <1>; 732 733 be0_out_tcon0: endpoint@0 { 734 reg = <0>; 735 remote-endpoint = <&tcon0_in_be0>; 736 }; 737 }; 738 }; 739 }; 740 }; 741}; 742