1/* 2 * Copyright 2012-2015 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/clock/sun4i-a10-pll2.h> 48#include <dt-bindings/dma/sun4i-a10.h> 49#include <dt-bindings/pinctrl/sun4i-a10.h> 50 51/ { 52 interrupt-parent = <&intc>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a8"; 61 reg = <0x0>; 62 clocks = <&cpu>; 63 }; 64 }; 65 66 clocks { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 /* 72 * This is a dummy clock, to be used as placeholder on 73 * other mux clocks when a specific parent clock is not 74 * yet implemented. It should be dropped when the driver 75 * is complete. 76 */ 77 dummy: dummy { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <0>; 81 }; 82 83 osc24M: clk@01c20050 { 84 #clock-cells = <0>; 85 compatible = "allwinner,sun4i-a10-osc-clk"; 86 reg = <0x01c20050 0x4>; 87 clock-frequency = <24000000>; 88 clock-output-names = "osc24M"; 89 }; 90 91 osc32k: clk@0 { 92 #clock-cells = <0>; 93 compatible = "fixed-clock"; 94 clock-frequency = <32768>; 95 clock-output-names = "osc32k"; 96 }; 97 98 pll1: clk@01c20000 { 99 #clock-cells = <0>; 100 compatible = "allwinner,sun4i-a10-pll1-clk"; 101 reg = <0x01c20000 0x4>; 102 clocks = <&osc24M>; 103 clock-output-names = "pll1"; 104 }; 105 106 pll2: clk@01c20008 { 107 #clock-cells = <1>; 108 compatible = "allwinner,sun5i-a13-pll2-clk"; 109 reg = <0x01c20008 0x8>; 110 clocks = <&osc24M>; 111 clock-output-names = "pll2-1x", "pll2-2x", 112 "pll2-4x", "pll2-8x"; 113 }; 114 115 pll4: clk@01c20018 { 116 #clock-cells = <0>; 117 compatible = "allwinner,sun4i-a10-pll1-clk"; 118 reg = <0x01c20018 0x4>; 119 clocks = <&osc24M>; 120 clock-output-names = "pll4"; 121 }; 122 123 pll5: clk@01c20020 { 124 #clock-cells = <1>; 125 compatible = "allwinner,sun4i-a10-pll5-clk"; 126 reg = <0x01c20020 0x4>; 127 clocks = <&osc24M>; 128 clock-output-names = "pll5_ddr", "pll5_other"; 129 }; 130 131 pll6: clk@01c20028 { 132 #clock-cells = <1>; 133 compatible = "allwinner,sun4i-a10-pll6-clk"; 134 reg = <0x01c20028 0x4>; 135 clocks = <&osc24M>; 136 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 137 }; 138 139 /* dummy is 200M */ 140 cpu: cpu@01c20054 { 141 #clock-cells = <0>; 142 compatible = "allwinner,sun4i-a10-cpu-clk"; 143 reg = <0x01c20054 0x4>; 144 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 145 clock-output-names = "cpu"; 146 }; 147 148 axi: axi@01c20054 { 149 #clock-cells = <0>; 150 compatible = "allwinner,sun4i-a10-axi-clk"; 151 reg = <0x01c20054 0x4>; 152 clocks = <&cpu>; 153 clock-output-names = "axi"; 154 }; 155 156 ahb: ahb@01c20054 { 157 #clock-cells = <0>; 158 compatible = "allwinner,sun5i-a13-ahb-clk"; 159 reg = <0x01c20054 0x4>; 160 clocks = <&axi>, <&cpu>, <&pll6 1>; 161 clock-output-names = "ahb"; 162 /* 163 * Use PLL6 as parent, instead of CPU/AXI 164 * which has rate changes due to cpufreq 165 */ 166 assigned-clocks = <&ahb>; 167 assigned-clock-parents = <&pll6 1>; 168 }; 169 170 apb0: apb0@01c20054 { 171 #clock-cells = <0>; 172 compatible = "allwinner,sun4i-a10-apb0-clk"; 173 reg = <0x01c20054 0x4>; 174 clocks = <&ahb>; 175 clock-output-names = "apb0"; 176 }; 177 178 apb1: clk@01c20058 { 179 #clock-cells = <0>; 180 compatible = "allwinner,sun4i-a10-apb1-clk"; 181 reg = <0x01c20058 0x4>; 182 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 183 clock-output-names = "apb1"; 184 }; 185 186 axi_gates: clk@01c2005c { 187 #clock-cells = <1>; 188 compatible = "allwinner,sun4i-a10-axi-gates-clk"; 189 reg = <0x01c2005c 0x4>; 190 clocks = <&axi>; 191 clock-indices = <0>; 192 clock-output-names = "axi_dram"; 193 }; 194 195 nand_clk: clk@01c20080 { 196 #clock-cells = <0>; 197 compatible = "allwinner,sun4i-a10-mod0-clk"; 198 reg = <0x01c20080 0x4>; 199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 200 clock-output-names = "nand"; 201 }; 202 203 ms_clk: clk@01c20084 { 204 #clock-cells = <0>; 205 compatible = "allwinner,sun4i-a10-mod0-clk"; 206 reg = <0x01c20084 0x4>; 207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 208 clock-output-names = "ms"; 209 }; 210 211 mmc0_clk: clk@01c20088 { 212 #clock-cells = <1>; 213 compatible = "allwinner,sun4i-a10-mmc-clk"; 214 reg = <0x01c20088 0x4>; 215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 216 clock-output-names = "mmc0", 217 "mmc0_output", 218 "mmc0_sample"; 219 }; 220 221 mmc1_clk: clk@01c2008c { 222 #clock-cells = <1>; 223 compatible = "allwinner,sun4i-a10-mmc-clk"; 224 reg = <0x01c2008c 0x4>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 226 clock-output-names = "mmc1", 227 "mmc1_output", 228 "mmc1_sample"; 229 }; 230 231 mmc2_clk: clk@01c20090 { 232 #clock-cells = <1>; 233 compatible = "allwinner,sun4i-a10-mmc-clk"; 234 reg = <0x01c20090 0x4>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 236 clock-output-names = "mmc2", 237 "mmc2_output", 238 "mmc2_sample"; 239 }; 240 241 ts_clk: clk@01c20098 { 242 #clock-cells = <0>; 243 compatible = "allwinner,sun4i-a10-mod0-clk"; 244 reg = <0x01c20098 0x4>; 245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 246 clock-output-names = "ts"; 247 }; 248 249 ss_clk: clk@01c2009c { 250 #clock-cells = <0>; 251 compatible = "allwinner,sun4i-a10-mod0-clk"; 252 reg = <0x01c2009c 0x4>; 253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 254 clock-output-names = "ss"; 255 }; 256 257 spi0_clk: clk@01c200a0 { 258 #clock-cells = <0>; 259 compatible = "allwinner,sun4i-a10-mod0-clk"; 260 reg = <0x01c200a0 0x4>; 261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 262 clock-output-names = "spi0"; 263 }; 264 265 spi1_clk: clk@01c200a4 { 266 #clock-cells = <0>; 267 compatible = "allwinner,sun4i-a10-mod0-clk"; 268 reg = <0x01c200a4 0x4>; 269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 270 clock-output-names = "spi1"; 271 }; 272 273 spi2_clk: clk@01c200a8 { 274 #clock-cells = <0>; 275 compatible = "allwinner,sun4i-a10-mod0-clk"; 276 reg = <0x01c200a8 0x4>; 277 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 278 clock-output-names = "spi2"; 279 }; 280 281 ir0_clk: clk@01c200b0 { 282 #clock-cells = <0>; 283 compatible = "allwinner,sun4i-a10-mod0-clk"; 284 reg = <0x01c200b0 0x4>; 285 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 286 clock-output-names = "ir0"; 287 }; 288 289 usb_clk: clk@01c200cc { 290 #clock-cells = <1>; 291 #reset-cells = <1>; 292 compatible = "allwinner,sun5i-a13-usb-clk"; 293 reg = <0x01c200cc 0x4>; 294 clocks = <&pll6 1>; 295 clock-output-names = "usb_ohci0", "usb_phy"; 296 }; 297 298 codec_clk: clk@01c20140 { 299 #clock-cells = <0>; 300 compatible = "allwinner,sun4i-a10-codec-clk"; 301 reg = <0x01c20140 0x4>; 302 clocks = <&pll2 SUN4I_A10_PLL2_1X>; 303 clock-output-names = "codec"; 304 }; 305 306 mbus_clk: clk@01c2015c { 307 #clock-cells = <0>; 308 compatible = "allwinner,sun5i-a13-mbus-clk"; 309 reg = <0x01c2015c 0x4>; 310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 311 clock-output-names = "mbus"; 312 }; 313 }; 314 315 soc@01c00000 { 316 compatible = "simple-bus"; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges; 320 321 sram-controller@01c00000 { 322 compatible = "allwinner,sun4i-a10-sram-controller"; 323 reg = <0x01c00000 0x30>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges; 327 328 sram_a: sram@00000000 { 329 compatible = "mmio-sram"; 330 reg = <0x00000000 0xc000>; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 ranges = <0 0x00000000 0xc000>; 334 }; 335 336 sram_d: sram@00010000 { 337 compatible = "mmio-sram"; 338 reg = <0x00010000 0x1000>; 339 #address-cells = <1>; 340 #size-cells = <1>; 341 ranges = <0 0x00010000 0x1000>; 342 343 otg_sram: sram-section@0000 { 344 compatible = "allwinner,sun4i-a10-sram-d"; 345 reg = <0x0000 0x1000>; 346 status = "disabled"; 347 }; 348 }; 349 }; 350 351 dma: dma-controller@01c02000 { 352 compatible = "allwinner,sun4i-a10-dma"; 353 reg = <0x01c02000 0x1000>; 354 interrupts = <27>; 355 clocks = <&ahb_gates 6>; 356 #dma-cells = <2>; 357 }; 358 359 nfc: nand@01c03000 { 360 compatible = "allwinner,sun4i-a10-nand"; 361 reg = <0x01c03000 0x1000>; 362 interrupts = <37>; 363 clocks = <&ahb_gates 13>, <&nand_clk>; 364 clock-names = "ahb", "mod"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 status = "disabled"; 368 }; 369 370 spi0: spi@01c05000 { 371 compatible = "allwinner,sun4i-a10-spi"; 372 reg = <0x01c05000 0x1000>; 373 interrupts = <10>; 374 clocks = <&ahb_gates 20>, <&spi0_clk>; 375 clock-names = "ahb", "mod"; 376 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 377 <&dma SUN4I_DMA_DEDICATED 26>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 }; 383 384 spi1: spi@01c06000 { 385 compatible = "allwinner,sun4i-a10-spi"; 386 reg = <0x01c06000 0x1000>; 387 interrupts = <11>; 388 clocks = <&ahb_gates 21>, <&spi1_clk>; 389 clock-names = "ahb", "mod"; 390 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 391 <&dma SUN4I_DMA_DEDICATED 8>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 }; 397 398 mmc0: mmc@01c0f000 { 399 compatible = "allwinner,sun5i-a13-mmc"; 400 reg = <0x01c0f000 0x1000>; 401 clocks = <&ahb_gates 8>, 402 <&mmc0_clk 0>, 403 <&mmc0_clk 1>, 404 <&mmc0_clk 2>; 405 clock-names = "ahb", 406 "mmc", 407 "output", 408 "sample"; 409 interrupts = <32>; 410 status = "disabled"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 }; 414 415 mmc1: mmc@01c10000 { 416 compatible = "allwinner,sun5i-a13-mmc"; 417 reg = <0x01c10000 0x1000>; 418 clocks = <&ahb_gates 9>, 419 <&mmc1_clk 0>, 420 <&mmc1_clk 1>, 421 <&mmc1_clk 2>; 422 clock-names = "ahb", 423 "mmc", 424 "output", 425 "sample"; 426 interrupts = <33>; 427 status = "disabled"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 432 mmc2: mmc@01c11000 { 433 compatible = "allwinner,sun5i-a13-mmc"; 434 reg = <0x01c11000 0x1000>; 435 clocks = <&ahb_gates 10>, 436 <&mmc2_clk 0>, 437 <&mmc2_clk 1>, 438 <&mmc2_clk 2>; 439 clock-names = "ahb", 440 "mmc", 441 "output", 442 "sample"; 443 interrupts = <34>; 444 status = "disabled"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 }; 448 449 usb_otg: usb@01c13000 { 450 compatible = "allwinner,sun4i-a10-musb"; 451 reg = <0x01c13000 0x0400>; 452 clocks = <&ahb_gates 0>; 453 interrupts = <38>; 454 interrupt-names = "mc"; 455 phys = <&usbphy 0>; 456 phy-names = "usb"; 457 extcon = <&usbphy 0>; 458 allwinner,sram = <&otg_sram 1>; 459 status = "disabled"; 460 }; 461 462 usbphy: phy@01c13400 { 463 #phy-cells = <1>; 464 compatible = "allwinner,sun5i-a13-usb-phy"; 465 reg = <0x01c13400 0x10 0x01c14800 0x4>; 466 reg-names = "phy_ctrl", "pmu1"; 467 clocks = <&usb_clk 8>; 468 clock-names = "usb_phy"; 469 resets = <&usb_clk 0>, <&usb_clk 1>; 470 reset-names = "usb0_reset", "usb1_reset"; 471 status = "disabled"; 472 }; 473 474 ehci0: usb@01c14000 { 475 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 476 reg = <0x01c14000 0x100>; 477 interrupts = <39>; 478 clocks = <&ahb_gates 1>; 479 phys = <&usbphy 1>; 480 phy-names = "usb"; 481 status = "disabled"; 482 }; 483 484 ohci0: usb@01c14400 { 485 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 486 reg = <0x01c14400 0x100>; 487 interrupts = <40>; 488 clocks = <&usb_clk 6>, <&ahb_gates 2>; 489 phys = <&usbphy 1>; 490 phy-names = "usb"; 491 status = "disabled"; 492 }; 493 494 spi2: spi@01c17000 { 495 compatible = "allwinner,sun4i-a10-spi"; 496 reg = <0x01c17000 0x1000>; 497 interrupts = <12>; 498 clocks = <&ahb_gates 22>, <&spi2_clk>; 499 clock-names = "ahb", "mod"; 500 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 501 <&dma SUN4I_DMA_DEDICATED 28>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 }; 507 508 intc: interrupt-controller@01c20400 { 509 compatible = "allwinner,sun4i-a10-ic"; 510 reg = <0x01c20400 0x400>; 511 interrupt-controller; 512 #interrupt-cells = <1>; 513 }; 514 515 pio: pinctrl@01c20800 { 516 reg = <0x01c20800 0x400>; 517 interrupts = <28>; 518 clocks = <&apb0_gates 5>; 519 gpio-controller; 520 interrupt-controller; 521 #interrupt-cells = <3>; 522 #gpio-cells = <3>; 523 524 i2c0_pins_a: i2c0@0 { 525 allwinner,pins = "PB0", "PB1"; 526 allwinner,function = "i2c0"; 527 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 528 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 529 }; 530 531 i2c1_pins_a: i2c1@0 { 532 allwinner,pins = "PB15", "PB16"; 533 allwinner,function = "i2c1"; 534 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 535 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 536 }; 537 538 i2c2_pins_a: i2c2@0 { 539 allwinner,pins = "PB17", "PB18"; 540 allwinner,function = "i2c2"; 541 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 542 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 543 }; 544 545 mmc0_pins_a: mmc0@0 { 546 allwinner,pins = "PF0", "PF1", "PF2", "PF3", 547 "PF4", "PF5"; 548 allwinner,function = "mmc0"; 549 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 550 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 551 }; 552 553 mmc2_pins_a: mmc2@0 { 554 allwinner,pins = "PC6", "PC7", "PC8", "PC9", 555 "PC10", "PC11", "PC12", "PC13", 556 "PC14", "PC15"; 557 allwinner,function = "mmc2"; 558 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 559 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 560 }; 561 562 nand_pins_a: nand_base0@0 { 563 allwinner,pins = "PC0", "PC1", "PC2", 564 "PC5", "PC8", "PC9", "PC10", 565 "PC11", "PC12", "PC13", "PC14", 566 "PC15"; 567 allwinner,function = "nand0"; 568 allwinner,drive = <0>; 569 allwinner,pull = <0>; 570 }; 571 572 nand_cs0_pins_a: nand_cs@0 { 573 allwinner,pins = "PC4"; 574 allwinner,function = "nand0"; 575 allwinner,drive = <0>; 576 allwinner,pull = <0>; 577 }; 578 579 nand_cs1_pins_a: nand_cs@1 { 580 allwinner,pins = "PC3"; 581 allwinner,function = "nand0"; 582 allwinner,drive = <0>; 583 allwinner,pull = <0>; 584 }; 585 586 nand_rb0_pins_a: nand_rb@0 { 587 allwinner,pins = "PC6"; 588 allwinner,function = "nand0"; 589 allwinner,drive = <0>; 590 allwinner,pull = <0>; 591 }; 592 593 nand_rb1_pins_a: nand_rb@1 { 594 allwinner,pins = "PC7"; 595 allwinner,function = "nand0"; 596 allwinner,drive = <0>; 597 allwinner,pull = <0>; 598 }; 599 600 uart3_pins_a: uart3@0 { 601 allwinner,pins = "PG9", "PG10"; 602 allwinner,function = "uart3"; 603 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 604 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 605 }; 606 607 uart3_pins_cts_rts_a: uart3-cts-rts@0 { 608 allwinner,pins = "PG11", "PG12"; 609 allwinner,function = "uart3"; 610 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 611 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 612 }; 613 614 pwm0_pins: pwm0 { 615 allwinner,pins = "PB2"; 616 allwinner,function = "pwm"; 617 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 618 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 619 }; 620 }; 621 622 timer@01c20c00 { 623 compatible = "allwinner,sun4i-a10-timer"; 624 reg = <0x01c20c00 0x90>; 625 interrupts = <22>; 626 clocks = <&osc24M>; 627 }; 628 629 wdt: watchdog@01c20c90 { 630 compatible = "allwinner,sun4i-a10-wdt"; 631 reg = <0x01c20c90 0x10>; 632 }; 633 634 lradc: lradc@01c22800 { 635 compatible = "allwinner,sun4i-a10-lradc-keys"; 636 reg = <0x01c22800 0x100>; 637 interrupts = <31>; 638 status = "disabled"; 639 }; 640 641 codec: codec@01c22c00 { 642 #sound-dai-cells = <0>; 643 compatible = "allwinner,sun4i-a10-codec"; 644 reg = <0x01c22c00 0x40>; 645 interrupts = <30>; 646 clocks = <&apb0_gates 0>, <&codec_clk>; 647 clock-names = "apb", "codec"; 648 dmas = <&dma SUN4I_DMA_NORMAL 19>, 649 <&dma SUN4I_DMA_NORMAL 19>; 650 dma-names = "rx", "tx"; 651 status = "disabled"; 652 }; 653 654 sid: eeprom@01c23800 { 655 compatible = "allwinner,sun4i-a10-sid"; 656 reg = <0x01c23800 0x10>; 657 }; 658 659 rtp: rtp@01c25000 { 660 compatible = "allwinner,sun5i-a13-ts"; 661 reg = <0x01c25000 0x100>; 662 interrupts = <29>; 663 #thermal-sensor-cells = <0>; 664 }; 665 666 uart1: serial@01c28400 { 667 compatible = "snps,dw-apb-uart"; 668 reg = <0x01c28400 0x400>; 669 interrupts = <2>; 670 reg-shift = <2>; 671 reg-io-width = <4>; 672 clocks = <&apb1_gates 17>; 673 status = "disabled"; 674 }; 675 676 uart3: serial@01c28c00 { 677 compatible = "snps,dw-apb-uart"; 678 reg = <0x01c28c00 0x400>; 679 interrupts = <4>; 680 reg-shift = <2>; 681 reg-io-width = <4>; 682 clocks = <&apb1_gates 19>; 683 status = "disabled"; 684 }; 685 686 i2c0: i2c@01c2ac00 { 687 compatible = "allwinner,sun4i-a10-i2c"; 688 reg = <0x01c2ac00 0x400>; 689 interrupts = <7>; 690 clocks = <&apb1_gates 0>; 691 status = "disabled"; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 }; 695 696 i2c1: i2c@01c2b000 { 697 compatible = "allwinner,sun4i-a10-i2c"; 698 reg = <0x01c2b000 0x400>; 699 interrupts = <8>; 700 clocks = <&apb1_gates 1>; 701 status = "disabled"; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 }; 705 706 i2c2: i2c@01c2b400 { 707 compatible = "allwinner,sun4i-a10-i2c"; 708 reg = <0x01c2b400 0x400>; 709 interrupts = <9>; 710 clocks = <&apb1_gates 2>; 711 status = "disabled"; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 }; 715 716 timer@01c60000 { 717 compatible = "allwinner,sun5i-a13-hstimer"; 718 reg = <0x01c60000 0x1000>; 719 interrupts = <82>, <83>; 720 clocks = <&ahb_gates 28>; 721 }; 722 }; 723}; 724