1*6a3a226eSMaxime Ripard/* 2*6a3a226eSMaxime Ripard * Copyright 2016 Mylène Josserand 3*6a3a226eSMaxime Ripard * 4*6a3a226eSMaxime Ripard * Mylène Josserand <mylene.josserand@free-electrons.com> 5*6a3a226eSMaxime Ripard * 6*6a3a226eSMaxime Ripard * This file is dual-licensed: you can use it either under the terms 7*6a3a226eSMaxime Ripard * of the GPL or the X11 license, at your option. Note that this dual 8*6a3a226eSMaxime Ripard * licensing only applies to this file, and not this project as a 9*6a3a226eSMaxime Ripard * whole. 10*6a3a226eSMaxime Ripard * 11*6a3a226eSMaxime Ripard * a) This library is free software; you can redistribute it and/or 12*6a3a226eSMaxime Ripard * modify it under the terms of the GNU General Public License as 13*6a3a226eSMaxime Ripard * published by the Free Software Foundation; either version 2 of the 14*6a3a226eSMaxime Ripard * License, or (at your option) any later version. 15*6a3a226eSMaxime Ripard * 16*6a3a226eSMaxime Ripard * This library is distributed in the hope that it will be useful, 17*6a3a226eSMaxime Ripard * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*6a3a226eSMaxime Ripard * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*6a3a226eSMaxime Ripard * GNU General Public License for more details. 20*6a3a226eSMaxime Ripard * 21*6a3a226eSMaxime Ripard * Or, alternatively, 22*6a3a226eSMaxime Ripard * 23*6a3a226eSMaxime Ripard * b) Permission is hereby granted, free of charge, to any person 24*6a3a226eSMaxime Ripard * obtaining a copy of this software and associated documentation 25*6a3a226eSMaxime Ripard * files (the "Software"), to deal in the Software without 26*6a3a226eSMaxime Ripard * restriction, including without limitation the rights to use, 27*6a3a226eSMaxime Ripard * copy, modify, merge, publish, distribute, sublicense, and/or 28*6a3a226eSMaxime Ripard * sell copies of the Software, and to permit persons to whom the 29*6a3a226eSMaxime Ripard * Software is furnished to do so, subject to the following 30*6a3a226eSMaxime Ripard * conditions: 31*6a3a226eSMaxime Ripard * 32*6a3a226eSMaxime Ripard * The above copyright notice and this permission notice shall be 33*6a3a226eSMaxime Ripard * included in all copies or substantial portions of the Software. 34*6a3a226eSMaxime Ripard * 35*6a3a226eSMaxime Ripard * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*6a3a226eSMaxime Ripard * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*6a3a226eSMaxime Ripard * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*6a3a226eSMaxime Ripard * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*6a3a226eSMaxime Ripard * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*6a3a226eSMaxime Ripard * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*6a3a226eSMaxime Ripard * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*6a3a226eSMaxime Ripard * OTHER DEALINGS IN THE SOFTWARE. 43*6a3a226eSMaxime Ripard */ 44*6a3a226eSMaxime Ripard 45*6a3a226eSMaxime Ripard#include <dt-bindings/clock/sun4i-a10-pll2.h> 46*6a3a226eSMaxime Ripard#include <dt-bindings/dma/sun4i-a10.h> 47*6a3a226eSMaxime Ripard#include <dt-bindings/pinctrl/sun4i-a10.h> 48*6a3a226eSMaxime Ripard 49*6a3a226eSMaxime Ripard/ { 50*6a3a226eSMaxime Ripard interrupt-parent = <&intc>; 51*6a3a226eSMaxime Ripard #address-cells = <1>; 52*6a3a226eSMaxime Ripard #size-cells = <1>; 53*6a3a226eSMaxime Ripard 54*6a3a226eSMaxime Ripard cpus { 55*6a3a226eSMaxime Ripard #address-cells = <1>; 56*6a3a226eSMaxime Ripard #size-cells = <0>; 57*6a3a226eSMaxime Ripard 58*6a3a226eSMaxime Ripard cpu0: cpu@0 { 59*6a3a226eSMaxime Ripard device_type = "cpu"; 60*6a3a226eSMaxime Ripard compatible = "arm,cortex-a8"; 61*6a3a226eSMaxime Ripard reg = <0x0>; 62*6a3a226eSMaxime Ripard clocks = <&cpu>; 63*6a3a226eSMaxime Ripard }; 64*6a3a226eSMaxime Ripard }; 65*6a3a226eSMaxime Ripard 66*6a3a226eSMaxime Ripard clocks { 67*6a3a226eSMaxime Ripard #address-cells = <1>; 68*6a3a226eSMaxime Ripard #size-cells = <1>; 69*6a3a226eSMaxime Ripard ranges; 70*6a3a226eSMaxime Ripard 71*6a3a226eSMaxime Ripard /* 72*6a3a226eSMaxime Ripard * This is a dummy clock, to be used as placeholder on 73*6a3a226eSMaxime Ripard * other mux clocks when a specific parent clock is not 74*6a3a226eSMaxime Ripard * yet implemented. It should be dropped when the driver 75*6a3a226eSMaxime Ripard * is complete. 76*6a3a226eSMaxime Ripard */ 77*6a3a226eSMaxime Ripard dummy: dummy { 78*6a3a226eSMaxime Ripard #clock-cells = <0>; 79*6a3a226eSMaxime Ripard compatible = "fixed-clock"; 80*6a3a226eSMaxime Ripard clock-frequency = <0>; 81*6a3a226eSMaxime Ripard }; 82*6a3a226eSMaxime Ripard 83*6a3a226eSMaxime Ripard osc24M: clk@01c20050 { 84*6a3a226eSMaxime Ripard #clock-cells = <0>; 85*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-osc-clk"; 86*6a3a226eSMaxime Ripard reg = <0x01c20050 0x4>; 87*6a3a226eSMaxime Ripard clock-frequency = <24000000>; 88*6a3a226eSMaxime Ripard clock-output-names = "osc24M"; 89*6a3a226eSMaxime Ripard }; 90*6a3a226eSMaxime Ripard 91*6a3a226eSMaxime Ripard osc3M: osc3M-clk { 92*6a3a226eSMaxime Ripard compatible = "fixed-factor-clock"; 93*6a3a226eSMaxime Ripard #clock-cells = <0>; 94*6a3a226eSMaxime Ripard clock-div = <8>; 95*6a3a226eSMaxime Ripard clock-mult = <1>; 96*6a3a226eSMaxime Ripard clocks = <&osc24M>; 97*6a3a226eSMaxime Ripard clock-output-names = "osc3M"; 98*6a3a226eSMaxime Ripard }; 99*6a3a226eSMaxime Ripard 100*6a3a226eSMaxime Ripard osc32k: clk@0 { 101*6a3a226eSMaxime Ripard #clock-cells = <0>; 102*6a3a226eSMaxime Ripard compatible = "fixed-clock"; 103*6a3a226eSMaxime Ripard clock-frequency = <32768>; 104*6a3a226eSMaxime Ripard clock-output-names = "osc32k"; 105*6a3a226eSMaxime Ripard }; 106*6a3a226eSMaxime Ripard 107*6a3a226eSMaxime Ripard pll1: clk@01c20000 { 108*6a3a226eSMaxime Ripard #clock-cells = <0>; 109*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll1-clk"; 110*6a3a226eSMaxime Ripard reg = <0x01c20000 0x4>; 111*6a3a226eSMaxime Ripard clocks = <&osc24M>; 112*6a3a226eSMaxime Ripard clock-output-names = "pll1"; 113*6a3a226eSMaxime Ripard }; 114*6a3a226eSMaxime Ripard 115*6a3a226eSMaxime Ripard pll2: clk@01c20008 { 116*6a3a226eSMaxime Ripard #clock-cells = <1>; 117*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-pll2-clk"; 118*6a3a226eSMaxime Ripard reg = <0x01c20008 0x8>; 119*6a3a226eSMaxime Ripard clocks = <&osc24M>; 120*6a3a226eSMaxime Ripard clock-output-names = "pll2-1x", "pll2-2x", 121*6a3a226eSMaxime Ripard "pll2-4x", "pll2-8x"; 122*6a3a226eSMaxime Ripard }; 123*6a3a226eSMaxime Ripard 124*6a3a226eSMaxime Ripard pll3: clk@01c20010 { 125*6a3a226eSMaxime Ripard #clock-cells = <0>; 126*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll3-clk"; 127*6a3a226eSMaxime Ripard reg = <0x01c20010 0x4>; 128*6a3a226eSMaxime Ripard clocks = <&osc3M>; 129*6a3a226eSMaxime Ripard clock-output-names = "pll3"; 130*6a3a226eSMaxime Ripard }; 131*6a3a226eSMaxime Ripard 132*6a3a226eSMaxime Ripard pll3x2: pll3x2-clk { 133*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll3-2x-clk"; 134*6a3a226eSMaxime Ripard #clock-cells = <0>; 135*6a3a226eSMaxime Ripard clock-div = <1>; 136*6a3a226eSMaxime Ripard clock-mult = <2>; 137*6a3a226eSMaxime Ripard clocks = <&pll3>; 138*6a3a226eSMaxime Ripard clock-output-names = "pll3-2x"; 139*6a3a226eSMaxime Ripard }; 140*6a3a226eSMaxime Ripard 141*6a3a226eSMaxime Ripard pll4: clk@01c20018 { 142*6a3a226eSMaxime Ripard #clock-cells = <0>; 143*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll1-clk"; 144*6a3a226eSMaxime Ripard reg = <0x01c20018 0x4>; 145*6a3a226eSMaxime Ripard clocks = <&osc24M>; 146*6a3a226eSMaxime Ripard clock-output-names = "pll4"; 147*6a3a226eSMaxime Ripard }; 148*6a3a226eSMaxime Ripard 149*6a3a226eSMaxime Ripard pll5: clk@01c20020 { 150*6a3a226eSMaxime Ripard #clock-cells = <1>; 151*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll5-clk"; 152*6a3a226eSMaxime Ripard reg = <0x01c20020 0x4>; 153*6a3a226eSMaxime Ripard clocks = <&osc24M>; 154*6a3a226eSMaxime Ripard clock-output-names = "pll5_ddr", "pll5_other"; 155*6a3a226eSMaxime Ripard }; 156*6a3a226eSMaxime Ripard 157*6a3a226eSMaxime Ripard pll6: clk@01c20028 { 158*6a3a226eSMaxime Ripard #clock-cells = <1>; 159*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll6-clk"; 160*6a3a226eSMaxime Ripard reg = <0x01c20028 0x4>; 161*6a3a226eSMaxime Ripard clocks = <&osc24M>; 162*6a3a226eSMaxime Ripard clock-output-names = "pll6_sata", "pll6_other", "pll6"; 163*6a3a226eSMaxime Ripard }; 164*6a3a226eSMaxime Ripard 165*6a3a226eSMaxime Ripard pll7: clk@01c20030 { 166*6a3a226eSMaxime Ripard #clock-cells = <0>; 167*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll3-clk"; 168*6a3a226eSMaxime Ripard reg = <0x01c20030 0x4>; 169*6a3a226eSMaxime Ripard clocks = <&osc3M>; 170*6a3a226eSMaxime Ripard clock-output-names = "pll7"; 171*6a3a226eSMaxime Ripard }; 172*6a3a226eSMaxime Ripard 173*6a3a226eSMaxime Ripard pll7x2: pll7x2-clk { 174*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-pll3-2x-clk"; 175*6a3a226eSMaxime Ripard #clock-cells = <0>; 176*6a3a226eSMaxime Ripard clock-div = <1>; 177*6a3a226eSMaxime Ripard clock-mult = <2>; 178*6a3a226eSMaxime Ripard clocks = <&pll7>; 179*6a3a226eSMaxime Ripard clock-output-names = "pll7-2x"; 180*6a3a226eSMaxime Ripard }; 181*6a3a226eSMaxime Ripard 182*6a3a226eSMaxime Ripard /* dummy is 200M */ 183*6a3a226eSMaxime Ripard cpu: cpu@01c20054 { 184*6a3a226eSMaxime Ripard #clock-cells = <0>; 185*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-cpu-clk"; 186*6a3a226eSMaxime Ripard reg = <0x01c20054 0x4>; 187*6a3a226eSMaxime Ripard clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 188*6a3a226eSMaxime Ripard clock-output-names = "cpu"; 189*6a3a226eSMaxime Ripard }; 190*6a3a226eSMaxime Ripard 191*6a3a226eSMaxime Ripard axi: axi@01c20054 { 192*6a3a226eSMaxime Ripard #clock-cells = <0>; 193*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-axi-clk"; 194*6a3a226eSMaxime Ripard reg = <0x01c20054 0x4>; 195*6a3a226eSMaxime Ripard clocks = <&cpu>; 196*6a3a226eSMaxime Ripard clock-output-names = "axi"; 197*6a3a226eSMaxime Ripard }; 198*6a3a226eSMaxime Ripard 199*6a3a226eSMaxime Ripard ahb: ahb@01c20054 { 200*6a3a226eSMaxime Ripard #clock-cells = <0>; 201*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-ahb-clk"; 202*6a3a226eSMaxime Ripard reg = <0x01c20054 0x4>; 203*6a3a226eSMaxime Ripard clocks = <&axi>, <&cpu>, <&pll6 1>; 204*6a3a226eSMaxime Ripard clock-output-names = "ahb"; 205*6a3a226eSMaxime Ripard /* 206*6a3a226eSMaxime Ripard * Use PLL6 as parent, instead of CPU/AXI 207*6a3a226eSMaxime Ripard * which has rate changes due to cpufreq 208*6a3a226eSMaxime Ripard */ 209*6a3a226eSMaxime Ripard assigned-clocks = <&ahb>; 210*6a3a226eSMaxime Ripard assigned-clock-parents = <&pll6 1>; 211*6a3a226eSMaxime Ripard }; 212*6a3a226eSMaxime Ripard 213*6a3a226eSMaxime Ripard apb0: apb0@01c20054 { 214*6a3a226eSMaxime Ripard #clock-cells = <0>; 215*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-apb0-clk"; 216*6a3a226eSMaxime Ripard reg = <0x01c20054 0x4>; 217*6a3a226eSMaxime Ripard clocks = <&ahb>; 218*6a3a226eSMaxime Ripard clock-output-names = "apb0"; 219*6a3a226eSMaxime Ripard }; 220*6a3a226eSMaxime Ripard 221*6a3a226eSMaxime Ripard apb1: clk@01c20058 { 222*6a3a226eSMaxime Ripard #clock-cells = <0>; 223*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-apb1-clk"; 224*6a3a226eSMaxime Ripard reg = <0x01c20058 0x4>; 225*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 226*6a3a226eSMaxime Ripard clock-output-names = "apb1"; 227*6a3a226eSMaxime Ripard }; 228*6a3a226eSMaxime Ripard 229*6a3a226eSMaxime Ripard axi_gates: clk@01c2005c { 230*6a3a226eSMaxime Ripard #clock-cells = <1>; 231*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-gates-clk"; 232*6a3a226eSMaxime Ripard reg = <0x01c2005c 0x4>; 233*6a3a226eSMaxime Ripard clocks = <&axi>; 234*6a3a226eSMaxime Ripard clock-indices = <0>; 235*6a3a226eSMaxime Ripard clock-output-names = "axi_dram"; 236*6a3a226eSMaxime Ripard }; 237*6a3a226eSMaxime Ripard 238*6a3a226eSMaxime Ripard ahb_gates: clk@01c20060 { 239*6a3a226eSMaxime Ripard #clock-cells = <1>; 240*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-ahb-gates-clk"; 241*6a3a226eSMaxime Ripard reg = <0x01c20060 0x8>; 242*6a3a226eSMaxime Ripard clocks = <&ahb>; 243*6a3a226eSMaxime Ripard clock-indices = <0>, <1>, 244*6a3a226eSMaxime Ripard <2>, <5>, <6>, 245*6a3a226eSMaxime Ripard <7>, <8>, <9>, 246*6a3a226eSMaxime Ripard <10>, <13>, 247*6a3a226eSMaxime Ripard <14>, <17>, <20>, 248*6a3a226eSMaxime Ripard <21>, <22>, 249*6a3a226eSMaxime Ripard <28>, <32>, <34>, 250*6a3a226eSMaxime Ripard <36>, <40>, <44>, 251*6a3a226eSMaxime Ripard <46>, <51>, 252*6a3a226eSMaxime Ripard <52>; 253*6a3a226eSMaxime Ripard clock-output-names = "ahb_usbotg", "ahb_ehci", 254*6a3a226eSMaxime Ripard "ahb_ohci", "ahb_ss", "ahb_dma", 255*6a3a226eSMaxime Ripard "ahb_bist", "ahb_mmc0", "ahb_mmc1", 256*6a3a226eSMaxime Ripard "ahb_mmc2", "ahb_nand", 257*6a3a226eSMaxime Ripard "ahb_sdram", "ahb_emac", "ahb_spi0", 258*6a3a226eSMaxime Ripard "ahb_spi1", "ahb_spi2", 259*6a3a226eSMaxime Ripard "ahb_hstimer", "ahb_ve", "ahb_tve", 260*6a3a226eSMaxime Ripard "ahb_lcd", "ahb_csi", "ahb_de_be", 261*6a3a226eSMaxime Ripard "ahb_de_fe", "ahb_iep", 262*6a3a226eSMaxime Ripard "ahb_mali400"; 263*6a3a226eSMaxime Ripard }; 264*6a3a226eSMaxime Ripard 265*6a3a226eSMaxime Ripard apb0_gates: clk@01c20068 { 266*6a3a226eSMaxime Ripard #clock-cells = <1>; 267*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-gates-clk"; 268*6a3a226eSMaxime Ripard reg = <0x01c20068 0x4>; 269*6a3a226eSMaxime Ripard clocks = <&apb0>; 270*6a3a226eSMaxime Ripard clock-indices = <0>, <3>, 271*6a3a226eSMaxime Ripard <5>, <6>; 272*6a3a226eSMaxime Ripard clock-output-names = "apb0_codec", "apb0_i2s0", 273*6a3a226eSMaxime Ripard "apb0_pio", "apb0_ir"; 274*6a3a226eSMaxime Ripard }; 275*6a3a226eSMaxime Ripard 276*6a3a226eSMaxime Ripard apb1_gates: clk@01c2006c { 277*6a3a226eSMaxime Ripard #clock-cells = <1>; 278*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-gates-clk"; 279*6a3a226eSMaxime Ripard reg = <0x01c2006c 0x4>; 280*6a3a226eSMaxime Ripard clocks = <&apb1>; 281*6a3a226eSMaxime Ripard clock-indices = <0>, <1>, 282*6a3a226eSMaxime Ripard <2>, <17>, 283*6a3a226eSMaxime Ripard <18>, <19>; 284*6a3a226eSMaxime Ripard clock-output-names = "apb1_i2c0", "apb1_i2c1", 285*6a3a226eSMaxime Ripard "apb1_i2c2", "apb1_uart1", 286*6a3a226eSMaxime Ripard "apb1_uart2", "apb1_uart3"; 287*6a3a226eSMaxime Ripard }; 288*6a3a226eSMaxime Ripard 289*6a3a226eSMaxime Ripard nand_clk: clk@01c20080 { 290*6a3a226eSMaxime Ripard #clock-cells = <0>; 291*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 292*6a3a226eSMaxime Ripard reg = <0x01c20080 0x4>; 293*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 294*6a3a226eSMaxime Ripard clock-output-names = "nand"; 295*6a3a226eSMaxime Ripard }; 296*6a3a226eSMaxime Ripard 297*6a3a226eSMaxime Ripard ms_clk: clk@01c20084 { 298*6a3a226eSMaxime Ripard #clock-cells = <0>; 299*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 300*6a3a226eSMaxime Ripard reg = <0x01c20084 0x4>; 301*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 302*6a3a226eSMaxime Ripard clock-output-names = "ms"; 303*6a3a226eSMaxime Ripard }; 304*6a3a226eSMaxime Ripard 305*6a3a226eSMaxime Ripard mmc0_clk: clk@01c20088 { 306*6a3a226eSMaxime Ripard #clock-cells = <1>; 307*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mmc-clk"; 308*6a3a226eSMaxime Ripard reg = <0x01c20088 0x4>; 309*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 310*6a3a226eSMaxime Ripard clock-output-names = "mmc0", 311*6a3a226eSMaxime Ripard "mmc0_output", 312*6a3a226eSMaxime Ripard "mmc0_sample"; 313*6a3a226eSMaxime Ripard }; 314*6a3a226eSMaxime Ripard 315*6a3a226eSMaxime Ripard mmc1_clk: clk@01c2008c { 316*6a3a226eSMaxime Ripard #clock-cells = <1>; 317*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mmc-clk"; 318*6a3a226eSMaxime Ripard reg = <0x01c2008c 0x4>; 319*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 320*6a3a226eSMaxime Ripard clock-output-names = "mmc1", 321*6a3a226eSMaxime Ripard "mmc1_output", 322*6a3a226eSMaxime Ripard "mmc1_sample"; 323*6a3a226eSMaxime Ripard }; 324*6a3a226eSMaxime Ripard 325*6a3a226eSMaxime Ripard mmc2_clk: clk@01c20090 { 326*6a3a226eSMaxime Ripard #clock-cells = <1>; 327*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mmc-clk"; 328*6a3a226eSMaxime Ripard reg = <0x01c20090 0x4>; 329*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 330*6a3a226eSMaxime Ripard clock-output-names = "mmc2", 331*6a3a226eSMaxime Ripard "mmc2_output", 332*6a3a226eSMaxime Ripard "mmc2_sample"; 333*6a3a226eSMaxime Ripard }; 334*6a3a226eSMaxime Ripard 335*6a3a226eSMaxime Ripard ts_clk: clk@01c20098 { 336*6a3a226eSMaxime Ripard #clock-cells = <0>; 337*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 338*6a3a226eSMaxime Ripard reg = <0x01c20098 0x4>; 339*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 340*6a3a226eSMaxime Ripard clock-output-names = "ts"; 341*6a3a226eSMaxime Ripard }; 342*6a3a226eSMaxime Ripard 343*6a3a226eSMaxime Ripard ss_clk: clk@01c2009c { 344*6a3a226eSMaxime Ripard #clock-cells = <0>; 345*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 346*6a3a226eSMaxime Ripard reg = <0x01c2009c 0x4>; 347*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 348*6a3a226eSMaxime Ripard clock-output-names = "ss"; 349*6a3a226eSMaxime Ripard }; 350*6a3a226eSMaxime Ripard 351*6a3a226eSMaxime Ripard spi0_clk: clk@01c200a0 { 352*6a3a226eSMaxime Ripard #clock-cells = <0>; 353*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 354*6a3a226eSMaxime Ripard reg = <0x01c200a0 0x4>; 355*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 356*6a3a226eSMaxime Ripard clock-output-names = "spi0"; 357*6a3a226eSMaxime Ripard }; 358*6a3a226eSMaxime Ripard 359*6a3a226eSMaxime Ripard spi1_clk: clk@01c200a4 { 360*6a3a226eSMaxime Ripard #clock-cells = <0>; 361*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 362*6a3a226eSMaxime Ripard reg = <0x01c200a4 0x4>; 363*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 364*6a3a226eSMaxime Ripard clock-output-names = "spi1"; 365*6a3a226eSMaxime Ripard }; 366*6a3a226eSMaxime Ripard 367*6a3a226eSMaxime Ripard spi2_clk: clk@01c200a8 { 368*6a3a226eSMaxime Ripard #clock-cells = <0>; 369*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 370*6a3a226eSMaxime Ripard reg = <0x01c200a8 0x4>; 371*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 372*6a3a226eSMaxime Ripard clock-output-names = "spi2"; 373*6a3a226eSMaxime Ripard }; 374*6a3a226eSMaxime Ripard 375*6a3a226eSMaxime Ripard ir0_clk: clk@01c200b0 { 376*6a3a226eSMaxime Ripard #clock-cells = <0>; 377*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod0-clk"; 378*6a3a226eSMaxime Ripard reg = <0x01c200b0 0x4>; 379*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 380*6a3a226eSMaxime Ripard clock-output-names = "ir0"; 381*6a3a226eSMaxime Ripard }; 382*6a3a226eSMaxime Ripard 383*6a3a226eSMaxime Ripard i2s0_clk: clk@01c200b8 { 384*6a3a226eSMaxime Ripard #clock-cells = <0>; 385*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod1-clk"; 386*6a3a226eSMaxime Ripard reg = <0x01c200b8 0x4>; 387*6a3a226eSMaxime Ripard clocks = <&pll2 SUN4I_A10_PLL2_8X>, 388*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_4X>, 389*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_2X>, 390*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_1X>; 391*6a3a226eSMaxime Ripard clock-output-names = "i2s0"; 392*6a3a226eSMaxime Ripard }; 393*6a3a226eSMaxime Ripard 394*6a3a226eSMaxime Ripard spdif_clk: clk@01c200c0 { 395*6a3a226eSMaxime Ripard #clock-cells = <0>; 396*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-mod1-clk"; 397*6a3a226eSMaxime Ripard reg = <0x01c200c0 0x4>; 398*6a3a226eSMaxime Ripard clocks = <&pll2 SUN4I_A10_PLL2_8X>, 399*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_4X>, 400*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_2X>, 401*6a3a226eSMaxime Ripard <&pll2 SUN4I_A10_PLL2_1X>; 402*6a3a226eSMaxime Ripard clock-output-names = "spdif"; 403*6a3a226eSMaxime Ripard }; 404*6a3a226eSMaxime Ripard 405*6a3a226eSMaxime Ripard usb_clk: clk@01c200cc { 406*6a3a226eSMaxime Ripard #clock-cells = <1>; 407*6a3a226eSMaxime Ripard #reset-cells = <1>; 408*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-usb-clk"; 409*6a3a226eSMaxime Ripard reg = <0x01c200cc 0x4>; 410*6a3a226eSMaxime Ripard clocks = <&pll6 1>; 411*6a3a226eSMaxime Ripard clock-output-names = "usb_ohci0", "usb_phy"; 412*6a3a226eSMaxime Ripard }; 413*6a3a226eSMaxime Ripard 414*6a3a226eSMaxime Ripard dram_gates: clk@01c20100 { 415*6a3a226eSMaxime Ripard #clock-cells = <1>; 416*6a3a226eSMaxime Ripard compatible = "nextthing,gr8-dram-gates-clk", 417*6a3a226eSMaxime Ripard "allwinner,sun4i-a10-gates-clk"; 418*6a3a226eSMaxime Ripard reg = <0x01c20100 0x4>; 419*6a3a226eSMaxime Ripard clocks = <&pll5 0>; 420*6a3a226eSMaxime Ripard clock-indices = <0>, 421*6a3a226eSMaxime Ripard <1>, 422*6a3a226eSMaxime Ripard <25>, 423*6a3a226eSMaxime Ripard <26>, 424*6a3a226eSMaxime Ripard <29>, 425*6a3a226eSMaxime Ripard <31>; 426*6a3a226eSMaxime Ripard clock-output-names = "dram_ve", 427*6a3a226eSMaxime Ripard "dram_csi", 428*6a3a226eSMaxime Ripard "dram_de_fe", 429*6a3a226eSMaxime Ripard "dram_de_be", 430*6a3a226eSMaxime Ripard "dram_ace", 431*6a3a226eSMaxime Ripard "dram_iep"; 432*6a3a226eSMaxime Ripard }; 433*6a3a226eSMaxime Ripard 434*6a3a226eSMaxime Ripard de_be_clk: clk@01c20104 { 435*6a3a226eSMaxime Ripard #clock-cells = <0>; 436*6a3a226eSMaxime Ripard #reset-cells = <0>; 437*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-display-clk"; 438*6a3a226eSMaxime Ripard reg = <0x01c20104 0x4>; 439*6a3a226eSMaxime Ripard clocks = <&pll3>, <&pll7>, <&pll5 1>; 440*6a3a226eSMaxime Ripard clock-output-names = "de-be"; 441*6a3a226eSMaxime Ripard }; 442*6a3a226eSMaxime Ripard 443*6a3a226eSMaxime Ripard de_fe_clk: clk@01c2010c { 444*6a3a226eSMaxime Ripard #clock-cells = <0>; 445*6a3a226eSMaxime Ripard #reset-cells = <0>; 446*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-display-clk"; 447*6a3a226eSMaxime Ripard reg = <0x01c2010c 0x4>; 448*6a3a226eSMaxime Ripard clocks = <&pll3>, <&pll7>, <&pll5 1>; 449*6a3a226eSMaxime Ripard clock-output-names = "de-fe"; 450*6a3a226eSMaxime Ripard }; 451*6a3a226eSMaxime Ripard 452*6a3a226eSMaxime Ripard tcon_ch0_clk: clk@01c20118 { 453*6a3a226eSMaxime Ripard #clock-cells = <0>; 454*6a3a226eSMaxime Ripard #reset-cells = <1>; 455*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; 456*6a3a226eSMaxime Ripard reg = <0x01c20118 0x4>; 457*6a3a226eSMaxime Ripard clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 458*6a3a226eSMaxime Ripard clock-output-names = "tcon-ch0-sclk"; 459*6a3a226eSMaxime Ripard }; 460*6a3a226eSMaxime Ripard 461*6a3a226eSMaxime Ripard tcon_ch1_clk: clk@01c2012c { 462*6a3a226eSMaxime Ripard #clock-cells = <0>; 463*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; 464*6a3a226eSMaxime Ripard reg = <0x01c2012c 0x4>; 465*6a3a226eSMaxime Ripard clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; 466*6a3a226eSMaxime Ripard clock-output-names = "tcon-ch1-sclk"; 467*6a3a226eSMaxime Ripard }; 468*6a3a226eSMaxime Ripard 469*6a3a226eSMaxime Ripard codec_clk: clk@01c20140 { 470*6a3a226eSMaxime Ripard #clock-cells = <0>; 471*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-codec-clk"; 472*6a3a226eSMaxime Ripard reg = <0x01c20140 0x4>; 473*6a3a226eSMaxime Ripard clocks = <&pll2 SUN4I_A10_PLL2_1X>; 474*6a3a226eSMaxime Ripard clock-output-names = "codec"; 475*6a3a226eSMaxime Ripard }; 476*6a3a226eSMaxime Ripard 477*6a3a226eSMaxime Ripard mbus_clk: clk@01c2015c { 478*6a3a226eSMaxime Ripard #clock-cells = <0>; 479*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-mbus-clk"; 480*6a3a226eSMaxime Ripard reg = <0x01c2015c 0x4>; 481*6a3a226eSMaxime Ripard clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 482*6a3a226eSMaxime Ripard clock-output-names = "mbus"; 483*6a3a226eSMaxime Ripard }; 484*6a3a226eSMaxime Ripard }; 485*6a3a226eSMaxime Ripard 486*6a3a226eSMaxime Ripard display-engine { 487*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-display-engine"; 488*6a3a226eSMaxime Ripard allwinner,pipelines = <&fe0>; 489*6a3a226eSMaxime Ripard }; 490*6a3a226eSMaxime Ripard 491*6a3a226eSMaxime Ripard soc@01c00000 { 492*6a3a226eSMaxime Ripard compatible = "simple-bus"; 493*6a3a226eSMaxime Ripard #address-cells = <1>; 494*6a3a226eSMaxime Ripard #size-cells = <1>; 495*6a3a226eSMaxime Ripard ranges; 496*6a3a226eSMaxime Ripard 497*6a3a226eSMaxime Ripard sram-controller@01c00000 { 498*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-sram-controller"; 499*6a3a226eSMaxime Ripard reg = <0x01c00000 0x30>; 500*6a3a226eSMaxime Ripard #address-cells = <1>; 501*6a3a226eSMaxime Ripard #size-cells = <1>; 502*6a3a226eSMaxime Ripard ranges; 503*6a3a226eSMaxime Ripard 504*6a3a226eSMaxime Ripard sram_a: sram@00000000 { 505*6a3a226eSMaxime Ripard compatible = "mmio-sram"; 506*6a3a226eSMaxime Ripard reg = <0x00000000 0xc000>; 507*6a3a226eSMaxime Ripard #address-cells = <1>; 508*6a3a226eSMaxime Ripard #size-cells = <1>; 509*6a3a226eSMaxime Ripard ranges = <0 0x00000000 0xc000>; 510*6a3a226eSMaxime Ripard }; 511*6a3a226eSMaxime Ripard 512*6a3a226eSMaxime Ripard sram_d: sram@00010000 { 513*6a3a226eSMaxime Ripard compatible = "mmio-sram"; 514*6a3a226eSMaxime Ripard reg = <0x00010000 0x1000>; 515*6a3a226eSMaxime Ripard #address-cells = <1>; 516*6a3a226eSMaxime Ripard #size-cells = <1>; 517*6a3a226eSMaxime Ripard ranges = <0 0x00010000 0x1000>; 518*6a3a226eSMaxime Ripard 519*6a3a226eSMaxime Ripard otg_sram: sram-section@0000 { 520*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-sram-d"; 521*6a3a226eSMaxime Ripard reg = <0x0000 0x1000>; 522*6a3a226eSMaxime Ripard status = "disabled"; 523*6a3a226eSMaxime Ripard }; 524*6a3a226eSMaxime Ripard }; 525*6a3a226eSMaxime Ripard }; 526*6a3a226eSMaxime Ripard 527*6a3a226eSMaxime Ripard dma: dma-controller@01c02000 { 528*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-dma"; 529*6a3a226eSMaxime Ripard reg = <0x01c02000 0x1000>; 530*6a3a226eSMaxime Ripard interrupts = <27>; 531*6a3a226eSMaxime Ripard clocks = <&ahb_gates 6>; 532*6a3a226eSMaxime Ripard #dma-cells = <2>; 533*6a3a226eSMaxime Ripard }; 534*6a3a226eSMaxime Ripard 535*6a3a226eSMaxime Ripard nfc: nand@01c03000 { 536*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-nand"; 537*6a3a226eSMaxime Ripard reg = <0x01c03000 0x1000>; 538*6a3a226eSMaxime Ripard interrupts = <37>; 539*6a3a226eSMaxime Ripard clocks = <&ahb_gates 13>, <&nand_clk>; 540*6a3a226eSMaxime Ripard clock-names = "ahb", "mod"; 541*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_DEDICATED 3>; 542*6a3a226eSMaxime Ripard dma-names = "rxtx"; 543*6a3a226eSMaxime Ripard status = "disabled"; 544*6a3a226eSMaxime Ripard #address-cells = <1>; 545*6a3a226eSMaxime Ripard #size-cells = <0>; 546*6a3a226eSMaxime Ripard }; 547*6a3a226eSMaxime Ripard 548*6a3a226eSMaxime Ripard spi0: spi@01c05000 { 549*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-spi"; 550*6a3a226eSMaxime Ripard reg = <0x01c05000 0x1000>; 551*6a3a226eSMaxime Ripard interrupts = <10>; 552*6a3a226eSMaxime Ripard clocks = <&ahb_gates 20>, <&spi0_clk>; 553*6a3a226eSMaxime Ripard clock-names = "ahb", "mod"; 554*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_DEDICATED 27>, 555*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_DEDICATED 26>; 556*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 557*6a3a226eSMaxime Ripard status = "disabled"; 558*6a3a226eSMaxime Ripard #address-cells = <1>; 559*6a3a226eSMaxime Ripard #size-cells = <0>; 560*6a3a226eSMaxime Ripard }; 561*6a3a226eSMaxime Ripard 562*6a3a226eSMaxime Ripard spi1: spi@01c06000 { 563*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-spi"; 564*6a3a226eSMaxime Ripard reg = <0x01c06000 0x1000>; 565*6a3a226eSMaxime Ripard interrupts = <11>; 566*6a3a226eSMaxime Ripard clocks = <&ahb_gates 21>, <&spi1_clk>; 567*6a3a226eSMaxime Ripard clock-names = "ahb", "mod"; 568*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_DEDICATED 9>, 569*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_DEDICATED 8>; 570*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 571*6a3a226eSMaxime Ripard status = "disabled"; 572*6a3a226eSMaxime Ripard #address-cells = <1>; 573*6a3a226eSMaxime Ripard #size-cells = <0>; 574*6a3a226eSMaxime Ripard }; 575*6a3a226eSMaxime Ripard 576*6a3a226eSMaxime Ripard tve0: tv-encoder@01c0a000 { 577*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-tv-encoder"; 578*6a3a226eSMaxime Ripard reg = <0x01c0a000 0x1000>; 579*6a3a226eSMaxime Ripard clocks = <&ahb_gates 34>; 580*6a3a226eSMaxime Ripard resets = <&tcon_ch0_clk 0>; 581*6a3a226eSMaxime Ripard status = "disabled"; 582*6a3a226eSMaxime Ripard 583*6a3a226eSMaxime Ripard port { 584*6a3a226eSMaxime Ripard #address-cells = <1>; 585*6a3a226eSMaxime Ripard #size-cells = <0>; 586*6a3a226eSMaxime Ripard 587*6a3a226eSMaxime Ripard tve0_in_tcon0: endpoint@0 { 588*6a3a226eSMaxime Ripard reg = <0>; 589*6a3a226eSMaxime Ripard remote-endpoint = <&tcon0_out_tve0>; 590*6a3a226eSMaxime Ripard }; 591*6a3a226eSMaxime Ripard }; 592*6a3a226eSMaxime Ripard }; 593*6a3a226eSMaxime Ripard 594*6a3a226eSMaxime Ripard tcon0: lcd-controller@01c0c000 { 595*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-tcon"; 596*6a3a226eSMaxime Ripard reg = <0x01c0c000 0x1000>; 597*6a3a226eSMaxime Ripard interrupts = <44>; 598*6a3a226eSMaxime Ripard resets = <&tcon_ch0_clk 1>; 599*6a3a226eSMaxime Ripard reset-names = "lcd"; 600*6a3a226eSMaxime Ripard clocks = <&ahb_gates 36>, 601*6a3a226eSMaxime Ripard <&tcon_ch0_clk>, 602*6a3a226eSMaxime Ripard <&tcon_ch1_clk>; 603*6a3a226eSMaxime Ripard clock-names = "ahb", 604*6a3a226eSMaxime Ripard "tcon-ch0", 605*6a3a226eSMaxime Ripard "tcon-ch1"; 606*6a3a226eSMaxime Ripard clock-output-names = "tcon-pixel-clock"; 607*6a3a226eSMaxime Ripard status = "disabled"; 608*6a3a226eSMaxime Ripard 609*6a3a226eSMaxime Ripard ports { 610*6a3a226eSMaxime Ripard #address-cells = <1>; 611*6a3a226eSMaxime Ripard #size-cells = <0>; 612*6a3a226eSMaxime Ripard 613*6a3a226eSMaxime Ripard tcon0_in: port@0 { 614*6a3a226eSMaxime Ripard #address-cells = <1>; 615*6a3a226eSMaxime Ripard #size-cells = <0>; 616*6a3a226eSMaxime Ripard reg = <0>; 617*6a3a226eSMaxime Ripard 618*6a3a226eSMaxime Ripard tcon0_in_be0: endpoint@0 { 619*6a3a226eSMaxime Ripard reg = <0>; 620*6a3a226eSMaxime Ripard remote-endpoint = <&be0_out_tcon0>; 621*6a3a226eSMaxime Ripard }; 622*6a3a226eSMaxime Ripard }; 623*6a3a226eSMaxime Ripard 624*6a3a226eSMaxime Ripard tcon0_out: port@1 { 625*6a3a226eSMaxime Ripard #address-cells = <1>; 626*6a3a226eSMaxime Ripard #size-cells = <0>; 627*6a3a226eSMaxime Ripard reg = <1>; 628*6a3a226eSMaxime Ripard 629*6a3a226eSMaxime Ripard tcon0_out_tve0: endpoint@1 { 630*6a3a226eSMaxime Ripard reg = <1>; 631*6a3a226eSMaxime Ripard remote-endpoint = <&tve0_in_tcon0>; 632*6a3a226eSMaxime Ripard }; 633*6a3a226eSMaxime Ripard }; 634*6a3a226eSMaxime Ripard }; 635*6a3a226eSMaxime Ripard }; 636*6a3a226eSMaxime Ripard 637*6a3a226eSMaxime Ripard mmc0: mmc@01c0f000 { 638*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-mmc"; 639*6a3a226eSMaxime Ripard reg = <0x01c0f000 0x1000>; 640*6a3a226eSMaxime Ripard clocks = <&ahb_gates 8>, 641*6a3a226eSMaxime Ripard <&mmc0_clk 0>, 642*6a3a226eSMaxime Ripard <&mmc0_clk 1>, 643*6a3a226eSMaxime Ripard <&mmc0_clk 2>; 644*6a3a226eSMaxime Ripard clock-names = "ahb", 645*6a3a226eSMaxime Ripard "mmc", 646*6a3a226eSMaxime Ripard "output", 647*6a3a226eSMaxime Ripard "sample"; 648*6a3a226eSMaxime Ripard interrupts = <32>; 649*6a3a226eSMaxime Ripard status = "disabled"; 650*6a3a226eSMaxime Ripard #address-cells = <1>; 651*6a3a226eSMaxime Ripard #size-cells = <0>; 652*6a3a226eSMaxime Ripard }; 653*6a3a226eSMaxime Ripard 654*6a3a226eSMaxime Ripard mmc1: mmc@01c10000 { 655*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-mmc"; 656*6a3a226eSMaxime Ripard reg = <0x01c10000 0x1000>; 657*6a3a226eSMaxime Ripard clocks = <&ahb_gates 9>, 658*6a3a226eSMaxime Ripard <&mmc1_clk 0>, 659*6a3a226eSMaxime Ripard <&mmc1_clk 1>, 660*6a3a226eSMaxime Ripard <&mmc1_clk 2>; 661*6a3a226eSMaxime Ripard clock-names = "ahb", 662*6a3a226eSMaxime Ripard "mmc", 663*6a3a226eSMaxime Ripard "output", 664*6a3a226eSMaxime Ripard "sample"; 665*6a3a226eSMaxime Ripard interrupts = <33>; 666*6a3a226eSMaxime Ripard status = "disabled"; 667*6a3a226eSMaxime Ripard #address-cells = <1>; 668*6a3a226eSMaxime Ripard #size-cells = <0>; 669*6a3a226eSMaxime Ripard }; 670*6a3a226eSMaxime Ripard 671*6a3a226eSMaxime Ripard mmc2: mmc@01c11000 { 672*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-mmc"; 673*6a3a226eSMaxime Ripard reg = <0x01c11000 0x1000>; 674*6a3a226eSMaxime Ripard clocks = <&ahb_gates 10>, 675*6a3a226eSMaxime Ripard <&mmc2_clk 0>, 676*6a3a226eSMaxime Ripard <&mmc2_clk 1>, 677*6a3a226eSMaxime Ripard <&mmc2_clk 2>; 678*6a3a226eSMaxime Ripard clock-names = "ahb", 679*6a3a226eSMaxime Ripard "mmc", 680*6a3a226eSMaxime Ripard "output", 681*6a3a226eSMaxime Ripard "sample"; 682*6a3a226eSMaxime Ripard interrupts = <34>; 683*6a3a226eSMaxime Ripard status = "disabled"; 684*6a3a226eSMaxime Ripard #address-cells = <1>; 685*6a3a226eSMaxime Ripard #size-cells = <0>; 686*6a3a226eSMaxime Ripard }; 687*6a3a226eSMaxime Ripard 688*6a3a226eSMaxime Ripard usb_otg: usb@01c13000 { 689*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-musb"; 690*6a3a226eSMaxime Ripard reg = <0x01c13000 0x0400>; 691*6a3a226eSMaxime Ripard clocks = <&ahb_gates 0>; 692*6a3a226eSMaxime Ripard interrupts = <38>; 693*6a3a226eSMaxime Ripard interrupt-names = "mc"; 694*6a3a226eSMaxime Ripard phys = <&usbphy 0>; 695*6a3a226eSMaxime Ripard phy-names = "usb"; 696*6a3a226eSMaxime Ripard extcon = <&usbphy 0>; 697*6a3a226eSMaxime Ripard allwinner,sram = <&otg_sram 1>; 698*6a3a226eSMaxime Ripard status = "disabled"; 699*6a3a226eSMaxime Ripard 700*6a3a226eSMaxime Ripard dr_mode = "otg"; 701*6a3a226eSMaxime Ripard }; 702*6a3a226eSMaxime Ripard 703*6a3a226eSMaxime Ripard usbphy: phy@01c13400 { 704*6a3a226eSMaxime Ripard #phy-cells = <1>; 705*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-usb-phy"; 706*6a3a226eSMaxime Ripard reg = <0x01c13400 0x10 0x01c14800 0x4>; 707*6a3a226eSMaxime Ripard reg-names = "phy_ctrl", "pmu1"; 708*6a3a226eSMaxime Ripard clocks = <&usb_clk 8>; 709*6a3a226eSMaxime Ripard clock-names = "usb_phy"; 710*6a3a226eSMaxime Ripard resets = <&usb_clk 0>, <&usb_clk 1>; 711*6a3a226eSMaxime Ripard reset-names = "usb0_reset", "usb1_reset"; 712*6a3a226eSMaxime Ripard status = "disabled"; 713*6a3a226eSMaxime Ripard }; 714*6a3a226eSMaxime Ripard 715*6a3a226eSMaxime Ripard ehci0: usb@01c14000 { 716*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 717*6a3a226eSMaxime Ripard reg = <0x01c14000 0x100>; 718*6a3a226eSMaxime Ripard interrupts = <39>; 719*6a3a226eSMaxime Ripard clocks = <&ahb_gates 1>; 720*6a3a226eSMaxime Ripard phys = <&usbphy 1>; 721*6a3a226eSMaxime Ripard phy-names = "usb"; 722*6a3a226eSMaxime Ripard status = "disabled"; 723*6a3a226eSMaxime Ripard }; 724*6a3a226eSMaxime Ripard 725*6a3a226eSMaxime Ripard ohci0: usb@01c14400 { 726*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 727*6a3a226eSMaxime Ripard reg = <0x01c14400 0x100>; 728*6a3a226eSMaxime Ripard interrupts = <40>; 729*6a3a226eSMaxime Ripard clocks = <&usb_clk 6>, <&ahb_gates 2>; 730*6a3a226eSMaxime Ripard phys = <&usbphy 1>; 731*6a3a226eSMaxime Ripard phy-names = "usb"; 732*6a3a226eSMaxime Ripard status = "disabled"; 733*6a3a226eSMaxime Ripard }; 734*6a3a226eSMaxime Ripard 735*6a3a226eSMaxime Ripard spi2: spi@01c17000 { 736*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-spi"; 737*6a3a226eSMaxime Ripard reg = <0x01c17000 0x1000>; 738*6a3a226eSMaxime Ripard interrupts = <12>; 739*6a3a226eSMaxime Ripard clocks = <&ahb_gates 22>, <&spi2_clk>; 740*6a3a226eSMaxime Ripard clock-names = "ahb", "mod"; 741*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_DEDICATED 29>, 742*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_DEDICATED 28>; 743*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 744*6a3a226eSMaxime Ripard status = "disabled"; 745*6a3a226eSMaxime Ripard #address-cells = <1>; 746*6a3a226eSMaxime Ripard #size-cells = <0>; 747*6a3a226eSMaxime Ripard }; 748*6a3a226eSMaxime Ripard 749*6a3a226eSMaxime Ripard intc: interrupt-controller@01c20400 { 750*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-ic"; 751*6a3a226eSMaxime Ripard reg = <0x01c20400 0x400>; 752*6a3a226eSMaxime Ripard interrupt-controller; 753*6a3a226eSMaxime Ripard #interrupt-cells = <1>; 754*6a3a226eSMaxime Ripard }; 755*6a3a226eSMaxime Ripard 756*6a3a226eSMaxime Ripard pio: pinctrl@01c20800 { 757*6a3a226eSMaxime Ripard compatible = "nextthing,gr8-pinctrl"; 758*6a3a226eSMaxime Ripard reg = <0x01c20800 0x400>; 759*6a3a226eSMaxime Ripard interrupts = <28>; 760*6a3a226eSMaxime Ripard clocks = <&apb0_gates 5>; 761*6a3a226eSMaxime Ripard gpio-controller; 762*6a3a226eSMaxime Ripard interrupt-controller; 763*6a3a226eSMaxime Ripard #interrupt-cells = <3>; 764*6a3a226eSMaxime Ripard #gpio-cells = <3>; 765*6a3a226eSMaxime Ripard 766*6a3a226eSMaxime Ripard i2c0_pins_a: i2c0@0 { 767*6a3a226eSMaxime Ripard allwinner,pins = "PB0", "PB1"; 768*6a3a226eSMaxime Ripard allwinner,function = "i2c0"; 769*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 770*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 771*6a3a226eSMaxime Ripard }; 772*6a3a226eSMaxime Ripard 773*6a3a226eSMaxime Ripard i2c1_pins_a: i2c1@0 { 774*6a3a226eSMaxime Ripard allwinner,pins = "PB15", "PB16"; 775*6a3a226eSMaxime Ripard allwinner,function = "i2c1"; 776*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 777*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 778*6a3a226eSMaxime Ripard }; 779*6a3a226eSMaxime Ripard 780*6a3a226eSMaxime Ripard i2c2_pins_a: i2c2@0 { 781*6a3a226eSMaxime Ripard allwinner,pins = "PB17", "PB18"; 782*6a3a226eSMaxime Ripard allwinner,function = "i2c2"; 783*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 784*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 785*6a3a226eSMaxime Ripard }; 786*6a3a226eSMaxime Ripard 787*6a3a226eSMaxime Ripard i2s0_data_pins_a: i2s0-data@0 { 788*6a3a226eSMaxime Ripard allwinner,pins = "PB6", "PB7", "PB8", "PB9"; 789*6a3a226eSMaxime Ripard allwinner,function = "i2s0"; 790*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 791*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 792*6a3a226eSMaxime Ripard }; 793*6a3a226eSMaxime Ripard 794*6a3a226eSMaxime Ripard i2s0_mclk_pins_a: i2s0-mclk@0 { 795*6a3a226eSMaxime Ripard allwinner,pins = "PB5"; 796*6a3a226eSMaxime Ripard allwinner,function = "i2s0"; 797*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 798*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 799*6a3a226eSMaxime Ripard }; 800*6a3a226eSMaxime Ripard 801*6a3a226eSMaxime Ripard ir0_rx_pins_a: ir0@0 { 802*6a3a226eSMaxime Ripard allwinner,pins = "PB4"; 803*6a3a226eSMaxime Ripard allwinner,function = "ir0"; 804*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 805*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 806*6a3a226eSMaxime Ripard }; 807*6a3a226eSMaxime Ripard 808*6a3a226eSMaxime Ripard lcd_rgb666_pins: lcd-rgb666@0 { 809*6a3a226eSMaxime Ripard allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 810*6a3a226eSMaxime Ripard "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 811*6a3a226eSMaxime Ripard "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 812*6a3a226eSMaxime Ripard "PD24", "PD25", "PD26", "PD27"; 813*6a3a226eSMaxime Ripard allwinner,function = "lcd0"; 814*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 815*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 816*6a3a226eSMaxime Ripard }; 817*6a3a226eSMaxime Ripard 818*6a3a226eSMaxime Ripard mmc0_pins_a: mmc0@0 { 819*6a3a226eSMaxime Ripard allwinner,pins = "PF0", "PF1", "PF2", "PF3", 820*6a3a226eSMaxime Ripard "PF4", "PF5"; 821*6a3a226eSMaxime Ripard allwinner,function = "mmc0"; 822*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_30_MA>; 823*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 824*6a3a226eSMaxime Ripard }; 825*6a3a226eSMaxime Ripard 826*6a3a226eSMaxime Ripard nand_pins_a: nand-base0@0 { 827*6a3a226eSMaxime Ripard allwinner,pins = "PC0", "PC1", "PC2", 828*6a3a226eSMaxime Ripard "PC5", "PC8", "PC9", "PC10", 829*6a3a226eSMaxime Ripard "PC11", "PC12", "PC13", "PC14", 830*6a3a226eSMaxime Ripard "PC15"; 831*6a3a226eSMaxime Ripard allwinner,function = "nand0"; 832*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 833*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 834*6a3a226eSMaxime Ripard }; 835*6a3a226eSMaxime Ripard 836*6a3a226eSMaxime Ripard nand_cs0_pins_a: nand-cs@0 { 837*6a3a226eSMaxime Ripard allwinner,pins = "PC4"; 838*6a3a226eSMaxime Ripard allwinner,function = "nand0"; 839*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 840*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 841*6a3a226eSMaxime Ripard }; 842*6a3a226eSMaxime Ripard 843*6a3a226eSMaxime Ripard nand_rb0_pins_a: nand-rb@0 { 844*6a3a226eSMaxime Ripard allwinner,pins = "PC6"; 845*6a3a226eSMaxime Ripard allwinner,function = "nand0"; 846*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 847*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 848*6a3a226eSMaxime Ripard }; 849*6a3a226eSMaxime Ripard 850*6a3a226eSMaxime Ripard pwm0_pins_a: pwm0@0 { 851*6a3a226eSMaxime Ripard allwinner,pins = "PB2"; 852*6a3a226eSMaxime Ripard allwinner,function = "pwm0"; 853*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 854*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 855*6a3a226eSMaxime Ripard }; 856*6a3a226eSMaxime Ripard 857*6a3a226eSMaxime Ripard pwm1_pins: pwm1 { 858*6a3a226eSMaxime Ripard allwinner,pins = "PG13"; 859*6a3a226eSMaxime Ripard allwinner,function = "pwm1"; 860*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 861*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 862*6a3a226eSMaxime Ripard }; 863*6a3a226eSMaxime Ripard 864*6a3a226eSMaxime Ripard spdif_tx_pins_a: spdif@0 { 865*6a3a226eSMaxime Ripard allwinner,pins = "PB10"; 866*6a3a226eSMaxime Ripard allwinner,function = "spdif"; 867*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 868*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; 869*6a3a226eSMaxime Ripard }; 870*6a3a226eSMaxime Ripard 871*6a3a226eSMaxime Ripard uart1_pins_a: uart1@1 { 872*6a3a226eSMaxime Ripard allwinner,pins = "PG3", "PG4"; 873*6a3a226eSMaxime Ripard allwinner,function = "uart1"; 874*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 875*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 876*6a3a226eSMaxime Ripard }; 877*6a3a226eSMaxime Ripard 878*6a3a226eSMaxime Ripard uart1_cts_rts_pins_a: uart1-cts-rts@0 { 879*6a3a226eSMaxime Ripard allwinner,pins = "PG5", "PG6"; 880*6a3a226eSMaxime Ripard allwinner,function = "uart1"; 881*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 882*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 883*6a3a226eSMaxime Ripard }; 884*6a3a226eSMaxime Ripard 885*6a3a226eSMaxime Ripard uart2_pins_a: uart2@1 { 886*6a3a226eSMaxime Ripard allwinner,pins = "PD2", "PD3"; 887*6a3a226eSMaxime Ripard allwinner,function = "uart2"; 888*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 889*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 890*6a3a226eSMaxime Ripard }; 891*6a3a226eSMaxime Ripard 892*6a3a226eSMaxime Ripard uart2_cts_rts_pins_a: uart2-cts-rts@0 { 893*6a3a226eSMaxime Ripard allwinner,pins = "PD4", "PD5"; 894*6a3a226eSMaxime Ripard allwinner,function = "uart2"; 895*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 896*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 897*6a3a226eSMaxime Ripard }; 898*6a3a226eSMaxime Ripard 899*6a3a226eSMaxime Ripard uart3_pins_a: uart3@1 { 900*6a3a226eSMaxime Ripard allwinner,pins = "PG9", "PG10"; 901*6a3a226eSMaxime Ripard allwinner,function = "uart3"; 902*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 903*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 904*6a3a226eSMaxime Ripard }; 905*6a3a226eSMaxime Ripard 906*6a3a226eSMaxime Ripard uart3_cts_rts_pins_a: uart3-cts-rts@0 { 907*6a3a226eSMaxime Ripard allwinner,pins = "PG11", "PG12"; 908*6a3a226eSMaxime Ripard allwinner,function = "uart3"; 909*6a3a226eSMaxime Ripard allwinner,drive = <SUN4I_PINCTRL_10_MA>; 910*6a3a226eSMaxime Ripard allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 911*6a3a226eSMaxime Ripard }; 912*6a3a226eSMaxime Ripard }; 913*6a3a226eSMaxime Ripard 914*6a3a226eSMaxime Ripard pwm: pwm@01c20e00 { 915*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a10s-pwm"; 916*6a3a226eSMaxime Ripard reg = <0x01c20e00 0xc>; 917*6a3a226eSMaxime Ripard clocks = <&osc24M>; 918*6a3a226eSMaxime Ripard #pwm-cells = <3>; 919*6a3a226eSMaxime Ripard status = "disabled"; 920*6a3a226eSMaxime Ripard }; 921*6a3a226eSMaxime Ripard 922*6a3a226eSMaxime Ripard timer@01c20c00 { 923*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-timer"; 924*6a3a226eSMaxime Ripard reg = <0x01c20c00 0x90>; 925*6a3a226eSMaxime Ripard interrupts = <22>; 926*6a3a226eSMaxime Ripard clocks = <&osc24M>; 927*6a3a226eSMaxime Ripard }; 928*6a3a226eSMaxime Ripard 929*6a3a226eSMaxime Ripard wdt: watchdog@01c20c90 { 930*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-wdt"; 931*6a3a226eSMaxime Ripard reg = <0x01c20c90 0x10>; 932*6a3a226eSMaxime Ripard }; 933*6a3a226eSMaxime Ripard 934*6a3a226eSMaxime Ripard spdif: spdif@01c21000 { 935*6a3a226eSMaxime Ripard #sound-dai-cells = <0>; 936*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-spdif"; 937*6a3a226eSMaxime Ripard reg = <0x01c21000 0x400>; 938*6a3a226eSMaxime Ripard interrupts = <13>; 939*6a3a226eSMaxime Ripard clocks = <&apb0_gates 1>, <&spdif_clk>; 940*6a3a226eSMaxime Ripard clock-names = "apb", "spdif"; 941*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_NORMAL 2>, 942*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_NORMAL 2>; 943*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 944*6a3a226eSMaxime Ripard status = "disabled"; 945*6a3a226eSMaxime Ripard }; 946*6a3a226eSMaxime Ripard 947*6a3a226eSMaxime Ripard ir0: ir@01c21800 { 948*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-ir"; 949*6a3a226eSMaxime Ripard clocks = <&apb0_gates 6>, <&ir0_clk>; 950*6a3a226eSMaxime Ripard clock-names = "apb", "ir"; 951*6a3a226eSMaxime Ripard interrupts = <5>; 952*6a3a226eSMaxime Ripard reg = <0x01c21800 0x40>; 953*6a3a226eSMaxime Ripard status = "disabled"; 954*6a3a226eSMaxime Ripard }; 955*6a3a226eSMaxime Ripard 956*6a3a226eSMaxime Ripard i2s0: i2s@01c22400 { 957*6a3a226eSMaxime Ripard #sound-dai-cells = <0>; 958*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-i2s"; 959*6a3a226eSMaxime Ripard reg = <0x01c22400 0x400>; 960*6a3a226eSMaxime Ripard interrupts = <16>; 961*6a3a226eSMaxime Ripard clocks = <&apb0_gates 3>, <&i2s0_clk>; 962*6a3a226eSMaxime Ripard clock-names = "apb", "mod"; 963*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_NORMAL 3>, 964*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_NORMAL 3>; 965*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 966*6a3a226eSMaxime Ripard status = "disabled"; 967*6a3a226eSMaxime Ripard }; 968*6a3a226eSMaxime Ripard 969*6a3a226eSMaxime Ripard lradc: lradc@01c22800 { 970*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-lradc-keys"; 971*6a3a226eSMaxime Ripard reg = <0x01c22800 0x100>; 972*6a3a226eSMaxime Ripard interrupts = <31>; 973*6a3a226eSMaxime Ripard status = "disabled"; 974*6a3a226eSMaxime Ripard }; 975*6a3a226eSMaxime Ripard 976*6a3a226eSMaxime Ripard codec: codec@01c22c00 { 977*6a3a226eSMaxime Ripard #sound-dai-cells = <0>; 978*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-codec"; 979*6a3a226eSMaxime Ripard reg = <0x01c22c00 0x40>; 980*6a3a226eSMaxime Ripard interrupts = <30>; 981*6a3a226eSMaxime Ripard clocks = <&apb0_gates 0>, <&codec_clk>; 982*6a3a226eSMaxime Ripard clock-names = "apb", "codec"; 983*6a3a226eSMaxime Ripard dmas = <&dma SUN4I_DMA_NORMAL 19>, 984*6a3a226eSMaxime Ripard <&dma SUN4I_DMA_NORMAL 19>; 985*6a3a226eSMaxime Ripard dma-names = "rx", "tx"; 986*6a3a226eSMaxime Ripard status = "disabled"; 987*6a3a226eSMaxime Ripard }; 988*6a3a226eSMaxime Ripard 989*6a3a226eSMaxime Ripard rtp: rtp@01c25000 { 990*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-ts"; 991*6a3a226eSMaxime Ripard reg = <0x01c25000 0x100>; 992*6a3a226eSMaxime Ripard interrupts = <29>; 993*6a3a226eSMaxime Ripard #thermal-sensor-cells = <0>; 994*6a3a226eSMaxime Ripard }; 995*6a3a226eSMaxime Ripard 996*6a3a226eSMaxime Ripard uart1: serial@01c28400 { 997*6a3a226eSMaxime Ripard compatible = "snps,dw-apb-uart"; 998*6a3a226eSMaxime Ripard reg = <0x01c28400 0x400>; 999*6a3a226eSMaxime Ripard interrupts = <2>; 1000*6a3a226eSMaxime Ripard reg-shift = <2>; 1001*6a3a226eSMaxime Ripard reg-io-width = <4>; 1002*6a3a226eSMaxime Ripard clocks = <&apb1_gates 17>; 1003*6a3a226eSMaxime Ripard status = "disabled"; 1004*6a3a226eSMaxime Ripard }; 1005*6a3a226eSMaxime Ripard 1006*6a3a226eSMaxime Ripard uart2: serial@01c28800 { 1007*6a3a226eSMaxime Ripard compatible = "snps,dw-apb-uart"; 1008*6a3a226eSMaxime Ripard reg = <0x01c28800 0x400>; 1009*6a3a226eSMaxime Ripard interrupts = <3>; 1010*6a3a226eSMaxime Ripard reg-shift = <2>; 1011*6a3a226eSMaxime Ripard reg-io-width = <4>; 1012*6a3a226eSMaxime Ripard clocks = <&apb1_gates 18>; 1013*6a3a226eSMaxime Ripard status = "disabled"; 1014*6a3a226eSMaxime Ripard }; 1015*6a3a226eSMaxime Ripard 1016*6a3a226eSMaxime Ripard uart3: serial@01c28c00 { 1017*6a3a226eSMaxime Ripard compatible = "snps,dw-apb-uart"; 1018*6a3a226eSMaxime Ripard reg = <0x01c28c00 0x400>; 1019*6a3a226eSMaxime Ripard interrupts = <4>; 1020*6a3a226eSMaxime Ripard reg-shift = <2>; 1021*6a3a226eSMaxime Ripard reg-io-width = <4>; 1022*6a3a226eSMaxime Ripard clocks = <&apb1_gates 19>; 1023*6a3a226eSMaxime Ripard status = "disabled"; 1024*6a3a226eSMaxime Ripard }; 1025*6a3a226eSMaxime Ripard 1026*6a3a226eSMaxime Ripard i2c0: i2c@01c2ac00 { 1027*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-i2c"; 1028*6a3a226eSMaxime Ripard reg = <0x01c2ac00 0x400>; 1029*6a3a226eSMaxime Ripard interrupts = <7>; 1030*6a3a226eSMaxime Ripard clocks = <&apb1_gates 0>; 1031*6a3a226eSMaxime Ripard status = "disabled"; 1032*6a3a226eSMaxime Ripard #address-cells = <1>; 1033*6a3a226eSMaxime Ripard #size-cells = <0>; 1034*6a3a226eSMaxime Ripard }; 1035*6a3a226eSMaxime Ripard 1036*6a3a226eSMaxime Ripard i2c1: i2c@01c2b000 { 1037*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-i2c"; 1038*6a3a226eSMaxime Ripard reg = <0x01c2b000 0x400>; 1039*6a3a226eSMaxime Ripard interrupts = <8>; 1040*6a3a226eSMaxime Ripard clocks = <&apb1_gates 1>; 1041*6a3a226eSMaxime Ripard status = "disabled"; 1042*6a3a226eSMaxime Ripard #address-cells = <1>; 1043*6a3a226eSMaxime Ripard #size-cells = <0>; 1044*6a3a226eSMaxime Ripard }; 1045*6a3a226eSMaxime Ripard 1046*6a3a226eSMaxime Ripard i2c2: i2c@01c2b400 { 1047*6a3a226eSMaxime Ripard compatible = "allwinner,sun4i-a10-i2c"; 1048*6a3a226eSMaxime Ripard reg = <0x01c2b400 0x400>; 1049*6a3a226eSMaxime Ripard interrupts = <9>; 1050*6a3a226eSMaxime Ripard clocks = <&apb1_gates 2>; 1051*6a3a226eSMaxime Ripard status = "disabled"; 1052*6a3a226eSMaxime Ripard #address-cells = <1>; 1053*6a3a226eSMaxime Ripard #size-cells = <0>; 1054*6a3a226eSMaxime Ripard }; 1055*6a3a226eSMaxime Ripard 1056*6a3a226eSMaxime Ripard timer@01c60000 { 1057*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-hstimer"; 1058*6a3a226eSMaxime Ripard reg = <0x01c60000 0x1000>; 1059*6a3a226eSMaxime Ripard interrupts = <82>, <83>; 1060*6a3a226eSMaxime Ripard clocks = <&ahb_gates 28>; 1061*6a3a226eSMaxime Ripard }; 1062*6a3a226eSMaxime Ripard 1063*6a3a226eSMaxime Ripard fe0: display-frontend@01e00000 { 1064*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-display-frontend"; 1065*6a3a226eSMaxime Ripard reg = <0x01e00000 0x20000>; 1066*6a3a226eSMaxime Ripard interrupts = <47>; 1067*6a3a226eSMaxime Ripard clocks = <&ahb_gates 46>, <&de_fe_clk>, 1068*6a3a226eSMaxime Ripard <&dram_gates 25>; 1069*6a3a226eSMaxime Ripard clock-names = "ahb", "mod", 1070*6a3a226eSMaxime Ripard "ram"; 1071*6a3a226eSMaxime Ripard resets = <&de_fe_clk>; 1072*6a3a226eSMaxime Ripard status = "disabled"; 1073*6a3a226eSMaxime Ripard 1074*6a3a226eSMaxime Ripard ports { 1075*6a3a226eSMaxime Ripard #address-cells = <1>; 1076*6a3a226eSMaxime Ripard #size-cells = <0>; 1077*6a3a226eSMaxime Ripard 1078*6a3a226eSMaxime Ripard fe0_out: port@1 { 1079*6a3a226eSMaxime Ripard #address-cells = <1>; 1080*6a3a226eSMaxime Ripard #size-cells = <0>; 1081*6a3a226eSMaxime Ripard reg = <1>; 1082*6a3a226eSMaxime Ripard 1083*6a3a226eSMaxime Ripard fe0_out_be0: endpoint@0 { 1084*6a3a226eSMaxime Ripard reg = <0>; 1085*6a3a226eSMaxime Ripard remote-endpoint = <&be0_in_fe0>; 1086*6a3a226eSMaxime Ripard }; 1087*6a3a226eSMaxime Ripard }; 1088*6a3a226eSMaxime Ripard }; 1089*6a3a226eSMaxime Ripard }; 1090*6a3a226eSMaxime Ripard 1091*6a3a226eSMaxime Ripard be0: display-backend@01e60000 { 1092*6a3a226eSMaxime Ripard compatible = "allwinner,sun5i-a13-display-backend"; 1093*6a3a226eSMaxime Ripard reg = <0x01e60000 0x10000>; 1094*6a3a226eSMaxime Ripard clocks = <&ahb_gates 44>, <&de_be_clk>, 1095*6a3a226eSMaxime Ripard <&dram_gates 26>; 1096*6a3a226eSMaxime Ripard clock-names = "ahb", "mod", 1097*6a3a226eSMaxime Ripard "ram"; 1098*6a3a226eSMaxime Ripard resets = <&de_be_clk>; 1099*6a3a226eSMaxime Ripard status = "disabled"; 1100*6a3a226eSMaxime Ripard 1101*6a3a226eSMaxime Ripard assigned-clocks = <&de_be_clk>; 1102*6a3a226eSMaxime Ripard assigned-clock-rates = <300000000>; 1103*6a3a226eSMaxime Ripard 1104*6a3a226eSMaxime Ripard ports { 1105*6a3a226eSMaxime Ripard #address-cells = <1>; 1106*6a3a226eSMaxime Ripard #size-cells = <0>; 1107*6a3a226eSMaxime Ripard 1108*6a3a226eSMaxime Ripard be0_in: port@0 { 1109*6a3a226eSMaxime Ripard #address-cells = <1>; 1110*6a3a226eSMaxime Ripard #size-cells = <0>; 1111*6a3a226eSMaxime Ripard reg = <0>; 1112*6a3a226eSMaxime Ripard 1113*6a3a226eSMaxime Ripard be0_in_fe0: endpoint@0 { 1114*6a3a226eSMaxime Ripard reg = <0>; 1115*6a3a226eSMaxime Ripard remote-endpoint = <&fe0_out_be0>; 1116*6a3a226eSMaxime Ripard }; 1117*6a3a226eSMaxime Ripard }; 1118*6a3a226eSMaxime Ripard 1119*6a3a226eSMaxime Ripard be0_out: port@1 { 1120*6a3a226eSMaxime Ripard #address-cells = <1>; 1121*6a3a226eSMaxime Ripard #size-cells = <0>; 1122*6a3a226eSMaxime Ripard reg = <1>; 1123*6a3a226eSMaxime Ripard 1124*6a3a226eSMaxime Ripard be0_out_tcon0: endpoint@0 { 1125*6a3a226eSMaxime Ripard reg = <0>; 1126*6a3a226eSMaxime Ripard remote-endpoint = <&tcon0_in_be0>; 1127*6a3a226eSMaxime Ripard }; 1128*6a3a226eSMaxime Ripard }; 1129*6a3a226eSMaxime Ripard }; 1130*6a3a226eSMaxime Ripard }; 1131*6a3a226eSMaxime Ripard }; 1132*6a3a226eSMaxime Ripard}; 1133