xref: /openbmc/u-boot/arch/arm/dts/sun5i-a13.dtsi (revision 60570df1)
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This library is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This library is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 *     You should have received a copy of the GNU General Public
22 *     License along with this library; if not, write to the Free
23 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 *     MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 *  b) Permission is hereby granted, free of charge, to any person
29 *     obtaining a copy of this software and associated documentation
30 *     files (the "Software"), to deal in the Software without
31 *     restriction, including without limitation the rights to use,
32 *     copy, modify, merge, publish, distribute, sublicense, and/or
33 *     sell copies of the Software, and to permit persons to whom the
34 *     Software is furnished to do so, subject to the following
35 *     conditions:
36 *
37 *     The above copyright notice and this permission notice shall be
38 *     included in all copies or substantial portions of the Software.
39 *
40 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 *     OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50#include "skeleton.dtsi"
51
52#include "sun5i.dtsi"
53
54#include <dt-bindings/pinctrl/sun4i-a10.h>
55#include <dt-bindings/thermal/thermal.h>
56
57/ {
58	interrupt-parent = <&intc>;
59
60	chosen {
61		#address-cells = <1>;
62		#size-cells = <1>;
63		ranges;
64
65		framebuffer@0 {
66			compatible = "allwinner,simple-framebuffer",
67				     "simple-framebuffer";
68			allwinner,pipeline = "de_be0-lcd0";
69			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
70			status = "disabled";
71		};
72	};
73
74	thermal-zones {
75		cpu_thermal {
76			/* milliseconds */
77			polling-delay-passive = <250>;
78			polling-delay = <1000>;
79			thermal-sensors = <&rtp>;
80
81			cooling-maps {
82				map0 {
83					trip = <&cpu_alert0>;
84					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
85				};
86			};
87
88			trips {
89				cpu_alert0: cpu_alert0 {
90					/* milliCelsius */
91					temperature = <850000>;
92					hysteresis = <2000>;
93					type = "passive";
94				};
95
96				cpu_crit: cpu_crit {
97					/* milliCelsius */
98					temperature = <100000>;
99					hysteresis = <2000>;
100					type = "critical";
101				};
102			};
103		};
104	};
105
106	clocks {
107		ahb_gates: clk@01c20060 {
108			#clock-cells = <1>;
109			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
110			reg = <0x01c20060 0x8>;
111			clocks = <&ahb>;
112			clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
113				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
114				"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
115				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
116				"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
117				"ahb_de_fe", "ahb_iep", "ahb_mali400";
118		};
119
120		apb0_gates: clk@01c20068 {
121			#clock-cells = <1>;
122			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
123			reg = <0x01c20068 0x4>;
124			clocks = <&apb0>;
125			clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
126		};
127
128		apb1_gates: clk@01c2006c {
129			#clock-cells = <1>;
130			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
131			reg = <0x01c2006c 0x4>;
132			clocks = <&apb1>;
133			clock-output-names = "apb1_i2c0", "apb1_i2c1",
134				"apb1_i2c2", "apb1_uart1", "apb1_uart3";
135		};
136	};
137};
138
139&cpu0 {
140	clock-latency = <244144>; /* 8 32k periods */
141	operating-points = <
142		/* kHz    uV */
143		1008000 1400000
144		912000  1350000
145		864000  1300000
146		624000  1200000
147		576000  1200000
148		432000  1200000
149		>;
150	#cooling-cells = <2>;
151	cooling-min-level = <0>;
152	cooling-max-level = <5>;
153};
154
155&pio {
156	compatible = "allwinner,sun5i-a13-pinctrl";
157
158	uart1_pins_a: uart1@0 {
159		allwinner,pins = "PE10", "PE11";
160		allwinner,function = "uart1";
161		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
162		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
163	};
164
165	uart1_pins_b: uart1@1 {
166		allwinner,pins = "PG3", "PG4";
167		allwinner,function = "uart1";
168		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
169		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
170	};
171};
172