1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 next-level-cache = <&L2>; 92 }; 93 94 cpu1: cpu@1 { 95 compatible = "arm,cortex-a53", "arm,armv8"; 96 device_type = "cpu"; 97 reg = <1>; 98 enable-method = "psci"; 99 next-level-cache = <&L2>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <2>; 106 enable-method = "psci"; 107 next-level-cache = <&L2>; 108 }; 109 110 cpu3: cpu@3 { 111 compatible = "arm,cortex-a53", "arm,armv8"; 112 device_type = "cpu"; 113 reg = <3>; 114 enable-method = "psci"; 115 next-level-cache = <&L2>; 116 }; 117 118 L2: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 }; 122 }; 123 124 de: display-engine { 125 compatible = "allwinner,sun50i-a64-display-engine"; 126 allwinner,pipelines = <&mixer0>, 127 <&mixer1>; 128 status = "disabled"; 129 }; 130 131 osc24M: osc24M_clk { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc24M"; 136 }; 137 138 osc32k: osc32k_clk { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <32768>; 142 clock-output-names = "osc32k"; 143 }; 144 145 iosc: internal-osc-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <16000000>; 149 clock-accuracy = <300000000>; 150 clock-output-names = "iosc"; 151 }; 152 153 psci { 154 compatible = "arm,psci-0.2"; 155 method = "smc"; 156 }; 157 158 sound_spdif { 159 compatible = "simple-audio-card"; 160 simple-audio-card,name = "On-board SPDIF"; 161 162 simple-audio-card,cpu { 163 sound-dai = <&spdif>; 164 }; 165 166 simple-audio-card,codec { 167 sound-dai = <&spdif_out>; 168 }; 169 }; 170 171 spdif_out: spdif-out { 172 #sound-dai-cells = <0>; 173 compatible = "linux,spdif-dit"; 174 }; 175 176 timer { 177 compatible = "arm,armv8-timer"; 178 interrupts = <GIC_PPI 13 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 14 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 182 <GIC_PPI 11 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 184 <GIC_PPI 10 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 soc { 189 compatible = "simple-bus"; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges; 193 194 de2@1000000 { 195 compatible = "allwinner,sun50i-a64-de2"; 196 reg = <0x1000000 0x400000>; 197 allwinner,sram = <&de2_sram 1>; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0 0x1000000 0x400000>; 201 202 display_clocks: clock@0 { 203 compatible = "allwinner,sun50i-a64-de2-clk"; 204 reg = <0x0 0x100000>; 205 clocks = <&ccu CLK_DE>, 206 <&ccu CLK_BUS_DE>; 207 clock-names = "mod", 208 "bus"; 209 resets = <&ccu RST_BUS_DE>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 }; 213 214 mixer0: mixer@100000 { 215 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 216 reg = <0x100000 0x100000>; 217 clocks = <&display_clocks CLK_BUS_MIXER0>, 218 <&display_clocks CLK_MIXER0>; 219 clock-names = "bus", 220 "mod"; 221 resets = <&display_clocks RST_MIXER0>; 222 223 ports { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 mixer0_out: port@1 { 228 reg = <1>; 229 230 mixer0_out_tcon0: endpoint { 231 remote-endpoint = <&tcon0_in_mixer0>; 232 }; 233 }; 234 }; 235 }; 236 237 mixer1: mixer@200000 { 238 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 239 reg = <0x200000 0x100000>; 240 clocks = <&display_clocks CLK_BUS_MIXER1>, 241 <&display_clocks CLK_MIXER1>; 242 clock-names = "bus", 243 "mod"; 244 resets = <&display_clocks RST_MIXER1>; 245 246 ports { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 mixer1_out: port@1 { 251 reg = <1>; 252 253 mixer1_out_tcon1: endpoint { 254 remote-endpoint = <&tcon1_in_mixer1>; 255 }; 256 }; 257 }; 258 }; 259 }; 260 261 syscon: syscon@1c00000 { 262 compatible = "allwinner,sun50i-a64-system-control", 263 "syscon"; 264 reg = <0x01c00000 0x1000>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 269 sram_c: sram@18000 { 270 compatible = "mmio-sram"; 271 reg = <0x00018000 0x28000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0 0x00018000 0x28000>; 275 276 de2_sram: sram-section@0 { 277 compatible = "allwinner,sun50i-a64-sram-c"; 278 reg = <0x0000 0x28000>; 279 }; 280 }; 281 }; 282 283 dma: dma-controller@1c02000 { 284 compatible = "allwinner,sun50i-a64-dma"; 285 reg = <0x01c02000 0x1000>; 286 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&ccu CLK_BUS_DMA>; 288 dma-channels = <8>; 289 dma-requests = <27>; 290 resets = <&ccu RST_BUS_DMA>; 291 #dma-cells = <1>; 292 }; 293 294 tcon0: lcd-controller@1c0c000 { 295 compatible = "allwinner,sun50i-a64-tcon-lcd", 296 "allwinner,sun8i-a83t-tcon-lcd"; 297 reg = <0x01c0c000 0x1000>; 298 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 300 clock-names = "ahb", "tcon-ch0"; 301 clock-output-names = "tcon-pixel-clock"; 302 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 303 reset-names = "lcd", "lvds"; 304 305 ports { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 tcon0_in: port@0 { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 reg = <0>; 313 314 tcon0_in_mixer0: endpoint@0 { 315 reg = <0>; 316 remote-endpoint = <&mixer0_out_tcon0>; 317 }; 318 }; 319 320 tcon0_out: port@1 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <1>; 324 }; 325 }; 326 }; 327 328 tcon1: lcd-controller@1c0d000 { 329 compatible = "allwinner,sun50i-a64-tcon-tv", 330 "allwinner,sun8i-a83t-tcon-tv"; 331 reg = <0x01c0d000 0x1000>; 332 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 334 clock-names = "ahb", "tcon-ch1"; 335 resets = <&ccu RST_BUS_TCON1>; 336 reset-names = "lcd"; 337 338 ports { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 tcon1_in: port@0 { 343 reg = <0>; 344 345 tcon1_in_mixer1: endpoint { 346 remote-endpoint = <&mixer1_out_tcon1>; 347 }; 348 }; 349 350 tcon1_out: port@1 { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <1>; 354 355 tcon1_out_hdmi: endpoint@1 { 356 reg = <1>; 357 remote-endpoint = <&hdmi_in_tcon1>; 358 }; 359 }; 360 }; 361 }; 362 363 mmc0: mmc@1c0f000 { 364 compatible = "allwinner,sun50i-a64-mmc"; 365 reg = <0x01c0f000 0x1000>; 366 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 367 clock-names = "ahb", "mmc"; 368 resets = <&ccu RST_BUS_MMC0>; 369 reset-names = "ahb"; 370 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 371 max-frequency = <150000000>; 372 status = "disabled"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 }; 376 377 mmc1: mmc@1c10000 { 378 compatible = "allwinner,sun50i-a64-mmc"; 379 reg = <0x01c10000 0x1000>; 380 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 381 clock-names = "ahb", "mmc"; 382 resets = <&ccu RST_BUS_MMC1>; 383 reset-names = "ahb"; 384 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 385 max-frequency = <150000000>; 386 status = "disabled"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 }; 390 391 mmc2: mmc@1c11000 { 392 compatible = "allwinner,sun50i-a64-emmc"; 393 reg = <0x01c11000 0x1000>; 394 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 395 clock-names = "ahb", "mmc"; 396 resets = <&ccu RST_BUS_MMC2>; 397 reset-names = "ahb"; 398 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 399 max-frequency = <200000000>; 400 status = "disabled"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 }; 404 405 sid: eeprom@1c14000 { 406 compatible = "allwinner,sun50i-a64-sid"; 407 reg = <0x1c14000 0x400>; 408 }; 409 410 usb_otg: usb@1c19000 { 411 compatible = "allwinner,sun8i-a33-musb"; 412 reg = <0x01c19000 0x0400>; 413 clocks = <&ccu CLK_BUS_OTG>; 414 resets = <&ccu RST_BUS_OTG>; 415 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "mc"; 417 phys = <&usbphy 0>; 418 phy-names = "usb"; 419 extcon = <&usbphy 0>; 420 status = "disabled"; 421 }; 422 423 usbphy: phy@1c19400 { 424 compatible = "allwinner,sun50i-a64-usb-phy"; 425 reg = <0x01c19400 0x14>, 426 <0x01c1a800 0x4>, 427 <0x01c1b800 0x4>; 428 reg-names = "phy_ctrl", 429 "pmu0", 430 "pmu1"; 431 clocks = <&ccu CLK_USB_PHY0>, 432 <&ccu CLK_USB_PHY1>; 433 clock-names = "usb0_phy", 434 "usb1_phy"; 435 resets = <&ccu RST_USB_PHY0>, 436 <&ccu RST_USB_PHY1>; 437 reset-names = "usb0_reset", 438 "usb1_reset"; 439 status = "disabled"; 440 #phy-cells = <1>; 441 }; 442 443 ehci0: usb@1c1a000 { 444 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 445 reg = <0x01c1a000 0x100>; 446 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&ccu CLK_BUS_OHCI0>, 448 <&ccu CLK_BUS_EHCI0>, 449 <&ccu CLK_USB_OHCI0>; 450 resets = <&ccu RST_BUS_OHCI0>, 451 <&ccu RST_BUS_EHCI0>; 452 status = "disabled"; 453 }; 454 455 ohci0: usb@1c1a400 { 456 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 457 reg = <0x01c1a400 0x100>; 458 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&ccu CLK_BUS_OHCI0>, 460 <&ccu CLK_USB_OHCI0>; 461 resets = <&ccu RST_BUS_OHCI0>; 462 status = "disabled"; 463 }; 464 465 ehci1: usb@1c1b000 { 466 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 467 reg = <0x01c1b000 0x100>; 468 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&ccu CLK_BUS_OHCI1>, 470 <&ccu CLK_BUS_EHCI1>, 471 <&ccu CLK_USB_OHCI1>; 472 resets = <&ccu RST_BUS_OHCI1>, 473 <&ccu RST_BUS_EHCI1>; 474 phys = <&usbphy 1>; 475 phy-names = "usb"; 476 status = "disabled"; 477 }; 478 479 ohci1: usb@1c1b400 { 480 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 481 reg = <0x01c1b400 0x100>; 482 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&ccu CLK_BUS_OHCI1>, 484 <&ccu CLK_USB_OHCI1>; 485 resets = <&ccu RST_BUS_OHCI1>; 486 phys = <&usbphy 1>; 487 phy-names = "usb"; 488 status = "disabled"; 489 }; 490 491 ccu: clock@1c20000 { 492 compatible = "allwinner,sun50i-a64-ccu"; 493 reg = <0x01c20000 0x400>; 494 clocks = <&osc24M>, <&osc32k>; 495 clock-names = "hosc", "losc"; 496 #clock-cells = <1>; 497 #reset-cells = <1>; 498 }; 499 500 pio: pinctrl@1c20800 { 501 compatible = "allwinner,sun50i-a64-pinctrl"; 502 reg = <0x01c20800 0x400>; 503 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&ccu 58>; 507 gpio-controller; 508 #gpio-cells = <3>; 509 interrupt-controller; 510 #interrupt-cells = <3>; 511 512 i2c0_pins: i2c0_pins { 513 pins = "PH0", "PH1"; 514 function = "i2c0"; 515 }; 516 517 i2c1_pins: i2c1_pins { 518 pins = "PH2", "PH3"; 519 function = "i2c1"; 520 }; 521 522 mmc0_pins: mmc0-pins { 523 pins = "PF0", "PF1", "PF2", "PF3", 524 "PF4", "PF5"; 525 function = "mmc0"; 526 drive-strength = <30>; 527 bias-pull-up; 528 }; 529 530 mmc1_pins: mmc1-pins { 531 pins = "PG0", "PG1", "PG2", "PG3", 532 "PG4", "PG5"; 533 function = "mmc1"; 534 drive-strength = <30>; 535 bias-pull-up; 536 }; 537 538 mmc2_pins: mmc2-pins { 539 pins = "PC5", "PC6", "PC8", "PC9", 540 "PC10","PC11", "PC12", "PC13", 541 "PC14", "PC15", "PC16"; 542 function = "mmc2"; 543 drive-strength = <30>; 544 bias-pull-up; 545 }; 546 547 mmc2_ds_pin: mmc2-ds-pin { 548 pins = "PC1"; 549 function = "mmc2"; 550 drive-strength = <30>; 551 bias-pull-up; 552 }; 553 554 pwm_pin: pwm_pin { 555 pins = "PD22"; 556 function = "pwm"; 557 }; 558 559 rmii_pins: rmii_pins { 560 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 561 "PD18", "PD19", "PD20", "PD22", "PD23"; 562 function = "emac"; 563 drive-strength = <40>; 564 }; 565 566 rgmii_pins: rgmii_pins { 567 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 568 "PD13", "PD15", "PD16", "PD17", "PD18", 569 "PD19", "PD20", "PD21", "PD22", "PD23"; 570 function = "emac"; 571 drive-strength = <40>; 572 }; 573 574 spdif_tx_pin: spdif { 575 pins = "PH8"; 576 function = "spdif"; 577 }; 578 579 spi0_pins: spi0 { 580 pins = "PC0", "PC1", "PC2", "PC3"; 581 function = "spi0"; 582 }; 583 584 spi1_pins: spi1 { 585 pins = "PD0", "PD1", "PD2", "PD3"; 586 function = "spi1"; 587 }; 588 589 uart0_pb_pins: uart0-pb-pins { 590 pins = "PB8", "PB9"; 591 function = "uart0"; 592 }; 593 594 uart1_pins: uart1_pins { 595 pins = "PG6", "PG7"; 596 function = "uart1"; 597 }; 598 599 uart1_rts_cts_pins: uart1_rts_cts_pins { 600 pins = "PG8", "PG9"; 601 function = "uart1"; 602 }; 603 604 uart2_pins: uart2-pins { 605 pins = "PB0", "PB1"; 606 function = "uart2"; 607 }; 608 609 uart3_pins: uart3-pins { 610 pins = "PD0", "PD1"; 611 function = "uart3"; 612 }; 613 614 uart4_pins: uart4-pins { 615 pins = "PD2", "PD3"; 616 function = "uart4"; 617 }; 618 619 uart4_rts_cts_pins: uart4-rts-cts-pins { 620 pins = "PD4", "PD5"; 621 function = "uart4"; 622 }; 623 }; 624 625 spdif: spdif@1c21000 { 626 #sound-dai-cells = <0>; 627 compatible = "allwinner,sun50i-a64-spdif", 628 "allwinner,sun8i-h3-spdif"; 629 reg = <0x01c21000 0x400>; 630 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 632 resets = <&ccu RST_BUS_SPDIF>; 633 clock-names = "apb", "spdif"; 634 dmas = <&dma 2>; 635 dma-names = "tx"; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&spdif_tx_pin>; 638 status = "disabled"; 639 }; 640 641 i2s0: i2s@1c22000 { 642 #sound-dai-cells = <0>; 643 compatible = "allwinner,sun50i-a64-i2s", 644 "allwinner,sun8i-h3-i2s"; 645 reg = <0x01c22000 0x400>; 646 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 648 clock-names = "apb", "mod"; 649 resets = <&ccu RST_BUS_I2S0>; 650 dma-names = "rx", "tx"; 651 dmas = <&dma 3>, <&dma 3>; 652 status = "disabled"; 653 }; 654 655 i2s1: i2s@1c22400 { 656 #sound-dai-cells = <0>; 657 compatible = "allwinner,sun50i-a64-i2s", 658 "allwinner,sun8i-h3-i2s"; 659 reg = <0x01c22400 0x400>; 660 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 662 clock-names = "apb", "mod"; 663 resets = <&ccu RST_BUS_I2S1>; 664 dma-names = "rx", "tx"; 665 dmas = <&dma 4>, <&dma 4>; 666 status = "disabled"; 667 }; 668 669 uart0: serial@1c28000 { 670 compatible = "snps,dw-apb-uart"; 671 reg = <0x01c28000 0x400>; 672 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 673 reg-shift = <2>; 674 reg-io-width = <4>; 675 clocks = <&ccu CLK_BUS_UART0>; 676 resets = <&ccu RST_BUS_UART0>; 677 status = "disabled"; 678 }; 679 680 uart1: serial@1c28400 { 681 compatible = "snps,dw-apb-uart"; 682 reg = <0x01c28400 0x400>; 683 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 684 reg-shift = <2>; 685 reg-io-width = <4>; 686 clocks = <&ccu CLK_BUS_UART1>; 687 resets = <&ccu RST_BUS_UART1>; 688 status = "disabled"; 689 }; 690 691 uart2: serial@1c28800 { 692 compatible = "snps,dw-apb-uart"; 693 reg = <0x01c28800 0x400>; 694 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 695 reg-shift = <2>; 696 reg-io-width = <4>; 697 clocks = <&ccu CLK_BUS_UART2>; 698 resets = <&ccu RST_BUS_UART2>; 699 status = "disabled"; 700 }; 701 702 uart3: serial@1c28c00 { 703 compatible = "snps,dw-apb-uart"; 704 reg = <0x01c28c00 0x400>; 705 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 706 reg-shift = <2>; 707 reg-io-width = <4>; 708 clocks = <&ccu CLK_BUS_UART3>; 709 resets = <&ccu RST_BUS_UART3>; 710 status = "disabled"; 711 }; 712 713 uart4: serial@1c29000 { 714 compatible = "snps,dw-apb-uart"; 715 reg = <0x01c29000 0x400>; 716 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 717 reg-shift = <2>; 718 reg-io-width = <4>; 719 clocks = <&ccu CLK_BUS_UART4>; 720 resets = <&ccu RST_BUS_UART4>; 721 status = "disabled"; 722 }; 723 724 i2c0: i2c@1c2ac00 { 725 compatible = "allwinner,sun6i-a31-i2c"; 726 reg = <0x01c2ac00 0x400>; 727 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&ccu CLK_BUS_I2C0>; 729 resets = <&ccu RST_BUS_I2C0>; 730 status = "disabled"; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 }; 734 735 i2c1: i2c@1c2b000 { 736 compatible = "allwinner,sun6i-a31-i2c"; 737 reg = <0x01c2b000 0x400>; 738 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&ccu CLK_BUS_I2C1>; 740 resets = <&ccu RST_BUS_I2C1>; 741 status = "disabled"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 }; 745 746 i2c2: i2c@1c2b400 { 747 compatible = "allwinner,sun6i-a31-i2c"; 748 reg = <0x01c2b400 0x400>; 749 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&ccu CLK_BUS_I2C2>; 751 resets = <&ccu RST_BUS_I2C2>; 752 status = "disabled"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 }; 756 757 758 spi0: spi@1c68000 { 759 compatible = "allwinner,sun8i-h3-spi"; 760 reg = <0x01c68000 0x1000>; 761 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 763 clock-names = "ahb", "mod"; 764 dmas = <&dma 23>, <&dma 23>; 765 dma-names = "rx", "tx"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&spi0_pins>; 768 resets = <&ccu RST_BUS_SPI0>; 769 status = "disabled"; 770 num-cs = <1>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 }; 774 775 spi1: spi@1c69000 { 776 compatible = "allwinner,sun8i-h3-spi"; 777 reg = <0x01c69000 0x1000>; 778 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 780 clock-names = "ahb", "mod"; 781 dmas = <&dma 24>, <&dma 24>; 782 dma-names = "rx", "tx"; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&spi1_pins>; 785 resets = <&ccu RST_BUS_SPI1>; 786 status = "disabled"; 787 num-cs = <1>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 }; 791 792 emac: ethernet@1c30000 { 793 compatible = "allwinner,sun50i-a64-emac"; 794 syscon = <&syscon>; 795 reg = <0x01c30000 0x10000>; 796 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 797 interrupt-names = "macirq"; 798 resets = <&ccu RST_BUS_EMAC>; 799 reset-names = "stmmaceth"; 800 clocks = <&ccu CLK_BUS_EMAC>; 801 clock-names = "stmmaceth"; 802 status = "disabled"; 803 804 mdio: mdio { 805 compatible = "snps,dwmac-mdio"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 }; 809 }; 810 811 gic: interrupt-controller@1c81000 { 812 compatible = "arm,gic-400"; 813 reg = <0x01c81000 0x1000>, 814 <0x01c82000 0x2000>, 815 <0x01c84000 0x2000>, 816 <0x01c86000 0x2000>; 817 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 818 interrupt-controller; 819 #interrupt-cells = <3>; 820 }; 821 822 pwm: pwm@1c21400 { 823 compatible = "allwinner,sun50i-a64-pwm", 824 "allwinner,sun5i-a13-pwm"; 825 reg = <0x01c21400 0x400>; 826 clocks = <&osc24M>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&pwm_pin>; 829 #pwm-cells = <3>; 830 status = "disabled"; 831 }; 832 833 hdmi: hdmi@1ee0000 { 834 compatible = "allwinner,sun50i-a64-dw-hdmi", 835 "allwinner,sun8i-a83t-dw-hdmi"; 836 reg = <0x01ee0000 0x10000>; 837 reg-io-width = <1>; 838 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 840 <&ccu CLK_HDMI>; 841 clock-names = "iahb", "isfr", "tmds"; 842 resets = <&ccu RST_BUS_HDMI1>; 843 reset-names = "ctrl"; 844 phys = <&hdmi_phy>; 845 phy-names = "hdmi-phy"; 846 status = "disabled"; 847 848 ports { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 852 hdmi_in: port@0 { 853 reg = <0>; 854 855 hdmi_in_tcon1: endpoint { 856 remote-endpoint = <&tcon1_out_hdmi>; 857 }; 858 }; 859 860 hdmi_out: port@1 { 861 reg = <1>; 862 }; 863 }; 864 }; 865 866 hdmi_phy: hdmi-phy@1ef0000 { 867 compatible = "allwinner,sun50i-a64-hdmi-phy"; 868 reg = <0x01ef0000 0x10000>; 869 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 870 <&ccu 7>; 871 clock-names = "bus", "mod", "pll-0"; 872 resets = <&ccu RST_BUS_HDMI0>; 873 reset-names = "phy"; 874 #phy-cells = <0>; 875 }; 876 877 rtc: rtc@1f00000 { 878 compatible = "allwinner,sun6i-a31-rtc"; 879 reg = <0x01f00000 0x54>; 880 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 882 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 883 clocks = <&osc32k>; 884 #clock-cells = <1>; 885 }; 886 887 r_intc: interrupt-controller@1f00c00 { 888 compatible = "allwinner,sun50i-a64-r-intc", 889 "allwinner,sun6i-a31-r-intc"; 890 interrupt-controller; 891 #interrupt-cells = <2>; 892 reg = <0x01f00c00 0x400>; 893 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 894 }; 895 896 r_ccu: clock@1f01400 { 897 compatible = "allwinner,sun50i-a64-r-ccu"; 898 reg = <0x01f01400 0x100>; 899 clocks = <&osc24M>, <&osc32k>, <&iosc>, 900 <&ccu 11>; 901 clock-names = "hosc", "losc", "iosc", "pll-periph"; 902 #clock-cells = <1>; 903 #reset-cells = <1>; 904 }; 905 906 r_i2c: i2c@1f02400 { 907 compatible = "allwinner,sun50i-a64-i2c", 908 "allwinner,sun6i-a31-i2c"; 909 reg = <0x01f02400 0x400>; 910 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&r_ccu CLK_APB0_I2C>; 912 resets = <&r_ccu RST_APB0_I2C>; 913 status = "disabled"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 }; 917 918 r_pwm: pwm@1f03800 { 919 compatible = "allwinner,sun50i-a64-pwm", 920 "allwinner,sun5i-a13-pwm"; 921 reg = <0x01f03800 0x400>; 922 clocks = <&osc24M>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&r_pwm_pin>; 925 #pwm-cells = <3>; 926 status = "disabled"; 927 }; 928 929 r_pio: pinctrl@1f02c00 { 930 compatible = "allwinner,sun50i-a64-r-pinctrl"; 931 reg = <0x01f02c00 0x400>; 932 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 934 clock-names = "apb", "hosc", "losc"; 935 gpio-controller; 936 #gpio-cells = <3>; 937 interrupt-controller; 938 #interrupt-cells = <3>; 939 940 r_i2c_pl89_pins: r-i2c-pl89-pins { 941 pins = "PL8", "PL9"; 942 function = "s_i2c"; 943 }; 944 945 r_pwm_pin: pwm { 946 pins = "PL10"; 947 function = "s_pwm"; 948 }; 949 950 r_rsb_pins: rsb { 951 pins = "PL0", "PL1"; 952 function = "s_rsb"; 953 }; 954 }; 955 956 r_rsb: rsb@1f03400 { 957 compatible = "allwinner,sun8i-a23-rsb"; 958 reg = <0x01f03400 0x400>; 959 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&r_ccu 6>; 961 clock-frequency = <3000000>; 962 resets = <&r_ccu 2>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&r_rsb_pins>; 965 status = "disabled"; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 }; 969 970 wdt0: watchdog@1c20ca0 { 971 compatible = "allwinner,sun50i-a64-wdt", 972 "allwinner,sun6i-a31-wdt"; 973 reg = <0x01c20ca0 0x20>; 974 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 975 }; 976 }; 977}; 978