1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 24 cpu1: cpu@1 { 25 compatible = "arm,cortex-a7"; 26 device_type = "cpu"; 27 reg = <1>; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci"; 33 method = "smc"; 34 cpu_off = <0x84000002>; 35 cpu_on = <0x84000003>; 36 }; 37 38 aliases { 39 gpio0 = &gpioa; 40 gpio1 = &gpiob; 41 gpio2 = &gpioc; 42 gpio3 = &gpiod; 43 gpio4 = &gpioe; 44 gpio5 = &gpiof; 45 gpio6 = &gpiog; 46 gpio7 = &gpioh; 47 gpio8 = &gpioi; 48 gpio9 = &gpioj; 49 gpio10 = &gpiok; 50 serial0 = &usart1; 51 serial1 = &usart2; 52 serial2 = &usart3; 53 serial3 = &uart4; 54 serial4 = &uart5; 55 serial5 = &usart6; 56 serial6 = &uart7; 57 serial7 = &uart8; 58 }; 59 60 intc: interrupt-controller@a0021000 { 61 compatible = "arm,cortex-a7-gic"; 62 #interrupt-cells = <3>; 63 interrupt-controller; 64 reg = <0xa0021000 0x1000>, 65 <0xa0022000 0x2000>; 66 }; 67 68 timer { 69 compatible = "arm,armv7-timer"; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 74 interrupt-parent = <&intc>; 75 }; 76 77 clocks { 78 clk_hse: clk-hse { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <24000000>; 82 }; 83 84 clk_hsi: clk-hsi { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 90 clk_lse: clk-lse { 91 #clock-cells = <0>; 92 compatible = "fixed-clock"; 93 clock-frequency = <32768>; 94 }; 95 96 clk_lsi: clk-lsi { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <32000>; 100 }; 101 102 clk_csi: clk-csi { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 clock-frequency = <4000000>; 106 }; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 interrupt-parent = <&intc>; 114 ranges; 115 116 timers2: timer@40000000 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "st,stm32-timers"; 120 reg = <0x40000000 0x400>; 121 clocks = <&rcc TIM2_K>; 122 clock-names = "int"; 123 status = "disabled"; 124 125 pwm { 126 compatible = "st,stm32-pwm"; 127 status = "disabled"; 128 }; 129 130 timer@1 { 131 compatible = "st,stm32h7-timer-trigger"; 132 reg = <1>; 133 status = "disabled"; 134 }; 135 }; 136 137 timers3: timer@40001000 { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 compatible = "st,stm32-timers"; 141 reg = <0x40001000 0x400>; 142 clocks = <&rcc TIM3_K>; 143 clock-names = "int"; 144 status = "disabled"; 145 146 pwm { 147 compatible = "st,stm32-pwm"; 148 status = "disabled"; 149 }; 150 151 timer@2 { 152 compatible = "st,stm32h7-timer-trigger"; 153 reg = <2>; 154 status = "disabled"; 155 }; 156 }; 157 158 timers4: timer@40002000 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "st,stm32-timers"; 162 reg = <0x40002000 0x400>; 163 clocks = <&rcc TIM4_K>; 164 clock-names = "int"; 165 status = "disabled"; 166 167 pwm { 168 compatible = "st,stm32-pwm"; 169 status = "disabled"; 170 }; 171 172 timer@3 { 173 compatible = "st,stm32h7-timer-trigger"; 174 reg = <3>; 175 status = "disabled"; 176 }; 177 }; 178 179 timers5: timer@40003000 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "st,stm32-timers"; 183 reg = <0x40003000 0x400>; 184 clocks = <&rcc TIM5_K>; 185 clock-names = "int"; 186 status = "disabled"; 187 188 pwm { 189 compatible = "st,stm32-pwm"; 190 status = "disabled"; 191 }; 192 193 timer@4 { 194 compatible = "st,stm32h7-timer-trigger"; 195 reg = <4>; 196 status = "disabled"; 197 }; 198 }; 199 200 timers6: timer@40004000 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "st,stm32-timers"; 204 reg = <0x40004000 0x400>; 205 clocks = <&rcc TIM6_K>; 206 clock-names = "int"; 207 status = "disabled"; 208 209 timer@5 { 210 compatible = "st,stm32h7-timer-trigger"; 211 reg = <5>; 212 status = "disabled"; 213 }; 214 }; 215 216 timers7: timer@40005000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "st,stm32-timers"; 220 reg = <0x40005000 0x400>; 221 clocks = <&rcc TIM7_K>; 222 clock-names = "int"; 223 status = "disabled"; 224 225 timer@6 { 226 compatible = "st,stm32h7-timer-trigger"; 227 reg = <6>; 228 status = "disabled"; 229 }; 230 }; 231 232 timers12: timer@40006000 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "st,stm32-timers"; 236 reg = <0x40006000 0x400>; 237 clocks = <&rcc TIM12_K>; 238 clock-names = "int"; 239 status = "disabled"; 240 241 pwm { 242 compatible = "st,stm32-pwm"; 243 status = "disabled"; 244 }; 245 246 timer@11 { 247 compatible = "st,stm32h7-timer-trigger"; 248 reg = <11>; 249 status = "disabled"; 250 }; 251 }; 252 253 timers13: timer@40007000 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 compatible = "st,stm32-timers"; 257 reg = <0x40007000 0x400>; 258 clocks = <&rcc TIM13_K>; 259 clock-names = "int"; 260 status = "disabled"; 261 262 pwm { 263 compatible = "st,stm32-pwm"; 264 status = "disabled"; 265 }; 266 267 timer@12 { 268 compatible = "st,stm32h7-timer-trigger"; 269 reg = <12>; 270 status = "disabled"; 271 }; 272 }; 273 274 timers14: timer@40008000 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 compatible = "st,stm32-timers"; 278 reg = <0x40008000 0x400>; 279 clocks = <&rcc TIM14_K>; 280 clock-names = "int"; 281 status = "disabled"; 282 283 pwm { 284 compatible = "st,stm32-pwm"; 285 status = "disabled"; 286 }; 287 288 timer@13 { 289 compatible = "st,stm32h7-timer-trigger"; 290 reg = <13>; 291 status = "disabled"; 292 }; 293 }; 294 295 lptimer1: timer@40009000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "st,stm32-lptimer"; 299 reg = <0x40009000 0x400>; 300 clocks = <&rcc LPTIM1_K>; 301 clock-names = "mux"; 302 status = "disabled"; 303 304 pwm { 305 compatible = "st,stm32-pwm-lp"; 306 #pwm-cells = <3>; 307 status = "disabled"; 308 }; 309 310 trigger@0 { 311 compatible = "st,stm32-lptimer-trigger"; 312 reg = <0>; 313 status = "disabled"; 314 }; 315 316 counter { 317 compatible = "st,stm32-lptimer-counter"; 318 status = "disabled"; 319 }; 320 }; 321 322 usart2: serial@4000e000 { 323 compatible = "st,stm32h7-uart"; 324 reg = <0x4000e000 0x400>; 325 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&rcc USART2_K>; 327 status = "disabled"; 328 }; 329 330 usart3: serial@4000f000 { 331 compatible = "st,stm32h7-uart"; 332 reg = <0x4000f000 0x400>; 333 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&rcc USART3_K>; 335 status = "disabled"; 336 }; 337 338 uart4: serial@40010000 { 339 compatible = "st,stm32h7-uart"; 340 reg = <0x40010000 0x400>; 341 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&rcc UART4_K>; 343 status = "disabled"; 344 }; 345 346 uart5: serial@40011000 { 347 compatible = "st,stm32h7-uart"; 348 reg = <0x40011000 0x400>; 349 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&rcc UART5_K>; 351 status = "disabled"; 352 }; 353 354 i2c1: i2c@40012000 { 355 compatible = "st,stm32f7-i2c"; 356 reg = <0x40012000 0x400>; 357 interrupt-names = "event", "error"; 358 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&rcc I2C1_K>; 361 resets = <&rcc I2C1_R>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 i2c2: i2c@40013000 { 368 compatible = "st,stm32f7-i2c"; 369 reg = <0x40013000 0x400>; 370 interrupt-names = "event", "error"; 371 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&rcc I2C2_K>; 374 resets = <&rcc I2C2_R>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 i2c3: i2c@40014000 { 381 compatible = "st,stm32f7-i2c"; 382 reg = <0x40014000 0x400>; 383 interrupt-names = "event", "error"; 384 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&rcc I2C3_K>; 387 resets = <&rcc I2C3_R>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 i2c5: i2c@40015000 { 394 compatible = "st,stm32f7-i2c"; 395 reg = <0x40015000 0x400>; 396 interrupt-names = "event", "error"; 397 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&rcc I2C5_K>; 400 resets = <&rcc I2C5_R>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 cec: cec@40016000 { 407 compatible = "st,stm32-cec"; 408 reg = <0x40016000 0x400>; 409 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&rcc CEC_K>, <&clk_lse>; 411 clock-names = "cec", "hdmi-cec"; 412 status = "disabled"; 413 }; 414 415 dac: dac@40017000 { 416 compatible = "st,stm32h7-dac-core"; 417 reg = <0x40017000 0x400>; 418 clocks = <&rcc DAC12>; 419 clock-names = "pclk"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 status = "disabled"; 423 424 dac1: dac@1 { 425 compatible = "st,stm32-dac"; 426 #io-channels-cells = <1>; 427 reg = <1>; 428 status = "disabled"; 429 }; 430 431 dac2: dac@2 { 432 compatible = "st,stm32-dac"; 433 #io-channels-cells = <1>; 434 reg = <2>; 435 status = "disabled"; 436 }; 437 }; 438 439 uart7: serial@40018000 { 440 compatible = "st,stm32h7-uart"; 441 reg = <0x40018000 0x400>; 442 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&rcc UART7_K>; 444 status = "disabled"; 445 }; 446 447 uart8: serial@40019000 { 448 compatible = "st,stm32h7-uart"; 449 reg = <0x40019000 0x400>; 450 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&rcc UART8_K>; 452 status = "disabled"; 453 }; 454 455 timers1: timer@44000000 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 compatible = "st,stm32-timers"; 459 reg = <0x44000000 0x400>; 460 clocks = <&rcc TIM1_K>; 461 clock-names = "int"; 462 status = "disabled"; 463 464 pwm { 465 compatible = "st,stm32-pwm"; 466 status = "disabled"; 467 }; 468 469 timer@0 { 470 compatible = "st,stm32h7-timer-trigger"; 471 reg = <0>; 472 status = "disabled"; 473 }; 474 }; 475 476 timers8: timer@44001000 { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 compatible = "st,stm32-timers"; 480 reg = <0x44001000 0x400>; 481 clocks = <&rcc TIM8_K>; 482 clock-names = "int"; 483 status = "disabled"; 484 485 pwm { 486 compatible = "st,stm32-pwm"; 487 status = "disabled"; 488 }; 489 490 timer@7 { 491 compatible = "st,stm32h7-timer-trigger"; 492 reg = <7>; 493 status = "disabled"; 494 }; 495 }; 496 497 usart6: serial@44003000 { 498 compatible = "st,stm32h7-uart"; 499 reg = <0x44003000 0x400>; 500 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&rcc USART6_K>; 502 status = "disabled"; 503 }; 504 505 timers15: timer@44006000 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "st,stm32-timers"; 509 reg = <0x44006000 0x400>; 510 clocks = <&rcc TIM15_K>; 511 clock-names = "int"; 512 status = "disabled"; 513 514 pwm { 515 compatible = "st,stm32-pwm"; 516 status = "disabled"; 517 }; 518 519 timer@14 { 520 compatible = "st,stm32h7-timer-trigger"; 521 reg = <14>; 522 status = "disabled"; 523 }; 524 }; 525 526 timers16: timer@44007000 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 compatible = "st,stm32-timers"; 530 reg = <0x44007000 0x400>; 531 clocks = <&rcc TIM16_K>; 532 clock-names = "int"; 533 status = "disabled"; 534 535 pwm { 536 compatible = "st,stm32-pwm"; 537 status = "disabled"; 538 }; 539 timer@15 { 540 compatible = "st,stm32h7-timer-trigger"; 541 reg = <15>; 542 status = "disabled"; 543 }; 544 }; 545 546 timers17: timer@44008000 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "st,stm32-timers"; 550 reg = <0x44008000 0x400>; 551 clocks = <&rcc TIM17_K>; 552 clock-names = "int"; 553 status = "disabled"; 554 555 pwm { 556 compatible = "st,stm32-pwm"; 557 status = "disabled"; 558 }; 559 560 timer@16 { 561 compatible = "st,stm32h7-timer-trigger"; 562 reg = <16>; 563 status = "disabled"; 564 }; 565 }; 566 567 dma1: dma@48000000 { 568 compatible = "st,stm32-dma"; 569 reg = <0x48000000 0x400>; 570 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&rcc DMA1>; 579 #dma-cells = <4>; 580 st,mem2mem; 581 dma-requests = <8>; 582 }; 583 584 dma2: dma@48001000 { 585 compatible = "st,stm32-dma"; 586 reg = <0x48001000 0x400>; 587 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&rcc DMA2>; 596 #dma-cells = <4>; 597 st,mem2mem; 598 dma-requests = <8>; 599 }; 600 601 dmamux1: dma-router@48002000 { 602 compatible = "st,stm32h7-dmamux"; 603 reg = <0x48002000 0x1c>; 604 #dma-cells = <3>; 605 dma-requests = <128>; 606 dma-masters = <&dma1 &dma2>; 607 dma-channels = <16>; 608 clocks = <&rcc DMAMUX>; 609 }; 610 611 adc: adc@48003000 { 612 compatible = "st,stm32mp1-adc-core"; 613 reg = <0x48003000 0x400>; 614 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 617 clock-names = "bus", "adc"; 618 interrupt-controller; 619 #interrupt-cells = <1>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 624 adc1: adc@0 { 625 compatible = "st,stm32mp1-adc"; 626 #io-channel-cells = <1>; 627 reg = <0x0>; 628 interrupt-parent = <&adc>; 629 interrupts = <0>; 630 status = "disabled"; 631 }; 632 633 adc2: adc@100 { 634 compatible = "st,stm32mp1-adc"; 635 #io-channel-cells = <1>; 636 reg = <0x100>; 637 interrupt-parent = <&adc>; 638 interrupts = <1>; 639 status = "disabled"; 640 }; 641 }; 642 643 sdmmc3: sdmmc@48004000 { 644 compatible = "st,stm32-sdmmc2"; 645 reg = <0x48004000 0x400>, <0x48005000 0x400>; 646 reg-names = "sdmmc", "delay"; 647 interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; 648 clocks = <&rcc SDMMC3_K>; 649 resets = <&rcc SDMMC3_R>; 650 st,idma = <1>; 651 cap-sd-highspeed; 652 cap-mmc-highspeed; 653 max-frequency = <120000000>; 654 status = "disabled"; 655 }; 656 657 rcc: rcc@50000000 { 658 compatible = "st,stm32mp1-rcc", "syscon"; 659 reg = <0x50000000 0x1000>; 660 #clock-cells = <1>; 661 #reset-cells = <1>; 662 }; 663 664 rcc_reboot: rcc-reboot@50000000 { 665 compatible = "syscon-reboot"; 666 regmap = <&rcc>; 667 offset = <0x404>; 668 mask = <0x1>; 669 }; 670 671 pwr: pwr@50001000 { 672 compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; 673 reg = <0x50001000 0x400>; 674 system-power-controller; 675 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 676 st,sysrcc = <&rcc>; 677 clocks = <&rcc PLL2_R>; 678 clock-names = "phyclk"; 679 680 pwr-regulators@c { 681 compatible = "st,stm32mp1,pwr-reg"; 682 st,tzcr = <&rcc 0x0 0x1>; 683 684 reg11: reg11 { 685 regulator-name = "reg11"; 686 regulator-min-microvolt = <1100000>; 687 regulator-max-microvolt = <1100000>; 688 }; 689 690 reg18: reg18 { 691 regulator-name = "reg18"; 692 regulator-min-microvolt = <1800000>; 693 regulator-max-microvolt = <1800000>; 694 }; 695 696 usb33: usb33 { 697 regulator-name = "usb33"; 698 regulator-min-microvolt = <3300000>; 699 regulator-max-microvolt = <3300000>; 700 }; 701 }; 702 }; 703 704 exti: interrupt-controller@5000d000 { 705 compatible = "st,stm32mp1-exti", "syscon"; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 reg = <0x5000d000 0x400>; 709 }; 710 711 syscfg: system-config@50020000 { 712 compatible = "st,stm32-syscfg", "syscon"; 713 reg = <0x50020000 0x400>; 714 }; 715 716 lptimer2: timer@50021000 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 compatible = "st,stm32-lptimer"; 720 reg = <0x50021000 0x400>; 721 clocks = <&rcc LPTIM2_K>; 722 clock-names = "mux"; 723 status = "disabled"; 724 725 pwm { 726 compatible = "st,stm32-pwm-lp"; 727 #pwm-cells = <3>; 728 status = "disabled"; 729 }; 730 731 trigger@1 { 732 compatible = "st,stm32-lptimer-trigger"; 733 reg = <1>; 734 status = "disabled"; 735 }; 736 737 counter { 738 compatible = "st,stm32-lptimer-counter"; 739 status = "disabled"; 740 }; 741 }; 742 743 lptimer3: timer@50022000 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 compatible = "st,stm32-lptimer"; 747 reg = <0x50022000 0x400>; 748 clocks = <&rcc LPTIM3_K>; 749 clock-names = "mux"; 750 status = "disabled"; 751 752 pwm { 753 compatible = "st,stm32-pwm-lp"; 754 #pwm-cells = <3>; 755 status = "disabled"; 756 }; 757 758 trigger@2 { 759 compatible = "st,stm32-lptimer-trigger"; 760 reg = <2>; 761 status = "disabled"; 762 }; 763 }; 764 765 lptimer4: timer@50023000 { 766 compatible = "st,stm32-lptimer"; 767 reg = <0x50023000 0x400>; 768 clocks = <&rcc LPTIM4_K>; 769 clock-names = "mux"; 770 status = "disabled"; 771 772 pwm { 773 compatible = "st,stm32-pwm-lp"; 774 #pwm-cells = <3>; 775 status = "disabled"; 776 }; 777 }; 778 779 lptimer5: timer@50024000 { 780 compatible = "st,stm32-lptimer"; 781 reg = <0x50024000 0x400>; 782 clocks = <&rcc LPTIM5_K>; 783 clock-names = "mux"; 784 status = "disabled"; 785 786 pwm { 787 compatible = "st,stm32-pwm-lp"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 }; 792 793 vrefbuf: vrefbuf@50025000 { 794 compatible = "st,stm32-vrefbuf"; 795 reg = <0x50025000 0x8>; 796 regulator-min-microvolt = <1500000>; 797 regulator-max-microvolt = <2500000>; 798 clocks = <&rcc VREF>; 799 status = "disabled"; 800 }; 801 802 cryp1: cryp@54001000 { 803 compatible = "st,stm32mp1-cryp"; 804 reg = <0x54001000 0x400>; 805 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&rcc CRYP1>; 807 resets = <&rcc CRYP1_R>; 808 status = "disabled"; 809 }; 810 811 rng1: rng@54003000 { 812 compatible = "st,stm32-rng"; 813 reg = <0x54003000 0x400>; 814 clocks = <&rcc RNG1_K>; 815 resets = <&rcc RNG1_R>; 816 status = "disabled"; 817 }; 818 819 mdma1: dma@58000000 { 820 compatible = "st,stm32h7-mdma"; 821 reg = <0x58000000 0x1000>; 822 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&rcc MDMA>; 824 #dma-cells = <5>; 825 dma-channels = <32>; 826 dma-requests = <48>; 827 }; 828 829 qspi: qspi@58003000 { 830 compatible = "st,stm32f469-qspi"; 831 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 832 reg-names = "qspi", "qspi_mm"; 833 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&rcc QSPI_K>; 835 resets = <&rcc QSPI_R>; 836 status = "disabled"; 837 }; 838 839 sdmmc1: sdmmc@58005000 { 840 compatible = "st,stm32-sdmmc2"; 841 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 842 reg-names = "sdmmc", "delay"; 843 clocks = <&rcc SDMMC1_K>; 844 resets = <&rcc SDMMC1_R>; 845 st,idma = <1>; 846 cap-sd-highspeed; 847 cap-mmc-highspeed; 848 max-frequency = <120000000>; 849 status = "disabled"; 850 }; 851 852 sdmmc2: sdmmc@58007000 { 853 compatible = "st,stm32-sdmmc2"; 854 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 855 reg-names = "sdmmc", "delay"; 856 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 857 clocks = <&rcc SDMMC2_K>; 858 resets = <&rcc SDMMC2_R>; 859 st,idma = <1>; 860 cap-sd-highspeed; 861 cap-mmc-highspeed; 862 max-frequency = <120000000>; 863 status = "disabled"; 864 }; 865 866 crc1: crc@58009000 { 867 compatible = "st,stm32f7-crc"; 868 reg = <0x58009000 0x400>; 869 clocks = <&rcc CRC1>; 870 status = "disabled"; 871 }; 872 873 usbh_ohci: usbh-ohci@5800c000 { 874 compatible = "generic-ohci"; 875 reg = <0x5800c000 0x1000>; 876 clocks = <&rcc USBH>; 877 resets = <&rcc USBH_R>; 878 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 879 status = "disabled"; 880 }; 881 882 usbh_ehci: usbh-ehci@5800d000 { 883 compatible = "generic-ehci"; 884 reg = <0x5800d000 0x1000>; 885 clocks = <&rcc USBH>; 886 resets = <&rcc USBH_R>; 887 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 888 companion = <&usbh_ohci>; 889 status = "disabled"; 890 }; 891 892 dsi: dsi@5a000000 { 893 compatible = "st,stm32-dsi"; 894 reg = <0x5a000000 0x800>; 895 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; 896 clock-names = "pclk", "ref", "px_clk"; 897 resets = <&rcc DSI_R>; 898 reset-names = "apb"; 899 status = "disabled"; 900 }; 901 902 ltdc: display-controller@5a001000 { 903 compatible = "st,stm32-ltdc"; 904 reg = <0x5a001000 0x400>; 905 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&rcc LTDC_PX>; 908 clock-names = "lcd"; 909 resets = <&rcc LTDC_R>; 910 status = "disabled"; 911 }; 912 913 usbphyc: usbphyc@5a006000 { 914 #address-cells = <1>; 915 #size-cells = <0>; 916 compatible = "st,stm32mp1-usbphyc"; 917 reg = <0x5a006000 0x1000>; 918 clocks = <&rcc USBPHY_K>; 919 resets = <&rcc USBPHY_R>; 920 status = "disabled"; 921 922 usbphyc_port0: usb-phy@0 { 923 #phy-cells = <0>; 924 reg = <0>; 925 }; 926 927 usbphyc_port1: usb-phy@1 { 928 #phy-cells = <1>; 929 reg = <1>; 930 }; 931 }; 932 933 usart1: serial@5c000000 { 934 compatible = "st,stm32h7-uart"; 935 reg = <0x5c000000 0x400>; 936 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&rcc USART1_K>; 938 status = "disabled"; 939 }; 940 941 i2c4: i2c@5c002000 { 942 compatible = "st,stm32f7-i2c"; 943 reg = <0x5c002000 0x400>; 944 interrupt-names = "event", "error"; 945 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&rcc I2C4_K>; 948 resets = <&rcc I2C4_R>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 status = "disabled"; 952 }; 953 954 i2c6: i2c@5c009000 { 955 compatible = "st,stm32f7-i2c"; 956 reg = <0x5c009000 0x400>; 957 interrupt-names = "event", "error"; 958 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&rcc I2C6_K>; 961 resets = <&rcc I2C6_R>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 }; 967}; 968