1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp157-u-boot.dtsi"
8#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		mmc0 = &sdmmc1;
13		mmc1 = &sdmmc2;
14		i2c3 = &i2c4;
15	};
16
17	led {
18		compatible = "gpio-leds";
19
20		red {
21			label = "stm32mp:red:status";
22			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
23			default-state = "off";
24		};
25		green {
26			label = "stm32mp:green:user";
27			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
28			default-state = "on";
29		};
30		orange {
31			label = "stm32mp:orange:status";
32			gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
33			default-state = "off";
34		};
35		blue {
36			label = "stm32mp:blue:user";
37			gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
38		};
39	};
40};
41
42&clk_hse {
43	st,digbypass;
44};
45
46&uart4_pins_a {
47	u-boot,dm-pre-reloc;
48	pins1 {
49		u-boot,dm-pre-reloc;
50	};
51	pins2 {
52		u-boot,dm-pre-reloc;
53	};
54};
55
56&i2c4_pins_a {
57	u-boot,dm-pre-reloc;
58	pins {
59		u-boot,dm-pre-reloc;
60	};
61};
62
63&uart4 {
64	u-boot,dm-pre-reloc;
65};
66
67&i2c4 {
68	u-boot,dm-pre-reloc;
69};
70
71&pmic {
72	u-boot,dm-pre-reloc;
73};
74
75&rcc {
76	st,clksrc = <
77		CLK_MPU_PLL1P
78		CLK_AXI_PLL2P
79		CLK_MCU_PLL3P
80		CLK_PLL12_HSE
81		CLK_PLL3_HSE
82		CLK_PLL4_HSE
83		CLK_RTC_LSE
84		CLK_MCO1_DISABLED
85		CLK_MCO2_DISABLED
86	>;
87
88	st,clkdiv = <
89		1 /*MPU*/
90		0 /*AXI*/
91		0 /*MCU*/
92		1 /*APB1*/
93		1 /*APB2*/
94		1 /*APB3*/
95		1 /*APB4*/
96		2 /*APB5*/
97		23 /*RTC*/
98		0 /*MCO1*/
99		0 /*MCO2*/
100	>;
101
102	st,pkcs = <
103		CLK_CKPER_HSE
104		CLK_FMC_ACLK
105		CLK_QSPI_ACLK
106		CLK_ETH_DISABLED
107		CLK_SDMMC12_PLL4P
108		CLK_DSI_DSIPLL
109		CLK_STGEN_HSE
110		CLK_USBPHY_HSE
111		CLK_SPI2S1_PLL3Q
112		CLK_SPI2S23_PLL3Q
113		CLK_SPI45_HSI
114		CLK_SPI6_HSI
115		CLK_I2C46_HSI
116		CLK_SDMMC3_PLL4P
117		CLK_USBO_USBPHY
118		CLK_ADC_CKPER
119		CLK_CEC_LSE
120		CLK_I2C12_HSI
121		CLK_I2C35_HSI
122		CLK_UART1_HSI
123		CLK_UART24_HSI
124		CLK_UART35_HSI
125		CLK_UART6_HSI
126		CLK_UART78_HSI
127		CLK_SPDIF_PLL4P
128		CLK_FDCAN_PLL4Q
129		CLK_SAI1_PLL3Q
130		CLK_SAI2_PLL3Q
131		CLK_SAI3_PLL3Q
132		CLK_SAI4_PLL3Q
133		CLK_RNG1_LSI
134		CLK_RNG2_LSI
135		CLK_LPTIM1_PCLK1
136		CLK_LPTIM23_PCLK3
137		CLK_LPTIM45_LSE
138	>;
139
140	/* VCO = 1300.0 MHz => P = 650 (CPU) */
141	pll1: st,pll@0 {
142		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
143		frac = < 0x800 >;
144		u-boot,dm-pre-reloc;
145	};
146
147	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
148	pll2: st,pll@1 {
149		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
150		frac = < 0x1400 >;
151		u-boot,dm-pre-reloc;
152	};
153
154	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
155	pll3: st,pll@2 {
156		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
157		frac = < 0x1a04 >;
158		u-boot,dm-pre-reloc;
159	};
160
161	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
162	pll4: st,pll@3 {
163		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
164		u-boot,dm-pre-reloc;
165	};
166};
167
168/* SPL part **************************************/
169/* MMC1 boot */
170&sdmmc1_b4_pins_a {
171	u-boot,dm-spl;
172	pins {
173		u-boot,dm-spl;
174	};
175};
176
177&sdmmc1_dir_pins_a {
178	u-boot,dm-spl;
179	pins {
180		u-boot,dm-spl;
181	};
182};
183
184&sdmmc1 {
185	u-boot,dm-spl;
186};
187
188/* MMC2 boot */
189&sdmmc2_b4_pins_a {
190	u-boot,dm-spl;
191	pins {
192		u-boot,dm-spl;
193	};
194};
195
196&sdmmc2_d47_pins_a {
197	u-boot,dm-spl;
198	pins {
199		u-boot,dm-spl;
200	};
201};
202
203&sdmmc2 {
204	u-boot,dm-spl;
205};
206