1/*
2 * Copyright : STMicroelectronics 2018
3 *
4 * SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
5 */
6
7#include <dt-bindings/clock/stm32mp1-clksrc.h>
8#include "stm32mp157-u-boot.dtsi"
9#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
10
11/ {
12	aliases {
13		mmc0 = &sdmmc1;
14		i2c3 = &i2c4;
15	};
16};
17
18&uart4_pins_a {
19	u-boot,dm-pre-reloc;
20	pins1 {
21		u-boot,dm-pre-reloc;
22	};
23	pins2 {
24		u-boot,dm-pre-reloc;
25	};
26};
27
28&i2c4_pins_a {
29	u-boot,dm-pre-reloc;
30	pins {
31		u-boot,dm-pre-reloc;
32	};
33};
34
35&uart4 {
36	u-boot,dm-pre-reloc;
37};
38
39&i2c4 {
40	u-boot,dm-pre-reloc;
41};
42
43&pmic {
44	u-boot,dm-pre-reloc;
45};
46
47/* CLOCK init */
48&rcc_clk {
49	st,clksrc = <
50		CLK_MPU_PLL1P
51		CLK_AXI_PLL2P
52		CLK_MCU_PLL3P
53		CLK_PLL12_HSE
54		CLK_PLL3_HSE
55		CLK_PLL4_HSE
56		CLK_RTC_LSE
57		CLK_MCO1_DISABLED
58		CLK_MCO2_DISABLED
59	>;
60
61	st,clkdiv = <
62		1 /*MPU*/
63		0 /*AXI*/
64		0 /*MCU*/
65		1 /*APB1*/
66		1 /*APB2*/
67		1 /*APB3*/
68		1 /*APB4*/
69		2 /*APB5*/
70		23 /*RTC*/
71		0 /*MCO1*/
72		0 /*MCO2*/
73	>;
74
75	st,pkcs = <
76		CLK_CKPER_DISABLED
77		CLK_SDMMC12_PLL3R
78		CLK_I2C46_PCLK5
79		CLK_I2C12_PCLK1
80		CLK_I2C35_PCLK1
81		CLK_UART1_PCLK5
82		CLK_UART24_PCLK1
83		CLK_UART35_PCLK1
84		CLK_UART6_PCLK2
85		CLK_UART78_PCLK1
86	>;
87
88	/* VCO = 1300.0 MHz => P = 650 (CPU) */
89	pll1: st,pll@0 {
90		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
91		frac = < 0x800 >;
92		u-boot,dm-pre-reloc;
93	};
94
95	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
96	pll2: st,pll@1 {
97		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
98		frac = < 0x1400 >;
99		u-boot,dm-pre-reloc;
100	};
101
102	/* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
103	pll3: st,pll@2 {
104		cfg = < 3 128 3 20 7 PQR(1,1,1) >;
105		u-boot,dm-pre-reloc;
106	};
107
108	/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
109	pll4: st,pll@3 {
110		cfg = < 5 126 8 8 8 PQR(1,1,1) >;
111		u-boot,dm-pre-reloc;
112	};
113};
114
115/* SPL part **************************************/
116/* MMC1 boot */
117&sdmmc1_b4_pins_a {
118	u-boot,dm-spl;
119	pins {
120		u-boot,dm-spl;
121	};
122};
123
124&sdmmc1_dir_pins_a {
125	u-boot,dm-spl;
126	pins {
127		u-boot,dm-spl;
128	};
129};
130
131&sdmmc1 {
132	u-boot,dm-spl;
133};
134