1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp157-u-boot.dtsi"
8#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		mmc0 = &sdmmc1;
13		mmc1 = &sdmmc2;
14		i2c3 = &i2c4;
15	};
16};
17
18&uart4_pins_a {
19	u-boot,dm-pre-reloc;
20	pins1 {
21		u-boot,dm-pre-reloc;
22	};
23	pins2 {
24		u-boot,dm-pre-reloc;
25	};
26};
27
28&i2c4_pins_a {
29	u-boot,dm-pre-reloc;
30	pins {
31		u-boot,dm-pre-reloc;
32	};
33};
34
35&uart4 {
36	u-boot,dm-pre-reloc;
37};
38
39&i2c4 {
40	u-boot,dm-pre-reloc;
41};
42
43&pmic {
44	u-boot,dm-pre-reloc;
45};
46
47/* CLOCK init */
48&rcc {
49	st,clksrc = <
50		CLK_MPU_PLL1P
51		CLK_AXI_PLL2P
52		CLK_MCU_PLL3P
53		CLK_PLL12_HSE
54		CLK_PLL3_HSE
55		CLK_PLL4_HSE
56		CLK_RTC_LSE
57		CLK_MCO1_DISABLED
58		CLK_MCO2_DISABLED
59	>;
60
61	st,clkdiv = <
62		1 /*MPU*/
63		0 /*AXI*/
64		0 /*MCU*/
65		1 /*APB1*/
66		1 /*APB2*/
67		1 /*APB3*/
68		1 /*APB4*/
69		2 /*APB5*/
70		23 /*RTC*/
71		0 /*MCO1*/
72		0 /*MCO2*/
73	>;
74
75	st,pkcs = <
76		CLK_CKPER_HSE
77		CLK_FMC_ACLK
78		CLK_QSPI_ACLK
79		CLK_ETH_DISABLED
80		CLK_SDMMC12_PLL3R
81		CLK_DSI_DSIPLL
82		CLK_STGEN_HSE
83		CLK_USBPHY_HSE
84		CLK_SPI2S1_PLL3Q
85		CLK_SPI2S23_PLL3Q
86		CLK_SPI45_HSI
87		CLK_SPI6_HSI
88		CLK_I2C46_HSI
89		CLK_SDMMC3_PLL3R
90		CLK_USBO_USBPHY
91		CLK_ADC_CKPER
92		CLK_CEC_LSE
93		CLK_I2C12_HSI
94		CLK_I2C35_HSI
95		CLK_UART1_HSI
96		CLK_UART24_HSI
97		CLK_UART35_HSI
98		CLK_UART6_HSI
99		CLK_UART78_HSI
100		CLK_SPDIF_PLL3Q
101		CLK_FDCAN_PLL4Q
102		CLK_SAI1_PLL3Q
103		CLK_SAI2_PLL3Q
104		CLK_SAI3_PLL3Q
105		CLK_SAI4_PLL3Q
106		CLK_RNG1_CSI
107		CLK_RNG2_CSI
108		CLK_LPTIM1_PCLK1
109		CLK_LPTIM23_PCLK3
110		CLK_LPTIM45_PCLK3
111	>;
112
113	/* VCO = 1300.0 MHz => P = 650 (CPU) */
114	pll1: st,pll@0 {
115		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
116		frac = < 0x800 >;
117		u-boot,dm-pre-reloc;
118	};
119
120	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
121	pll2: st,pll@1 {
122		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
123		frac = < 0x1400 >;
124		u-boot,dm-pre-reloc;
125	};
126
127	/* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
128	pll3: st,pll@2 {
129		cfg = < 2 97 3 15 7 PQR(1,1,1) >;
130		frac = < 0x9ba >;
131		u-boot,dm-pre-reloc;
132	};
133
134	/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
135	pll4: st,pll@3 {
136		cfg = < 5 126 8 8 8 PQR(1,1,1) >;
137		u-boot,dm-pre-reloc;
138	};
139};
140
141/* SPL part **************************************/
142/* MMC1 boot */
143&sdmmc1_b4_pins_a {
144	u-boot,dm-spl;
145	pins {
146		u-boot,dm-spl;
147	};
148};
149
150&sdmmc1_dir_pins_a {
151	u-boot,dm-spl;
152	pins {
153		u-boot,dm-spl;
154	};
155};
156
157&sdmmc1 {
158	u-boot,dm-spl;
159};
160
161/* MMC2 boot */
162&sdmmc2_b4_pins_a {
163	u-boot,dm-spl;
164	pins {
165		u-boot,dm-spl;
166	};
167};
168
169&sdmmc2_d47_pins_a {
170	u-boot,dm-spl;
171	pins {
172		u-boot,dm-spl;
173	};
174};
175
176&sdmmc2 {
177	u-boot,dm-spl;
178};
179