14549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 23d2d115aSPatrick Delaunay/* 33d2d115aSPatrick Delaunay * Copyright : STMicroelectronics 2018 43d2d115aSPatrick Delaunay */ 53d2d115aSPatrick Delaunay 63d2d115aSPatrick Delaunay#include <dt-bindings/clock/stm32mp1-clksrc.h> 73d2d115aSPatrick Delaunay#include "stm32mp157-u-boot.dtsi" 83d2d115aSPatrick Delaunay#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 93d2d115aSPatrick Delaunay 103d2d115aSPatrick Delaunay/ { 113d2d115aSPatrick Delaunay aliases { 123d2d115aSPatrick Delaunay mmc0 = &sdmmc1; 130ed232b1SPatrick Delaunay mmc1 = &sdmmc2; 143d2d115aSPatrick Delaunay i2c3 = &i2c4; 153d2d115aSPatrick Delaunay }; 163d2d115aSPatrick Delaunay}; 173d2d115aSPatrick Delaunay 183d2d115aSPatrick Delaunay&uart4_pins_a { 193d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 203d2d115aSPatrick Delaunay pins1 { 213d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 223d2d115aSPatrick Delaunay }; 233d2d115aSPatrick Delaunay pins2 { 243d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 253d2d115aSPatrick Delaunay }; 263d2d115aSPatrick Delaunay}; 273d2d115aSPatrick Delaunay 283d2d115aSPatrick Delaunay&i2c4_pins_a { 293d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 303d2d115aSPatrick Delaunay pins { 313d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 323d2d115aSPatrick Delaunay }; 333d2d115aSPatrick Delaunay}; 343d2d115aSPatrick Delaunay 353d2d115aSPatrick Delaunay&uart4 { 363d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 373d2d115aSPatrick Delaunay}; 383d2d115aSPatrick Delaunay 393d2d115aSPatrick Delaunay&i2c4 { 403d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 413d2d115aSPatrick Delaunay}; 423d2d115aSPatrick Delaunay 433d2d115aSPatrick Delaunay&pmic { 443d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 453d2d115aSPatrick Delaunay}; 463d2d115aSPatrick Delaunay 473d2d115aSPatrick Delaunay/* CLOCK init */ 48a674313cSPatrick Delaunay&rcc { 493d2d115aSPatrick Delaunay st,clksrc = < 503d2d115aSPatrick Delaunay CLK_MPU_PLL1P 513d2d115aSPatrick Delaunay CLK_AXI_PLL2P 523d2d115aSPatrick Delaunay CLK_MCU_PLL3P 533d2d115aSPatrick Delaunay CLK_PLL12_HSE 543d2d115aSPatrick Delaunay CLK_PLL3_HSE 553d2d115aSPatrick Delaunay CLK_PLL4_HSE 563d2d115aSPatrick Delaunay CLK_RTC_LSE 573d2d115aSPatrick Delaunay CLK_MCO1_DISABLED 583d2d115aSPatrick Delaunay CLK_MCO2_DISABLED 593d2d115aSPatrick Delaunay >; 603d2d115aSPatrick Delaunay 613d2d115aSPatrick Delaunay st,clkdiv = < 623d2d115aSPatrick Delaunay 1 /*MPU*/ 633d2d115aSPatrick Delaunay 0 /*AXI*/ 643d2d115aSPatrick Delaunay 0 /*MCU*/ 653d2d115aSPatrick Delaunay 1 /*APB1*/ 663d2d115aSPatrick Delaunay 1 /*APB2*/ 673d2d115aSPatrick Delaunay 1 /*APB3*/ 683d2d115aSPatrick Delaunay 1 /*APB4*/ 693d2d115aSPatrick Delaunay 2 /*APB5*/ 703d2d115aSPatrick Delaunay 23 /*RTC*/ 713d2d115aSPatrick Delaunay 0 /*MCO1*/ 723d2d115aSPatrick Delaunay 0 /*MCO2*/ 733d2d115aSPatrick Delaunay >; 743d2d115aSPatrick Delaunay 753d2d115aSPatrick Delaunay st,pkcs = < 76*8a07d5bfSPatrick Delaunay CLK_CKPER_HSE 77*8a07d5bfSPatrick Delaunay CLK_FMC_ACLK 78*8a07d5bfSPatrick Delaunay CLK_QSPI_ACLK 79*8a07d5bfSPatrick Delaunay CLK_ETH_DISABLED 803d2d115aSPatrick Delaunay CLK_SDMMC12_PLL3R 81*8a07d5bfSPatrick Delaunay CLK_DSI_DSIPLL 82b90f0e7cSPatrick Delaunay CLK_STGEN_HSE 83*8a07d5bfSPatrick Delaunay CLK_USBPHY_HSE 84*8a07d5bfSPatrick Delaunay CLK_SPI2S1_PLL3Q 85*8a07d5bfSPatrick Delaunay CLK_SPI2S23_PLL3Q 86*8a07d5bfSPatrick Delaunay CLK_SPI45_HSI 87*8a07d5bfSPatrick Delaunay CLK_SPI6_HSI 88*8a07d5bfSPatrick Delaunay CLK_I2C46_HSI 890ed232b1SPatrick Delaunay CLK_SDMMC3_PLL3R 90*8a07d5bfSPatrick Delaunay CLK_USBO_USBPHY 91*8a07d5bfSPatrick Delaunay CLK_ADC_CKPER 92*8a07d5bfSPatrick Delaunay CLK_CEC_LSE 93*8a07d5bfSPatrick Delaunay CLK_I2C12_HSI 94*8a07d5bfSPatrick Delaunay CLK_I2C35_HSI 95*8a07d5bfSPatrick Delaunay CLK_UART1_HSI 96*8a07d5bfSPatrick Delaunay CLK_UART24_HSI 97*8a07d5bfSPatrick Delaunay CLK_UART35_HSI 98*8a07d5bfSPatrick Delaunay CLK_UART6_HSI 99*8a07d5bfSPatrick Delaunay CLK_UART78_HSI 100*8a07d5bfSPatrick Delaunay CLK_SPDIF_PLL3Q 101*8a07d5bfSPatrick Delaunay CLK_FDCAN_PLL4Q 102*8a07d5bfSPatrick Delaunay CLK_SAI1_PLL3Q 103*8a07d5bfSPatrick Delaunay CLK_SAI2_PLL3Q 104*8a07d5bfSPatrick Delaunay CLK_SAI3_PLL3Q 105*8a07d5bfSPatrick Delaunay CLK_SAI4_PLL3Q 106*8a07d5bfSPatrick Delaunay CLK_RNG1_CSI 107*8a07d5bfSPatrick Delaunay CLK_RNG2_CSI 108*8a07d5bfSPatrick Delaunay CLK_LPTIM1_PCLK1 109*8a07d5bfSPatrick Delaunay CLK_LPTIM23_PCLK3 110*8a07d5bfSPatrick Delaunay CLK_LPTIM45_PCLK3 1113d2d115aSPatrick Delaunay >; 1123d2d115aSPatrick Delaunay 1133d2d115aSPatrick Delaunay /* VCO = 1300.0 MHz => P = 650 (CPU) */ 1143d2d115aSPatrick Delaunay pll1: st,pll@0 { 1153d2d115aSPatrick Delaunay cfg = < 2 80 0 0 0 PQR(1,0,0) >; 1163d2d115aSPatrick Delaunay frac = < 0x800 >; 1173d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1183d2d115aSPatrick Delaunay }; 1193d2d115aSPatrick Delaunay 1203d2d115aSPatrick Delaunay /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 1213d2d115aSPatrick Delaunay pll2: st,pll@1 { 1223d2d115aSPatrick Delaunay cfg = < 2 65 1 0 0 PQR(1,1,1) >; 1233d2d115aSPatrick Delaunay frac = < 0x1400 >; 1243d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1253d2d115aSPatrick Delaunay }; 1263d2d115aSPatrick Delaunay 127*8a07d5bfSPatrick Delaunay /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ 1283d2d115aSPatrick Delaunay pll3: st,pll@2 { 129*8a07d5bfSPatrick Delaunay cfg = < 2 97 3 15 7 PQR(1,1,1) >; 130*8a07d5bfSPatrick Delaunay frac = < 0x9ba >; 1313d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1323d2d115aSPatrick Delaunay }; 1333d2d115aSPatrick Delaunay 1343d2d115aSPatrick Delaunay /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ 1353d2d115aSPatrick Delaunay pll4: st,pll@3 { 1363d2d115aSPatrick Delaunay cfg = < 5 126 8 8 8 PQR(1,1,1) >; 1373d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1383d2d115aSPatrick Delaunay }; 1393d2d115aSPatrick Delaunay}; 1403d2d115aSPatrick Delaunay 1413d2d115aSPatrick Delaunay/* SPL part **************************************/ 1423d2d115aSPatrick Delaunay/* MMC1 boot */ 1433d2d115aSPatrick Delaunay&sdmmc1_b4_pins_a { 1443d2d115aSPatrick Delaunay u-boot,dm-spl; 1453d2d115aSPatrick Delaunay pins { 1463d2d115aSPatrick Delaunay u-boot,dm-spl; 1473d2d115aSPatrick Delaunay }; 1483d2d115aSPatrick Delaunay}; 1493d2d115aSPatrick Delaunay 1503d2d115aSPatrick Delaunay&sdmmc1_dir_pins_a { 1513d2d115aSPatrick Delaunay u-boot,dm-spl; 1523d2d115aSPatrick Delaunay pins { 1533d2d115aSPatrick Delaunay u-boot,dm-spl; 1543d2d115aSPatrick Delaunay }; 1553d2d115aSPatrick Delaunay}; 1563d2d115aSPatrick Delaunay 1573d2d115aSPatrick Delaunay&sdmmc1 { 1583d2d115aSPatrick Delaunay u-boot,dm-spl; 1593d2d115aSPatrick Delaunay}; 1600ed232b1SPatrick Delaunay 1610ed232b1SPatrick Delaunay/* MMC2 boot */ 1620ed232b1SPatrick Delaunay&sdmmc2_b4_pins_a { 1630ed232b1SPatrick Delaunay u-boot,dm-spl; 1640ed232b1SPatrick Delaunay pins { 1650ed232b1SPatrick Delaunay u-boot,dm-spl; 1660ed232b1SPatrick Delaunay }; 1670ed232b1SPatrick Delaunay}; 1680ed232b1SPatrick Delaunay 1690ed232b1SPatrick Delaunay&sdmmc2_d47_pins_a { 1700ed232b1SPatrick Delaunay u-boot,dm-spl; 1710ed232b1SPatrick Delaunay pins { 1720ed232b1SPatrick Delaunay u-boot,dm-spl; 1730ed232b1SPatrick Delaunay }; 1740ed232b1SPatrick Delaunay}; 1750ed232b1SPatrick Delaunay 1760ed232b1SPatrick Delaunay&sdmmc2 { 1770ed232b1SPatrick Delaunay u-boot,dm-spl; 1780ed232b1SPatrick Delaunay}; 179