1*4549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 23d2d115aSPatrick Delaunay/* 33d2d115aSPatrick Delaunay * Copyright : STMicroelectronics 2018 43d2d115aSPatrick Delaunay */ 53d2d115aSPatrick Delaunay 63d2d115aSPatrick Delaunay#include <dt-bindings/clock/stm32mp1-clksrc.h> 73d2d115aSPatrick Delaunay#include "stm32mp157-u-boot.dtsi" 83d2d115aSPatrick Delaunay#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 93d2d115aSPatrick Delaunay 103d2d115aSPatrick Delaunay/ { 113d2d115aSPatrick Delaunay aliases { 123d2d115aSPatrick Delaunay mmc0 = &sdmmc1; 130ed232b1SPatrick Delaunay mmc1 = &sdmmc2; 143d2d115aSPatrick Delaunay i2c3 = &i2c4; 153d2d115aSPatrick Delaunay }; 163d2d115aSPatrick Delaunay}; 173d2d115aSPatrick Delaunay 183d2d115aSPatrick Delaunay&uart4_pins_a { 193d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 203d2d115aSPatrick Delaunay pins1 { 213d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 223d2d115aSPatrick Delaunay }; 233d2d115aSPatrick Delaunay pins2 { 243d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 253d2d115aSPatrick Delaunay }; 263d2d115aSPatrick Delaunay}; 273d2d115aSPatrick Delaunay 283d2d115aSPatrick Delaunay&i2c4_pins_a { 293d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 303d2d115aSPatrick Delaunay pins { 313d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 323d2d115aSPatrick Delaunay }; 333d2d115aSPatrick Delaunay}; 343d2d115aSPatrick Delaunay 353d2d115aSPatrick Delaunay&uart4 { 363d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 373d2d115aSPatrick Delaunay}; 383d2d115aSPatrick Delaunay 393d2d115aSPatrick Delaunay&i2c4 { 403d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 413d2d115aSPatrick Delaunay}; 423d2d115aSPatrick Delaunay 433d2d115aSPatrick Delaunay&pmic { 443d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 453d2d115aSPatrick Delaunay}; 463d2d115aSPatrick Delaunay 473d2d115aSPatrick Delaunay/* CLOCK init */ 483d2d115aSPatrick Delaunay&rcc_clk { 493d2d115aSPatrick Delaunay st,clksrc = < 503d2d115aSPatrick Delaunay CLK_MPU_PLL1P 513d2d115aSPatrick Delaunay CLK_AXI_PLL2P 523d2d115aSPatrick Delaunay CLK_MCU_PLL3P 533d2d115aSPatrick Delaunay CLK_PLL12_HSE 543d2d115aSPatrick Delaunay CLK_PLL3_HSE 553d2d115aSPatrick Delaunay CLK_PLL4_HSE 563d2d115aSPatrick Delaunay CLK_RTC_LSE 573d2d115aSPatrick Delaunay CLK_MCO1_DISABLED 583d2d115aSPatrick Delaunay CLK_MCO2_DISABLED 593d2d115aSPatrick Delaunay >; 603d2d115aSPatrick Delaunay 613d2d115aSPatrick Delaunay st,clkdiv = < 623d2d115aSPatrick Delaunay 1 /*MPU*/ 633d2d115aSPatrick Delaunay 0 /*AXI*/ 643d2d115aSPatrick Delaunay 0 /*MCU*/ 653d2d115aSPatrick Delaunay 1 /*APB1*/ 663d2d115aSPatrick Delaunay 1 /*APB2*/ 673d2d115aSPatrick Delaunay 1 /*APB3*/ 683d2d115aSPatrick Delaunay 1 /*APB4*/ 693d2d115aSPatrick Delaunay 2 /*APB5*/ 703d2d115aSPatrick Delaunay 23 /*RTC*/ 713d2d115aSPatrick Delaunay 0 /*MCO1*/ 723d2d115aSPatrick Delaunay 0 /*MCO2*/ 733d2d115aSPatrick Delaunay >; 743d2d115aSPatrick Delaunay 753d2d115aSPatrick Delaunay st,pkcs = < 763d2d115aSPatrick Delaunay CLK_CKPER_DISABLED 773d2d115aSPatrick Delaunay CLK_SDMMC12_PLL3R 78b90f0e7cSPatrick Delaunay CLK_STGEN_HSE 793d2d115aSPatrick Delaunay CLK_I2C46_PCLK5 803d2d115aSPatrick Delaunay CLK_I2C12_PCLK1 810ed232b1SPatrick Delaunay CLK_SDMMC3_PLL3R 823d2d115aSPatrick Delaunay CLK_I2C35_PCLK1 833d2d115aSPatrick Delaunay CLK_UART1_PCLK5 843d2d115aSPatrick Delaunay CLK_UART24_PCLK1 853d2d115aSPatrick Delaunay CLK_UART35_PCLK1 863d2d115aSPatrick Delaunay CLK_UART6_PCLK2 873d2d115aSPatrick Delaunay CLK_UART78_PCLK1 883d2d115aSPatrick Delaunay >; 893d2d115aSPatrick Delaunay 903d2d115aSPatrick Delaunay /* VCO = 1300.0 MHz => P = 650 (CPU) */ 913d2d115aSPatrick Delaunay pll1: st,pll@0 { 923d2d115aSPatrick Delaunay cfg = < 2 80 0 0 0 PQR(1,0,0) >; 933d2d115aSPatrick Delaunay frac = < 0x800 >; 943d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 953d2d115aSPatrick Delaunay }; 963d2d115aSPatrick Delaunay 973d2d115aSPatrick Delaunay /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 983d2d115aSPatrick Delaunay pll2: st,pll@1 { 993d2d115aSPatrick Delaunay cfg = < 2 65 1 0 0 PQR(1,1,1) >; 1003d2d115aSPatrick Delaunay frac = < 0x1400 >; 1013d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1023d2d115aSPatrick Delaunay }; 1033d2d115aSPatrick Delaunay 1043d2d115aSPatrick Delaunay /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */ 1053d2d115aSPatrick Delaunay pll3: st,pll@2 { 1063d2d115aSPatrick Delaunay cfg = < 3 128 3 20 7 PQR(1,1,1) >; 1073d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1083d2d115aSPatrick Delaunay }; 1093d2d115aSPatrick Delaunay 1103d2d115aSPatrick Delaunay /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ 1113d2d115aSPatrick Delaunay pll4: st,pll@3 { 1123d2d115aSPatrick Delaunay cfg = < 5 126 8 8 8 PQR(1,1,1) >; 1133d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1143d2d115aSPatrick Delaunay }; 1153d2d115aSPatrick Delaunay}; 1163d2d115aSPatrick Delaunay 1173d2d115aSPatrick Delaunay/* SPL part **************************************/ 1183d2d115aSPatrick Delaunay/* MMC1 boot */ 1193d2d115aSPatrick Delaunay&sdmmc1_b4_pins_a { 1203d2d115aSPatrick Delaunay u-boot,dm-spl; 1213d2d115aSPatrick Delaunay pins { 1223d2d115aSPatrick Delaunay u-boot,dm-spl; 1233d2d115aSPatrick Delaunay }; 1243d2d115aSPatrick Delaunay}; 1253d2d115aSPatrick Delaunay 1263d2d115aSPatrick Delaunay&sdmmc1_dir_pins_a { 1273d2d115aSPatrick Delaunay u-boot,dm-spl; 1283d2d115aSPatrick Delaunay pins { 1293d2d115aSPatrick Delaunay u-boot,dm-spl; 1303d2d115aSPatrick Delaunay }; 1313d2d115aSPatrick Delaunay}; 1323d2d115aSPatrick Delaunay 1333d2d115aSPatrick Delaunay&sdmmc1 { 1343d2d115aSPatrick Delaunay u-boot,dm-spl; 1353d2d115aSPatrick Delaunay}; 1360ed232b1SPatrick Delaunay 1370ed232b1SPatrick Delaunay/* MMC2 boot */ 1380ed232b1SPatrick Delaunay&sdmmc2_b4_pins_a { 1390ed232b1SPatrick Delaunay u-boot,dm-spl; 1400ed232b1SPatrick Delaunay pins { 1410ed232b1SPatrick Delaunay u-boot,dm-spl; 1420ed232b1SPatrick Delaunay }; 1430ed232b1SPatrick Delaunay}; 1440ed232b1SPatrick Delaunay 1450ed232b1SPatrick Delaunay&sdmmc2_d47_pins_a { 1460ed232b1SPatrick Delaunay u-boot,dm-spl; 1470ed232b1SPatrick Delaunay pins { 1480ed232b1SPatrick Delaunay u-boot,dm-spl; 1490ed232b1SPatrick Delaunay }; 1500ed232b1SPatrick Delaunay}; 1510ed232b1SPatrick Delaunay 1520ed232b1SPatrick Delaunay&sdmmc2 { 1530ed232b1SPatrick Delaunay u-boot,dm-spl; 1540ed232b1SPatrick Delaunay}; 155