1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8/ {
9	soc {
10		pinctrl: pin-controller@50002000 {
11			#address-cells = <1>;
12			#size-cells = <1>;
13			compatible = "st,stm32mp157-pinctrl";
14			ranges = <0 0x50002000 0xa400>;
15			interrupt-parent = <&exti>;
16			st,syscfg = <&exti 0x60 0xff>;
17			pins-are-numbered;
18
19			gpioa: gpio@50002000 {
20				gpio-controller;
21				#gpio-cells = <2>;
22				interrupt-controller;
23				#interrupt-cells = <2>;
24				reg = <0x0 0x400>;
25				clocks = <&rcc GPIOA>;
26				st,bank-name = "GPIOA";
27				ngpios = <16>;
28				gpio-ranges = <&pinctrl 0 0 16>;
29			};
30
31			gpiob: gpio@50003000 {
32				gpio-controller;
33				#gpio-cells = <2>;
34				interrupt-controller;
35				#interrupt-cells = <2>;
36				reg = <0x1000 0x400>;
37				clocks = <&rcc GPIOB>;
38				st,bank-name = "GPIOB";
39				ngpios = <16>;
40				gpio-ranges = <&pinctrl 0 16 16>;
41			};
42
43			gpioc: gpio@50004000 {
44				gpio-controller;
45				#gpio-cells = <2>;
46				interrupt-controller;
47				#interrupt-cells = <2>;
48				reg = <0x2000 0x400>;
49				clocks = <&rcc GPIOC>;
50				st,bank-name = "GPIOC";
51				ngpios = <16>;
52				gpio-ranges = <&pinctrl 0 32 16>;
53			};
54
55			gpiod: gpio@50005000 {
56				gpio-controller;
57				#gpio-cells = <2>;
58				interrupt-controller;
59				#interrupt-cells = <2>;
60				reg = <0x3000 0x400>;
61				clocks = <&rcc GPIOD>;
62				st,bank-name = "GPIOD";
63				ngpios = <16>;
64				gpio-ranges = <&pinctrl 0 48 16>;
65			};
66
67			gpioe: gpio@50006000 {
68				gpio-controller;
69				#gpio-cells = <2>;
70				interrupt-controller;
71				#interrupt-cells = <2>;
72				reg = <0x4000 0x400>;
73				clocks = <&rcc GPIOE>;
74				st,bank-name = "GPIOE";
75				ngpios = <16>;
76				gpio-ranges = <&pinctrl 0 64 16>;
77			};
78
79			gpiof: gpio@50007000 {
80				gpio-controller;
81				#gpio-cells = <2>;
82				interrupt-controller;
83				#interrupt-cells = <2>;
84				reg = <0x5000 0x400>;
85				clocks = <&rcc GPIOF>;
86				st,bank-name = "GPIOF";
87				ngpios = <16>;
88				gpio-ranges = <&pinctrl 0 80 16>;
89			};
90
91			gpiog: gpio@50008000 {
92				gpio-controller;
93				#gpio-cells = <2>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				reg = <0x6000 0x400>;
97				clocks = <&rcc GPIOG>;
98				st,bank-name = "GPIOG";
99				ngpios = <16>;
100				gpio-ranges = <&pinctrl 0 96 16>;
101			};
102
103			gpioh: gpio@50009000 {
104				gpio-controller;
105				#gpio-cells = <2>;
106				interrupt-controller;
107				#interrupt-cells = <2>;
108				reg = <0x7000 0x400>;
109				clocks = <&rcc GPIOH>;
110				st,bank-name = "GPIOH";
111				ngpios = <16>;
112				gpio-ranges = <&pinctrl 0 112 16>;
113			};
114
115			gpioi: gpio@5000a000 {
116				gpio-controller;
117				#gpio-cells = <2>;
118				interrupt-controller;
119				#interrupt-cells = <2>;
120				reg = <0x8000 0x400>;
121				clocks = <&rcc GPIOI>;
122				st,bank-name = "GPIOI";
123				ngpios = <16>;
124				gpio-ranges = <&pinctrl 0 128 16>;
125			};
126
127			gpioj: gpio@5000b000 {
128				gpio-controller;
129				#gpio-cells = <2>;
130				interrupt-controller;
131				#interrupt-cells = <2>;
132				reg = <0x9000 0x400>;
133				clocks = <&rcc GPIOJ>;
134				st,bank-name = "GPIOJ";
135				ngpios = <16>;
136				gpio-ranges = <&pinctrl 0 144 16>;
137			};
138
139			gpiok: gpio@5000c000 {
140				gpio-controller;
141				#gpio-cells = <2>;
142				interrupt-controller;
143				#interrupt-cells = <2>;
144				reg = <0xa000 0x400>;
145				clocks = <&rcc GPIOK>;
146				st,bank-name = "GPIOK";
147				ngpios = <8>;
148				gpio-ranges = <&pinctrl 0 160 8>;
149			};
150
151			cec_pins_a: cec-0 {
152				pins {
153					pinmux = <STM32_PINMUX('A', 15, AF4)>;
154					bias-disable;
155					drive-open-drain;
156					slew-rate = <0>;
157				};
158			};
159
160			i2c1_pins_a: i2c1-0 {
161				pins {
162					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
163						 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
164					bias-disable;
165					drive-open-drain;
166					slew-rate = <0>;
167				};
168			};
169
170			i2c2_pins_a: i2c2-0 {
171				pins {
172					pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
173						 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
174					bias-disable;
175					drive-open-drain;
176					slew-rate = <0>;
177				};
178			};
179
180			i2c5_pins_a: i2c5-0 {
181				pins {
182					pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
183						 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
184					bias-disable;
185					drive-open-drain;
186					slew-rate = <0>;
187				};
188			};
189
190			pwm2_pins_a: pwm2-0 {
191				pins {
192					pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
193					bias-pull-down;
194					drive-push-pull;
195					slew-rate = <0>;
196				};
197			};
198
199			pwm8_pins_a: pwm8-0 {
200				pins {
201					pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
202					bias-pull-down;
203					drive-push-pull;
204					slew-rate = <0>;
205				};
206			};
207
208			pwm12_pins_a: pwm12-0 {
209				pins {
210					pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
211					bias-pull-down;
212					drive-push-pull;
213					slew-rate = <0>;
214				};
215			};
216
217			qspi_clk_pins_a: qspi-clk-0 {
218				pins {
219					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
220					bias-disable;
221					drive-push-pull;
222					slew-rate = <3>;
223				};
224			};
225
226			qspi_bk1_pins_a: qspi-bk1-0 {
227				pins1 {
228					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
229						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
230						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
231						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
232					bias-disable;
233					drive-push-pull;
234					slew-rate = <3>;
235				};
236				pins2 {
237					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
238					bias-pull-up;
239					drive-push-pull;
240					slew-rate = <3>;
241				};
242			};
243
244			qspi_bk2_pins_a: qspi-bk2-0 {
245				pins1 {
246					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
247						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
248						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
249						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
250					bias-disable;
251					drive-push-pull;
252					slew-rate = <3>;
253				};
254				pins2 {
255					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
256					bias-pull-up;
257					drive-push-pull;
258					slew-rate = <3>;
259				};
260			};
261			sdmmc1_b4_pins_a: sdmmc1-b4@0 {
262				pins {
263					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
264						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
265						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
266						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
267						 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
268						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
269					slew-rate = <3>;
270					drive-push-pull;
271					bias-disable;
272				};
273			};
274
275			sdmmc1_dir_pins_a: sdmmc1-dir@0 {
276				pins {
277					pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
278						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
279						 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
280						 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
281					slew-rate = <3>;
282					drive-push-pull;
283					bias-pull-up;
284				};
285			};
286			sdmmc2_b4_pins_a: sdmmc2-b4@0 {
287				pins {
288					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
289						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
290						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
291						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
292						 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
293						 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
294					slew-rate = <3>;
295					drive-push-pull;
296					bias-pull-up;
297				};
298			};
299
300			sdmmc2_d47_pins_a: sdmmc2-d47@0 {
301				pins {
302					pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
303						 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
304						 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
305						 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
306					slew-rate = <3>;
307					drive-push-pull;
308					bias-pull-up;
309				};
310			};
311
312			uart4_pins_a: uart4-0 {
313				pins1 {
314					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
315					bias-disable;
316					drive-push-pull;
317					slew-rate = <0>;
318				};
319				pins2 {
320					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
321					bias-disable;
322				};
323			};
324
325			usbotg_hs_pins_a: usbotg_hs-0 {
326				pins {
327					pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
328				};
329			};
330		};
331
332		pinctrl_z: pin-controller-z@54004000 {
333			#address-cells = <1>;
334			#size-cells = <1>;
335			compatible = "st,stm32mp157-z-pinctrl";
336			ranges = <0 0x54004000 0x400>;
337			pins-are-numbered;
338			interrupt-parent = <&exti>;
339			st,syscfg = <&exti 0x60 0xff>;
340
341			gpioz: gpio@54004000 {
342				gpio-controller;
343				#gpio-cells = <2>;
344				interrupt-controller;
345				#interrupt-cells = <2>;
346				reg = <0 0x400>;
347				clocks = <&rcc GPIOZ>;
348				st,bank-name = "GPIOZ";
349				st,bank-ioport = <11>;
350				ngpios = <8>;
351				gpio-ranges = <&pinctrl_z 0 400 8>;
352			};
353
354			i2c4_pins_a: i2c4-0 {
355				pins {
356					pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
357						 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
358					bias-disable;
359					drive-open-drain;
360					slew-rate = <0>;
361				};
362			};
363		};
364	};
365};
366