1*4549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 23d2d115aSPatrick Delaunay/* 33d2d115aSPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 43d2d115aSPatrick Delaunay */ 53d2d115aSPatrick Delaunay 63d2d115aSPatrick Delaunay/* STM32MP157C ED1 and ED2 BOARD configuration 73d2d115aSPatrick Delaunay * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. 83d2d115aSPatrick Delaunay * Reference used NT5CC256M16DP-DI from NANYA 93d2d115aSPatrick Delaunay * 103d2d115aSPatrick Delaunay * DDR type / Platform DDR3/3L 113d2d115aSPatrick Delaunay * freq 533MHz 123d2d115aSPatrick Delaunay * width 32 133d2d115aSPatrick Delaunay * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G 143d2d115aSPatrick Delaunay * DDR density 8 153d2d115aSPatrick Delaunay * timing mode optimized 163d2d115aSPatrick Delaunay * Scheduling/QoS options : type = 2 173d2d115aSPatrick Delaunay * address mapping : RBC 183d2d115aSPatrick Delaunay */ 193d2d115aSPatrick Delaunay 203d2d115aSPatrick Delaunay#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" 213d2d115aSPatrick Delaunay#define DDR_MEM_SPEED 533 223d2d115aSPatrick Delaunay#define DDR_MEM_SIZE 0x40000000 233d2d115aSPatrick Delaunay 243d2d115aSPatrick Delaunay#define DDR_MSTR 0x00040401 253d2d115aSPatrick Delaunay#define DDR_MRCTRL0 0x00000010 263d2d115aSPatrick Delaunay#define DDR_MRCTRL1 0x00000000 273d2d115aSPatrick Delaunay#define DDR_DERATEEN 0x00000000 283d2d115aSPatrick Delaunay#define DDR_DERATEINT 0x00800000 293d2d115aSPatrick Delaunay#define DDR_PWRCTL 0x00000000 303d2d115aSPatrick Delaunay#define DDR_PWRTMG 0x00400010 313d2d115aSPatrick Delaunay#define DDR_HWLPCTL 0x00000000 323d2d115aSPatrick Delaunay#define DDR_RFSHCTL0 0x00210000 333d2d115aSPatrick Delaunay#define DDR_RFSHCTL3 0x00000000 343d2d115aSPatrick Delaunay#define DDR_RFSHTMG 0x0081008B 353d2d115aSPatrick Delaunay#define DDR_CRCPARCTL0 0x00000000 363d2d115aSPatrick Delaunay#define DDR_DRAMTMG0 0x121B2414 373d2d115aSPatrick Delaunay#define DDR_DRAMTMG1 0x000A041C 383d2d115aSPatrick Delaunay#define DDR_DRAMTMG2 0x0608090F 393d2d115aSPatrick Delaunay#define DDR_DRAMTMG3 0x0050400C 403d2d115aSPatrick Delaunay#define DDR_DRAMTMG4 0x08040608 413d2d115aSPatrick Delaunay#define DDR_DRAMTMG5 0x06060403 423d2d115aSPatrick Delaunay#define DDR_DRAMTMG6 0x02020002 433d2d115aSPatrick Delaunay#define DDR_DRAMTMG7 0x00000202 443d2d115aSPatrick Delaunay#define DDR_DRAMTMG8 0x00001005 453d2d115aSPatrick Delaunay#define DDR_DRAMTMG14 0x000000A0 463d2d115aSPatrick Delaunay#define DDR_ZQCTL0 0xC2000040 473d2d115aSPatrick Delaunay#define DDR_DFITMG0 0x02060105 483d2d115aSPatrick Delaunay#define DDR_DFITMG1 0x00000202 493d2d115aSPatrick Delaunay#define DDR_DFILPCFG0 0x07000000 503d2d115aSPatrick Delaunay#define DDR_DFIUPD0 0xC0400003 513d2d115aSPatrick Delaunay#define DDR_DFIUPD1 0x00000000 523d2d115aSPatrick Delaunay#define DDR_DFIUPD2 0x00000000 533d2d115aSPatrick Delaunay#define DDR_DFIPHYMSTR 0x00000000 543d2d115aSPatrick Delaunay#define DDR_ADDRMAP1 0x00080808 553d2d115aSPatrick Delaunay#define DDR_ADDRMAP2 0x00000000 563d2d115aSPatrick Delaunay#define DDR_ADDRMAP3 0x00000000 573d2d115aSPatrick Delaunay#define DDR_ADDRMAP4 0x00001F1F 583d2d115aSPatrick Delaunay#define DDR_ADDRMAP5 0x07070707 593d2d115aSPatrick Delaunay#define DDR_ADDRMAP6 0x0F070707 603d2d115aSPatrick Delaunay#define DDR_ADDRMAP9 0x00000000 613d2d115aSPatrick Delaunay#define DDR_ADDRMAP10 0x00000000 623d2d115aSPatrick Delaunay#define DDR_ADDRMAP11 0x00000000 633d2d115aSPatrick Delaunay#define DDR_ODTCFG 0x06000600 643d2d115aSPatrick Delaunay#define DDR_ODTMAP 0x00000001 653d2d115aSPatrick Delaunay#define DDR_SCHED 0x00001201 663d2d115aSPatrick Delaunay#define DDR_SCHED1 0x00000000 673d2d115aSPatrick Delaunay#define DDR_PERFHPR1 0x01000001 683d2d115aSPatrick Delaunay#define DDR_PERFLPR1 0x08000200 693d2d115aSPatrick Delaunay#define DDR_PERFWR1 0x08000400 703d2d115aSPatrick Delaunay#define DDR_DBG0 0x00000000 713d2d115aSPatrick Delaunay#define DDR_DBG1 0x00000000 723d2d115aSPatrick Delaunay#define DDR_DBGCMD 0x00000000 733d2d115aSPatrick Delaunay#define DDR_POISONCFG 0x00000000 743d2d115aSPatrick Delaunay#define DDR_PCCFG 0x00000010 753d2d115aSPatrick Delaunay#define DDR_PCFGR_0 0x00010000 763d2d115aSPatrick Delaunay#define DDR_PCFGW_0 0x00000000 773d2d115aSPatrick Delaunay#define DDR_PCFGQOS0_0 0x02100B03 783d2d115aSPatrick Delaunay#define DDR_PCFGQOS1_0 0x00800100 793d2d115aSPatrick Delaunay#define DDR_PCFGWQOS0_0 0x01100B03 803d2d115aSPatrick Delaunay#define DDR_PCFGWQOS1_0 0x01000200 813d2d115aSPatrick Delaunay#define DDR_PCFGR_1 0x00010000 823d2d115aSPatrick Delaunay#define DDR_PCFGW_1 0x00000000 833d2d115aSPatrick Delaunay#define DDR_PCFGQOS0_1 0x02100B03 843d2d115aSPatrick Delaunay#define DDR_PCFGQOS1_1 0x00800100 853d2d115aSPatrick Delaunay#define DDR_PCFGWQOS0_1 0x01100B03 863d2d115aSPatrick Delaunay#define DDR_PCFGWQOS1_1 0x01000200 873d2d115aSPatrick Delaunay#define DDR_PGCR 0x01442E02 883d2d115aSPatrick Delaunay#define DDR_PTR0 0x0022AA5B 893d2d115aSPatrick Delaunay#define DDR_PTR1 0x04841104 903d2d115aSPatrick Delaunay#define DDR_PTR2 0x042DA068 913d2d115aSPatrick Delaunay#define DDR_ACIOCR 0x10400812 923d2d115aSPatrick Delaunay#define DDR_DXCCR 0x00000C40 933d2d115aSPatrick Delaunay#define DDR_DSGCR 0xF200001F 943d2d115aSPatrick Delaunay#define DDR_DCR 0x0000000B 953d2d115aSPatrick Delaunay#define DDR_DTPR0 0x38D488D0 963d2d115aSPatrick Delaunay#define DDR_DTPR1 0x098B00D8 973d2d115aSPatrick Delaunay#define DDR_DTPR2 0x10023600 983d2d115aSPatrick Delaunay#define DDR_MR0 0x00000840 993d2d115aSPatrick Delaunay#define DDR_MR1 0x00000000 1003d2d115aSPatrick Delaunay#define DDR_MR2 0x00000208 1013d2d115aSPatrick Delaunay#define DDR_MR3 0x00000000 1023d2d115aSPatrick Delaunay#define DDR_ODTCR 0x00010000 1033d2d115aSPatrick Delaunay#define DDR_ZQ0CR1 0x0000005B 1043d2d115aSPatrick Delaunay#define DDR_DX0GCR 0x0000CE81 1053d2d115aSPatrick Delaunay#define DDR_DX0DLLCR 0x40000000 1063d2d115aSPatrick Delaunay#define DDR_DX0DQTR 0xFFFFFFFF 1073d2d115aSPatrick Delaunay#define DDR_DX0DQSTR 0x3DB02000 1083d2d115aSPatrick Delaunay#define DDR_DX1GCR 0x0000CE81 1093d2d115aSPatrick Delaunay#define DDR_DX1DLLCR 0x40000000 1103d2d115aSPatrick Delaunay#define DDR_DX1DQTR 0xFFFFFFFF 1113d2d115aSPatrick Delaunay#define DDR_DX1DQSTR 0x3DB02000 1123d2d115aSPatrick Delaunay#define DDR_DX2GCR 0x0000CE81 1133d2d115aSPatrick Delaunay#define DDR_DX2DLLCR 0x40000000 1143d2d115aSPatrick Delaunay#define DDR_DX2DQTR 0xFFFFFFFF 1153d2d115aSPatrick Delaunay#define DDR_DX2DQSTR 0x3DB02000 1163d2d115aSPatrick Delaunay#define DDR_DX3GCR 0x0000CE81 1173d2d115aSPatrick Delaunay#define DDR_DX3DLLCR 0x40000000 1183d2d115aSPatrick Delaunay#define DDR_DX3DQTR 0xFFFFFFFF 1193d2d115aSPatrick Delaunay#define DDR_DX3DQSTR 0x3DB02000 1203d2d115aSPatrick Delaunay 1213d2d115aSPatrick Delaunay#include "stm32mp15-ddr.dtsi" 122