1*3d2d115aSPatrick Delaunay/* 2*3d2d115aSPatrick Delaunay * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3*3d2d115aSPatrick Delaunay * 4*3d2d115aSPatrick Delaunay * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5*3d2d115aSPatrick Delaunay */ 6*3d2d115aSPatrick Delaunay 7*3d2d115aSPatrick Delaunay/* STM32MP157C ED1 and ED2 BOARD configuration 8*3d2d115aSPatrick Delaunay * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. 9*3d2d115aSPatrick Delaunay * Reference used NT5CC256M16DP-DI from NANYA 10*3d2d115aSPatrick Delaunay * 11*3d2d115aSPatrick Delaunay * DDR type / Platform DDR3/3L 12*3d2d115aSPatrick Delaunay * freq 533MHz 13*3d2d115aSPatrick Delaunay * width 32 14*3d2d115aSPatrick Delaunay * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G 15*3d2d115aSPatrick Delaunay * DDR density 8 16*3d2d115aSPatrick Delaunay * timing mode optimized 17*3d2d115aSPatrick Delaunay * Scheduling/QoS options : type = 2 18*3d2d115aSPatrick Delaunay * address mapping : RBC 19*3d2d115aSPatrick Delaunay */ 20*3d2d115aSPatrick Delaunay 21*3d2d115aSPatrick Delaunay#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" 22*3d2d115aSPatrick Delaunay#define DDR_MEM_SPEED 533 23*3d2d115aSPatrick Delaunay#define DDR_MEM_SIZE 0x40000000 24*3d2d115aSPatrick Delaunay 25*3d2d115aSPatrick Delaunay#define DDR_MSTR 0x00040401 26*3d2d115aSPatrick Delaunay#define DDR_MRCTRL0 0x00000010 27*3d2d115aSPatrick Delaunay#define DDR_MRCTRL1 0x00000000 28*3d2d115aSPatrick Delaunay#define DDR_DERATEEN 0x00000000 29*3d2d115aSPatrick Delaunay#define DDR_DERATEINT 0x00800000 30*3d2d115aSPatrick Delaunay#define DDR_PWRCTL 0x00000000 31*3d2d115aSPatrick Delaunay#define DDR_PWRTMG 0x00400010 32*3d2d115aSPatrick Delaunay#define DDR_HWLPCTL 0x00000000 33*3d2d115aSPatrick Delaunay#define DDR_RFSHCTL0 0x00210000 34*3d2d115aSPatrick Delaunay#define DDR_RFSHCTL3 0x00000000 35*3d2d115aSPatrick Delaunay#define DDR_RFSHTMG 0x0081008B 36*3d2d115aSPatrick Delaunay#define DDR_CRCPARCTL0 0x00000000 37*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG0 0x121B2414 38*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG1 0x000A041C 39*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG2 0x0608090F 40*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG3 0x0050400C 41*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG4 0x08040608 42*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG5 0x06060403 43*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG6 0x02020002 44*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG7 0x00000202 45*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG8 0x00001005 46*3d2d115aSPatrick Delaunay#define DDR_DRAMTMG14 0x000000A0 47*3d2d115aSPatrick Delaunay#define DDR_ZQCTL0 0xC2000040 48*3d2d115aSPatrick Delaunay#define DDR_DFITMG0 0x02060105 49*3d2d115aSPatrick Delaunay#define DDR_DFITMG1 0x00000202 50*3d2d115aSPatrick Delaunay#define DDR_DFILPCFG0 0x07000000 51*3d2d115aSPatrick Delaunay#define DDR_DFIUPD0 0xC0400003 52*3d2d115aSPatrick Delaunay#define DDR_DFIUPD1 0x00000000 53*3d2d115aSPatrick Delaunay#define DDR_DFIUPD2 0x00000000 54*3d2d115aSPatrick Delaunay#define DDR_DFIPHYMSTR 0x00000000 55*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP1 0x00080808 56*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP2 0x00000000 57*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP3 0x00000000 58*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP4 0x00001F1F 59*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP5 0x07070707 60*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP6 0x0F070707 61*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP9 0x00000000 62*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP10 0x00000000 63*3d2d115aSPatrick Delaunay#define DDR_ADDRMAP11 0x00000000 64*3d2d115aSPatrick Delaunay#define DDR_ODTCFG 0x06000600 65*3d2d115aSPatrick Delaunay#define DDR_ODTMAP 0x00000001 66*3d2d115aSPatrick Delaunay#define DDR_SCHED 0x00001201 67*3d2d115aSPatrick Delaunay#define DDR_SCHED1 0x00000000 68*3d2d115aSPatrick Delaunay#define DDR_PERFHPR1 0x01000001 69*3d2d115aSPatrick Delaunay#define DDR_PERFLPR1 0x08000200 70*3d2d115aSPatrick Delaunay#define DDR_PERFWR1 0x08000400 71*3d2d115aSPatrick Delaunay#define DDR_DBG0 0x00000000 72*3d2d115aSPatrick Delaunay#define DDR_DBG1 0x00000000 73*3d2d115aSPatrick Delaunay#define DDR_DBGCMD 0x00000000 74*3d2d115aSPatrick Delaunay#define DDR_POISONCFG 0x00000000 75*3d2d115aSPatrick Delaunay#define DDR_PCCFG 0x00000010 76*3d2d115aSPatrick Delaunay#define DDR_PCFGR_0 0x00010000 77*3d2d115aSPatrick Delaunay#define DDR_PCFGW_0 0x00000000 78*3d2d115aSPatrick Delaunay#define DDR_PCFGQOS0_0 0x02100B03 79*3d2d115aSPatrick Delaunay#define DDR_PCFGQOS1_0 0x00800100 80*3d2d115aSPatrick Delaunay#define DDR_PCFGWQOS0_0 0x01100B03 81*3d2d115aSPatrick Delaunay#define DDR_PCFGWQOS1_0 0x01000200 82*3d2d115aSPatrick Delaunay#define DDR_PCFGR_1 0x00010000 83*3d2d115aSPatrick Delaunay#define DDR_PCFGW_1 0x00000000 84*3d2d115aSPatrick Delaunay#define DDR_PCFGQOS0_1 0x02100B03 85*3d2d115aSPatrick Delaunay#define DDR_PCFGQOS1_1 0x00800100 86*3d2d115aSPatrick Delaunay#define DDR_PCFGWQOS0_1 0x01100B03 87*3d2d115aSPatrick Delaunay#define DDR_PCFGWQOS1_1 0x01000200 88*3d2d115aSPatrick Delaunay#define DDR_PGCR 0x01442E02 89*3d2d115aSPatrick Delaunay#define DDR_PTR0 0x0022AA5B 90*3d2d115aSPatrick Delaunay#define DDR_PTR1 0x04841104 91*3d2d115aSPatrick Delaunay#define DDR_PTR2 0x042DA068 92*3d2d115aSPatrick Delaunay#define DDR_ACIOCR 0x10400812 93*3d2d115aSPatrick Delaunay#define DDR_DXCCR 0x00000C40 94*3d2d115aSPatrick Delaunay#define DDR_DSGCR 0xF200001F 95*3d2d115aSPatrick Delaunay#define DDR_DCR 0x0000000B 96*3d2d115aSPatrick Delaunay#define DDR_DTPR0 0x38D488D0 97*3d2d115aSPatrick Delaunay#define DDR_DTPR1 0x098B00D8 98*3d2d115aSPatrick Delaunay#define DDR_DTPR2 0x10023600 99*3d2d115aSPatrick Delaunay#define DDR_MR0 0x00000840 100*3d2d115aSPatrick Delaunay#define DDR_MR1 0x00000000 101*3d2d115aSPatrick Delaunay#define DDR_MR2 0x00000208 102*3d2d115aSPatrick Delaunay#define DDR_MR3 0x00000000 103*3d2d115aSPatrick Delaunay#define DDR_ODTCR 0x00010000 104*3d2d115aSPatrick Delaunay#define DDR_ZQ0CR1 0x0000005B 105*3d2d115aSPatrick Delaunay#define DDR_DX0GCR 0x0000CE81 106*3d2d115aSPatrick Delaunay#define DDR_DX0DLLCR 0x40000000 107*3d2d115aSPatrick Delaunay#define DDR_DX0DQTR 0xFFFFFFFF 108*3d2d115aSPatrick Delaunay#define DDR_DX0DQSTR 0x3DB02000 109*3d2d115aSPatrick Delaunay#define DDR_DX1GCR 0x0000CE81 110*3d2d115aSPatrick Delaunay#define DDR_DX1DLLCR 0x40000000 111*3d2d115aSPatrick Delaunay#define DDR_DX1DQTR 0xFFFFFFFF 112*3d2d115aSPatrick Delaunay#define DDR_DX1DQSTR 0x3DB02000 113*3d2d115aSPatrick Delaunay#define DDR_DX2GCR 0x0000CE81 114*3d2d115aSPatrick Delaunay#define DDR_DX2DLLCR 0x40000000 115*3d2d115aSPatrick Delaunay#define DDR_DX2DQTR 0xFFFFFFFF 116*3d2d115aSPatrick Delaunay#define DDR_DX2DQSTR 0x3DB02000 117*3d2d115aSPatrick Delaunay#define DDR_DX3GCR 0x0000CE81 118*3d2d115aSPatrick Delaunay#define DDR_DX3DLLCR 0x40000000 119*3d2d115aSPatrick Delaunay#define DDR_DX3DQTR 0xFFFFFFFF 120*3d2d115aSPatrick Delaunay#define DDR_DX3DQSTR 0x3DB02000 121*3d2d115aSPatrick Delaunay 122*3d2d115aSPatrick Delaunay#include "stm32mp15-ddr.dtsi" 123