1*3d2d115aSPatrick Delaunay/* 2*3d2d115aSPatrick Delaunay * Copyright : STMicroelectronics 2018 3*3d2d115aSPatrick Delaunay * 4*3d2d115aSPatrick Delaunay * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5*3d2d115aSPatrick Delaunay */ 6*3d2d115aSPatrick Delaunay 7*3d2d115aSPatrick Delaunay/ { 8*3d2d115aSPatrick Delaunay soc { 9*3d2d115aSPatrick Delaunay ddr: ddr@0x5A003000{ 10*3d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 11*3d2d115aSPatrick Delaunay 12*3d2d115aSPatrick Delaunay compatible = "st,stm32mp1-ddr"; 13*3d2d115aSPatrick Delaunay 14*3d2d115aSPatrick Delaunay reg = <0x5A003000 0x550 15*3d2d115aSPatrick Delaunay 0x5A004000 0x234>; 16*3d2d115aSPatrick Delaunay 17*3d2d115aSPatrick Delaunay clocks = <&rcc_clk AXIDCG>, 18*3d2d115aSPatrick Delaunay <&rcc_clk DDRC1>, 19*3d2d115aSPatrick Delaunay <&rcc_clk DDRC2>, 20*3d2d115aSPatrick Delaunay <&rcc_clk DDRPHYC>, 21*3d2d115aSPatrick Delaunay <&rcc_clk DDRCAPB>, 22*3d2d115aSPatrick Delaunay <&rcc_clk DDRPHYCAPB>; 23*3d2d115aSPatrick Delaunay 24*3d2d115aSPatrick Delaunay clock-names = "axidcg", 25*3d2d115aSPatrick Delaunay "ddrc1", 26*3d2d115aSPatrick Delaunay "ddrc2", 27*3d2d115aSPatrick Delaunay "ddrphyc", 28*3d2d115aSPatrick Delaunay "ddrcapb", 29*3d2d115aSPatrick Delaunay "ddrphycapb"; 30*3d2d115aSPatrick Delaunay 31*3d2d115aSPatrick Delaunay st,mem-name = DDR_MEM_NAME; 32*3d2d115aSPatrick Delaunay st,mem-speed = <DDR_MEM_SPEED>; 33*3d2d115aSPatrick Delaunay st,mem-size = <DDR_MEM_SIZE>; 34*3d2d115aSPatrick Delaunay 35*3d2d115aSPatrick Delaunay st,ctl-reg = < 36*3d2d115aSPatrick Delaunay DDR_MSTR 37*3d2d115aSPatrick Delaunay DDR_MRCTRL0 38*3d2d115aSPatrick Delaunay DDR_MRCTRL1 39*3d2d115aSPatrick Delaunay DDR_DERATEEN 40*3d2d115aSPatrick Delaunay DDR_DERATEINT 41*3d2d115aSPatrick Delaunay DDR_PWRCTL 42*3d2d115aSPatrick Delaunay DDR_PWRTMG 43*3d2d115aSPatrick Delaunay DDR_HWLPCTL 44*3d2d115aSPatrick Delaunay DDR_RFSHCTL0 45*3d2d115aSPatrick Delaunay DDR_RFSHCTL3 46*3d2d115aSPatrick Delaunay DDR_CRCPARCTL0 47*3d2d115aSPatrick Delaunay DDR_ZQCTL0 48*3d2d115aSPatrick Delaunay DDR_DFITMG0 49*3d2d115aSPatrick Delaunay DDR_DFITMG1 50*3d2d115aSPatrick Delaunay DDR_DFILPCFG0 51*3d2d115aSPatrick Delaunay DDR_DFIUPD0 52*3d2d115aSPatrick Delaunay DDR_DFIUPD1 53*3d2d115aSPatrick Delaunay DDR_DFIUPD2 54*3d2d115aSPatrick Delaunay DDR_DFIPHYMSTR 55*3d2d115aSPatrick Delaunay DDR_ODTMAP 56*3d2d115aSPatrick Delaunay DDR_DBG0 57*3d2d115aSPatrick Delaunay DDR_DBG1 58*3d2d115aSPatrick Delaunay DDR_DBGCMD 59*3d2d115aSPatrick Delaunay DDR_POISONCFG 60*3d2d115aSPatrick Delaunay DDR_PCCFG 61*3d2d115aSPatrick Delaunay >; 62*3d2d115aSPatrick Delaunay 63*3d2d115aSPatrick Delaunay st,ctl-timing = < 64*3d2d115aSPatrick Delaunay DDR_RFSHTMG 65*3d2d115aSPatrick Delaunay DDR_DRAMTMG0 66*3d2d115aSPatrick Delaunay DDR_DRAMTMG1 67*3d2d115aSPatrick Delaunay DDR_DRAMTMG2 68*3d2d115aSPatrick Delaunay DDR_DRAMTMG3 69*3d2d115aSPatrick Delaunay DDR_DRAMTMG4 70*3d2d115aSPatrick Delaunay DDR_DRAMTMG5 71*3d2d115aSPatrick Delaunay DDR_DRAMTMG6 72*3d2d115aSPatrick Delaunay DDR_DRAMTMG7 73*3d2d115aSPatrick Delaunay DDR_DRAMTMG8 74*3d2d115aSPatrick Delaunay DDR_DRAMTMG14 75*3d2d115aSPatrick Delaunay DDR_ODTCFG 76*3d2d115aSPatrick Delaunay >; 77*3d2d115aSPatrick Delaunay 78*3d2d115aSPatrick Delaunay st,ctl-map = < 79*3d2d115aSPatrick Delaunay DDR_ADDRMAP1 80*3d2d115aSPatrick Delaunay DDR_ADDRMAP2 81*3d2d115aSPatrick Delaunay DDR_ADDRMAP3 82*3d2d115aSPatrick Delaunay DDR_ADDRMAP4 83*3d2d115aSPatrick Delaunay DDR_ADDRMAP5 84*3d2d115aSPatrick Delaunay DDR_ADDRMAP6 85*3d2d115aSPatrick Delaunay DDR_ADDRMAP9 86*3d2d115aSPatrick Delaunay DDR_ADDRMAP10 87*3d2d115aSPatrick Delaunay DDR_ADDRMAP11 88*3d2d115aSPatrick Delaunay >; 89*3d2d115aSPatrick Delaunay 90*3d2d115aSPatrick Delaunay st,ctl-perf = < 91*3d2d115aSPatrick Delaunay DDR_SCHED 92*3d2d115aSPatrick Delaunay DDR_SCHED1 93*3d2d115aSPatrick Delaunay DDR_PERFHPR1 94*3d2d115aSPatrick Delaunay DDR_PERFLPR1 95*3d2d115aSPatrick Delaunay DDR_PERFWR1 96*3d2d115aSPatrick Delaunay DDR_PCFGR_0 97*3d2d115aSPatrick Delaunay DDR_PCFGW_0 98*3d2d115aSPatrick Delaunay DDR_PCFGQOS0_0 99*3d2d115aSPatrick Delaunay DDR_PCFGQOS1_0 100*3d2d115aSPatrick Delaunay DDR_PCFGWQOS0_0 101*3d2d115aSPatrick Delaunay DDR_PCFGWQOS1_0 102*3d2d115aSPatrick Delaunay DDR_PCFGR_1 103*3d2d115aSPatrick Delaunay DDR_PCFGW_1 104*3d2d115aSPatrick Delaunay DDR_PCFGQOS0_1 105*3d2d115aSPatrick Delaunay DDR_PCFGQOS1_1 106*3d2d115aSPatrick Delaunay DDR_PCFGWQOS0_1 107*3d2d115aSPatrick Delaunay DDR_PCFGWQOS1_1 108*3d2d115aSPatrick Delaunay >; 109*3d2d115aSPatrick Delaunay 110*3d2d115aSPatrick Delaunay st,phy-reg = < 111*3d2d115aSPatrick Delaunay DDR_PGCR 112*3d2d115aSPatrick Delaunay DDR_ACIOCR 113*3d2d115aSPatrick Delaunay DDR_DXCCR 114*3d2d115aSPatrick Delaunay DDR_DSGCR 115*3d2d115aSPatrick Delaunay DDR_DCR 116*3d2d115aSPatrick Delaunay DDR_ODTCR 117*3d2d115aSPatrick Delaunay DDR_ZQ0CR1 118*3d2d115aSPatrick Delaunay DDR_DX0GCR 119*3d2d115aSPatrick Delaunay DDR_DX1GCR 120*3d2d115aSPatrick Delaunay DDR_DX2GCR 121*3d2d115aSPatrick Delaunay DDR_DX3GCR 122*3d2d115aSPatrick Delaunay >; 123*3d2d115aSPatrick Delaunay 124*3d2d115aSPatrick Delaunay st,phy-timing = < 125*3d2d115aSPatrick Delaunay DDR_PTR0 126*3d2d115aSPatrick Delaunay DDR_PTR1 127*3d2d115aSPatrick Delaunay DDR_PTR2 128*3d2d115aSPatrick Delaunay DDR_DTPR0 129*3d2d115aSPatrick Delaunay DDR_DTPR1 130*3d2d115aSPatrick Delaunay DDR_DTPR2 131*3d2d115aSPatrick Delaunay DDR_MR0 132*3d2d115aSPatrick Delaunay DDR_MR1 133*3d2d115aSPatrick Delaunay DDR_MR2 134*3d2d115aSPatrick Delaunay DDR_MR3 135*3d2d115aSPatrick Delaunay >; 136*3d2d115aSPatrick Delaunay 137*3d2d115aSPatrick Delaunay st,phy-cal = < 138*3d2d115aSPatrick Delaunay DDR_DX0DLLCR 139*3d2d115aSPatrick Delaunay DDR_DX0DQTR 140*3d2d115aSPatrick Delaunay DDR_DX0DQSTR 141*3d2d115aSPatrick Delaunay DDR_DX1DLLCR 142*3d2d115aSPatrick Delaunay DDR_DX1DQTR 143*3d2d115aSPatrick Delaunay DDR_DX1DQSTR 144*3d2d115aSPatrick Delaunay DDR_DX2DLLCR 145*3d2d115aSPatrick Delaunay DDR_DX2DQTR 146*3d2d115aSPatrick Delaunay DDR_DX2DQSTR 147*3d2d115aSPatrick Delaunay DDR_DX3DLLCR 148*3d2d115aSPatrick Delaunay DDR_DX3DQTR 149*3d2d115aSPatrick Delaunay DDR_DX3DQSTR 150*3d2d115aSPatrick Delaunay >; 151*3d2d115aSPatrick Delaunay 152*3d2d115aSPatrick Delaunay status = "okay"; 153*3d2d115aSPatrick Delaunay }; 154*3d2d115aSPatrick Delaunay }; 155*3d2d115aSPatrick Delaunay}; 156