xref: /openbmc/u-boot/arch/arm/dts/stm32h743.dtsi (revision dd1033e4)
1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44#include "armv7-m.dtsi"
45#include <dt-bindings/clock/stm32h7-clks.h>
46#include <dt-bindings/mfd/stm32h7-rcc.h>
47
48/ {
49	clocks {
50		clk_hse: clk-hse {
51			#clock-cells = <0>;
52			compatible = "fixed-clock";
53			clock-frequency = <25000000>;
54		};
55
56		clk_lse: clk-lse {
57			#clock-cells = <0>;
58			compatible = "fixed-clock";
59			clock-frequency = <32768>;
60		};
61
62		clk_i2s: i2s_ckin {
63			#clock-cells = <0>;
64			compatible = "fixed-clock";
65			clock-frequency = <0>;
66		};
67	};
68
69	soc {
70		rcc: rcc@58024400 {
71			#clock-cells = <1>;
72			#reset-cells = <1>;
73			compatible = "st,stm32h743-rcc", "st,stm32-rcc";
74			reg = <0x58024400 0x400>;
75			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
76			st,syscfg = <&pwrcfg>;
77		};
78
79		usart1: serial@40011000 {
80			compatible = "st,stm32h7-uart";
81			reg = <0x40011000 0x400>;
82			interrupts = <37>;
83			status = "disabled";
84			clocks = <&rcc USART1_CK>;
85		};
86
87		usart2: serial@40004400 {
88			compatible = "st,stm32h7-uart";
89			reg = <0x40004400 0x400>;
90			interrupts = <38>;
91			status = "disabled";
92			clocks = <&rcc USART2_CK>;
93		};
94
95		timer5: timer@40000c00 {
96			compatible = "st,stm32-timer";
97			reg = <0x40000c00 0x400>;
98			interrupts = <50>;
99			clocks = <&rcc TIM5_CK>;
100		};
101
102		pwrcfg: power-config@58024800 {
103			compatible = "syscon";
104			reg = <0x58024800 0x400>;
105		};
106
107		fmc: fmc@52004000 {
108			compatible = "st,stm32h7-fmc";
109			reg = <0x52004000 0x1000>;
110			clocks = <&rcc FMC_CK>;
111		};
112
113		clk_hsi: clk-hsi {
114			#clock-cells = <0>;
115			compatible = "fixed-clock";
116			clock-frequency = <64000000>;
117		};
118
119		clk_csi: clk-csi {
120			#clock-cells = <0>;
121			compatible = "fixed-clock";
122			clock-frequency = <4000000>;
123		};
124
125		sdmmc1: sdmmc@52007000 {
126			compatible = "st,stm32-sdmmc2";
127			reg = <0x52007000 0x1000>;
128			interrupts = <49>;
129			clocks = <&rcc SDMMC1_CK>;
130			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
131			st,idma = <1>;
132			cap-sd-highspeed;
133			cap-mmc-highspeed;
134			status = "disabled";
135		};
136	};
137};
138
139&systick {
140	clock-frequency = <250000000>;
141	status = "okay";
142};
143