xref: /openbmc/u-boot/arch/arm/dts/stm32h743-pinctrl.dtsi (revision d983a0f00853624b31d30811cdd45180b6682636)
1/*
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
44
45/ {
46	soc {
47		pin-controller {
48			#address-cells = <1>;
49			#size-cells = <1>;
50			compatible = "st,stm32h743-pinctrl";
51			ranges = <0 0x58020000 0x3000>;
52			pins-are-numbered;
53
54			gpioa: gpio@58020000 {
55				gpio-controller;
56				#gpio-cells = <2>;
57				reg = <0x0 0x400>;
58				clocks = <&timer_clk>;
59				st,bank-name = "GPIOA";
60			};
61
62			gpiob: gpio@58020400 {
63				gpio-controller;
64				#gpio-cells = <2>;
65				reg = <0x400 0x400>;
66				clocks = <&timer_clk>;
67				st,bank-name = "GPIOB";
68			};
69
70			gpioc: gpio@58020800 {
71				gpio-controller;
72				#gpio-cells = <2>;
73				reg = <0x800 0x400>;
74				clocks = <&timer_clk>;
75				st,bank-name = "GPIOC";
76			};
77
78			gpiod: gpio@58020c00 {
79				gpio-controller;
80				#gpio-cells = <2>;
81				reg = <0xc00 0x400>;
82				clocks = <&timer_clk>;
83				st,bank-name = "GPIOD";
84			};
85
86			gpioe: gpio@58021000 {
87				gpio-controller;
88				#gpio-cells = <2>;
89				reg = <0x1000 0x400>;
90				clocks = <&timer_clk>;
91				st,bank-name = "GPIOE";
92			};
93
94			gpiof: gpio@58021400 {
95				gpio-controller;
96				#gpio-cells = <2>;
97				reg = <0x1400 0x400>;
98				clocks = <&timer_clk>;
99				st,bank-name = "GPIOF";
100			};
101
102			gpiog: gpio@58021800 {
103				gpio-controller;
104				#gpio-cells = <2>;
105				reg = <0x1800 0x400>;
106				clocks = <&timer_clk>;
107				st,bank-name = "GPIOG";
108			};
109
110			gpioh: gpio@58021c00 {
111				gpio-controller;
112				#gpio-cells = <2>;
113				reg = <0x1c00 0x400>;
114				clocks = <&timer_clk>;
115				st,bank-name = "GPIOH";
116			};
117
118			gpioi: gpio@58022000 {
119				gpio-controller;
120				#gpio-cells = <2>;
121				reg = <0x2000 0x400>;
122				clocks = <&timer_clk>;
123				st,bank-name = "GPIOI";
124			};
125
126			gpioj: gpio@58022400 {
127				gpio-controller;
128				#gpio-cells = <2>;
129				reg = <0x2400 0x400>;
130				clocks = <&timer_clk>;
131				st,bank-name = "GPIOJ";
132			};
133
134			gpiok: gpio@58022800 {
135				gpio-controller;
136				#gpio-cells = <2>;
137				reg = <0x2800 0x400>;
138				clocks = <&timer_clk>;
139				st,bank-name = "GPIOK";
140			};
141
142			usart1_pins: usart1@0 {
143				pins1 {
144					pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
145					bias-disable;
146					drive-push-pull;
147					slew-rate = <0>;
148				};
149				pins2 {
150					pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
151					bias-disable;
152				};
153			};
154
155			usart2_pins: usart2@0 {
156				pins1 {
157					pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
158					bias-disable;
159					drive-push-pull;
160					slew-rate = <0>;
161				};
162				pins2 {
163					pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
164					bias-disable;
165				};
166			};
167		};
168	};
169};
170