1/* 2 * Copyright 2016 - Vikas Manocha <vikas.manocha@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/dts-v1/; 44#include "stm32f746.dtsi" 45#include <dt-bindings/memory/stm32-sdram.h> 46#include <dt-bindings/gpio/gpio.h> 47 48/ { 49 model = "STMicroelectronics STM32F769-DISCO board"; 50 compatible = "st,stm32f769-disco", "st,stm32f7"; 51 52 chosen { 53 bootargs = "root=/dev/ram rdinit=/linuxrc"; 54 stdout-path = "serial0:115200n8"; 55 }; 56 57 memory { 58 reg = <0xC0000000 0x1000000>; 59 }; 60 61 aliases { 62 serial0 = &usart1; 63 spi0 = &qspi; 64 mmc0 = &sdio2; 65 /* Aliases for gpios so as to use sequence */ 66 gpio0 = &gpioa; 67 gpio1 = &gpiob; 68 gpio2 = &gpioc; 69 gpio3 = &gpiod; 70 gpio4 = &gpioe; 71 gpio5 = &gpiof; 72 gpio6 = &gpiog; 73 gpio7 = &gpioh; 74 gpio8 = &gpioi; 75 gpio9 = &gpioj; 76 gpio10 = &gpiok; 77 }; 78 79 led1 { 80 compatible = "st,led1"; 81 led-gpio = <&gpioj 5 0>; 82 }; 83 84 button1 { 85 compatible = "st,button1"; 86 button-gpio = <&gpioa 0 0>; 87 }; 88}; 89 90&clk_hse { 91 clock-frequency = <25000000>; 92}; 93 94&pinctrl { 95 usart1_pins_a: usart1@0 { 96 pins1 { 97 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 98 bias-disable; 99 drive-push-pull; 100 slew-rate = <2>; 101 }; 102 pins2 { 103 pinmux = <STM32F746_PA10_FUNC_USART1_RX>; 104 bias-disable; 105 }; 106 }; 107 108 ethernet_mii: mii@0 { 109 pins { 110 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 111 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 112 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 113 <STM32F746_PA2_FUNC_ETH_MDIO>, 114 <STM32F746_PC1_FUNC_ETH_MDC>, 115 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 116 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 117 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 118 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 119 slew-rate = <2>; 120 }; 121 }; 122 123 qspi_pins: qspi@0 { 124 pins { 125 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 126 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 127 <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>, 128 <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>, 129 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 130 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 131 slew-rate = <2>; 132 }; 133 }; 134 135 fmc_pins: fmc@0 { 136 pins { 137 pinmux = <STM32F746_PI10_FUNC_FMC_D31>, 138 <STM32F746_PI9_FUNC_FMC_D30>, 139 <STM32F746_PI7_FUNC_FMC_D29>, 140 <STM32F746_PI6_FUNC_FMC_D28>, 141 <STM32F746_PI3_FUNC_FMC_D27>, 142 <STM32F746_PI2_FUNC_FMC_D26>, 143 <STM32F746_PI1_FUNC_FMC_D25>, 144 <STM32F746_PI0_FUNC_FMC_D24>, 145 <STM32F746_PH15_FUNC_FMC_D23>, 146 <STM32F746_PH14_FUNC_FMC_D22>, 147 <STM32F746_PH13_FUNC_FMC_D21>, 148 <STM32F746_PH12_FUNC_FMC_D20>, 149 <STM32F746_PH11_FUNC_FMC_D19>, 150 <STM32F746_PH10_FUNC_FMC_D18>, 151 <STM32F746_PH9_FUNC_FMC_D17>, 152 <STM32F746_PH8_FUNC_FMC_D16>, 153 154 <STM32F746_PD10_FUNC_FMC_D15>, 155 <STM32F746_PD9_FUNC_FMC_D14>, 156 <STM32F746_PD8_FUNC_FMC_D13>, 157 <STM32F746_PE15_FUNC_FMC_D12>, 158 <STM32F746_PE14_FUNC_FMC_D11>, 159 <STM32F746_PE13_FUNC_FMC_D10>, 160 <STM32F746_PE12_FUNC_FMC_D9>, 161 <STM32F746_PE11_FUNC_FMC_D8>, 162 <STM32F746_PE10_FUNC_FMC_D7>, 163 <STM32F746_PE9_FUNC_FMC_D6>, 164 <STM32F746_PE8_FUNC_FMC_D5>, 165 <STM32F746_PE7_FUNC_FMC_D4>, 166 <STM32F746_PD1_FUNC_FMC_D3>, 167 <STM32F746_PD0_FUNC_FMC_D2>, 168 <STM32F746_PD15_FUNC_FMC_D1>, 169 <STM32F746_PD14_FUNC_FMC_D0>, 170 171 <STM32F746_PI5_FUNC_FMC_NBL3>, 172 <STM32F746_PI4_FUNC_FMC_NBL2>, 173 <STM32F746_PE1_FUNC_FMC_NBL1>, 174 <STM32F746_PE0_FUNC_FMC_NBL0>, 175 176 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, 177 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, 178 179 <STM32F746_PG1_FUNC_FMC_A11>, 180 <STM32F746_PG0_FUNC_FMC_A10>, 181 <STM32F746_PF15_FUNC_FMC_A9>, 182 <STM32F746_PF14_FUNC_FMC_A8>, 183 <STM32F746_PF13_FUNC_FMC_A7>, 184 <STM32F746_PF12_FUNC_FMC_A6>, 185 <STM32F746_PF5_FUNC_FMC_A5>, 186 <STM32F746_PF4_FUNC_FMC_A4>, 187 <STM32F746_PF3_FUNC_FMC_A3>, 188 <STM32F746_PF2_FUNC_FMC_A2>, 189 <STM32F746_PF1_FUNC_FMC_A1>, 190 <STM32F746_PF0_FUNC_FMC_A0>, 191 192 <STM32F746_PH3_FUNC_FMC_SDNE0>, 193 <STM32F746_PH5_FUNC_FMC_SDNWE>, 194 <STM32F746_PF11_FUNC_FMC_SDNRAS>, 195 <STM32F746_PG15_FUNC_FMC_SDNCAS>, 196 <STM32F746_PH2_FUNC_FMC_SDCKE0>, 197 <STM32F746_PG8_FUNC_FMC_SDCLK>; 198 slew-rate = <2>; 199 }; 200 }; 201}; 202 203&usart1 { 204 pinctrl-0 = <&usart1_pins_a>; 205 pinctrl-names = "default"; 206 status = "okay"; 207}; 208 209&fmc { 210 pinctrl-0 = <&fmc_pins>; 211 pinctrl-names = "default"; 212 status = "okay"; 213 214 /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ 215 bank1: bank@0 { 216 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4 217 CAS_3 SDCLK_2 RD_BURST_EN 218 RD_PIPE_DL_0>; 219 st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 220 TRP_2 TRCD_2>; 221 /* refcount = (64msec/total_row_sdram)*freq - 20 */ 222 st,sdram-refcount = < 1542 >; 223 }; 224}; 225 226&mac { 227 status = "okay"; 228 pinctrl-0 = <ðernet_mii>; 229 phy-mode = "rmii"; 230 phy-handle = <&phy0>; 231 232 mdio0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "snps,dwmac-mdio"; 236 phy0: ethernet-phy@0 { 237 reg = <0>; 238 }; 239 }; 240}; 241 242&qspi { 243 pinctrl-0 = <&qspi_pins>; 244 status = "okay"; 245 246 qflash0: n25q128a { 247 #address-cells = <1>; 248 #size-cells = <1>; 249 compatible = "micron,n25q128a13", "spi-flash"; 250 spi-max-frequency = <108000000>; 251 spi-tx-bus-width = <1>; 252 spi-rx-bus-width = <1>; 253 memory-map = <0x90000000 0x1000000>; 254 reg = <0>; 255 }; 256}; 257 258&sdio2 { 259 status = "okay"; 260 cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; 261 pinctrl-names = "default", "opendrain"; 262 pinctrl-0 = <&sdio_pins_b>; 263 pinctrl-1 = <&sdio_pins_od_b>; 264 bus-width = <4>; 265 max-frequency = <25000000>; 266}; 267