1/* 2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> 3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> 4 * 5 * Based on: 6 * stm32f429.dtsi from Linux 7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This file is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "armv7-m.dtsi" 49#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> 50 51/ { 52 clocks { 53 clk_hse: clk-hse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58}; 59 60 soc { 61 u-boot,dm-pre-reloc; 62 mac: ethernet@40028000 { 63 compatible = "st,stm32-dwmac"; 64 reg = <0x40028000 0x8000>; 65 reg-names = "stmmaceth"; 66 interrupts = <61>, <62>; 67 interrupt-names = "macirq", "eth_wake_irq"; 68 snps,pbl = <8>; 69 snps,mixed-burst; 70 dma-ranges; 71 status = "disabled"; 72 }; 73 74 fmc: fmc@A0000000 { 75 compatible = "st,stm32-fmc"; 76 reg = <0xA0000000 0x1000>; 77 clocks = <&rcc 0 64>; 78 u-boot,dm-pre-reloc; 79 }; 80 81 qspi: quadspi@A0001000 { 82 compatible = "st,stm32-qspi"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 86 reg-names = "QuadSPI", "QuadSPI-memory"; 87 interrupts = <92>; 88 spi-max-frequency = <108000000>; 89 clocks = <&rcc 0 65>; 90 status = "disabled"; 91 }; 92 usart1: serial@40011000 { 93 compatible = "st,stm32-usart", "st,stm32-uart"; 94 reg = <0x40011000 0x400>; 95 interrupts = <37>; 96 clocks = <&rcc 0 164>; 97 status = "disabled"; 98 u-boot,dm-pre-reloc; 99 }; 100 rcc: rcc@40023810 { 101 #reset-cells = <1>; 102 #clock-cells = <2>; 103 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 104 reg = <0x40023800 0x400>; 105 clocks = <&clk_hse>; 106 u-boot,dm-pre-reloc; 107 }; 108 109 pinctrl: pin-controller { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 compatible = "st,stm32f746-pinctrl"; 113 ranges = <0 0x40020000 0x3000>; 114 u-boot,dm-pre-reloc; 115 pins-are-numbered; 116 117 usart1_pins_a: usart1@0 { 118 pins1 { 119 pinmux = <STM32F746_PA9_FUNC_USART1_TX>; 120 bias-disable; 121 drive-push-pull; 122 slew-rate = <2>; 123 }; 124 pins2 { 125 pinmux = <STM32F746_PB7_FUNC_USART1_RX>; 126 bias-disable; 127 }; 128 }; 129 ethernet_mii: mii@0 { 130 pins { 131 pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, 132 <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, 133 <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, 134 <STM32F746_PA2_FUNC_ETH_MDIO>, 135 <STM32F746_PC1_FUNC_ETH_MDC>, 136 <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, 137 <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, 138 <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, 139 <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; 140 slew-rate = <2>; 141 }; 142 }; 143 qspi_pins: qspi@0{ 144 pins { 145 pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, 146 <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, 147 <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, 148 <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, 149 <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, 150 <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; 151 slew-rate = <2>; 152 }; 153 }; 154 155 fmc_pins: fmc@0 { 156 pins { 157 pinmux = <STM32F746_PD10_FUNC_FMC_D15>, 158 <STM32F746_PD9_FUNC_FMC_D14>, 159 <STM32F746_PD8_FUNC_FMC_D13>, 160 <STM32F746_PE15_FUNC_FMC_D12>, 161 <STM32F746_PE14_FUNC_FMC_D11>, 162 <STM32F746_PE13_FUNC_FMC_D10>, 163 <STM32F746_PE12_FUNC_FMC_D9>, 164 <STM32F746_PE11_FUNC_FMC_D8>, 165 <STM32F746_PE10_FUNC_FMC_D7>, 166 <STM32F746_PE9_FUNC_FMC_D6>, 167 <STM32F746_PE8_FUNC_FMC_D5>, 168 <STM32F746_PE7_FUNC_FMC_D4>, 169 <STM32F746_PD1_FUNC_FMC_D3>, 170 <STM32F746_PD0_FUNC_FMC_D2>, 171 <STM32F746_PD15_FUNC_FMC_D1>, 172 <STM32F746_PD14_FUNC_FMC_D0>, 173 174 <STM32F746_PE1_FUNC_FMC_NBL1>, 175 <STM32F746_PE0_FUNC_FMC_NBL0>, 176 177 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, 178 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, 179 180 <STM32F746_PG1_FUNC_FMC_A11>, 181 <STM32F746_PG0_FUNC_FMC_A10>, 182 <STM32F746_PF15_FUNC_FMC_A9>, 183 <STM32F746_PF14_FUNC_FMC_A8>, 184 <STM32F746_PF13_FUNC_FMC_A7>, 185 <STM32F746_PF12_FUNC_FMC_A6>, 186 <STM32F746_PF5_FUNC_FMC_A5>, 187 <STM32F746_PF4_FUNC_FMC_A4>, 188 <STM32F746_PF3_FUNC_FMC_A3>, 189 <STM32F746_PF2_FUNC_FMC_A2>, 190 <STM32F746_PF1_FUNC_FMC_A1>, 191 <STM32F746_PF0_FUNC_FMC_A0>, 192 193 <STM32F746_PH3_FUNC_FMC_SDNE0>, 194 <STM32F746_PH5_FUNC_FMC_SDNWE>, 195 <STM32F746_PF11_FUNC_FMC_SDNRAS>, 196 <STM32F746_PG15_FUNC_FMC_SDNCAS>, 197 <STM32F746_PC3_FUNC_FMC_SDCKE0>, 198 <STM32F746_PG8_FUNC_FMC_SDCLK>; 199 slew-rate = <2>; 200 }; 201 }; 202 203 }; 204 }; 205}; 206 207&systick { 208 status = "okay"; 209}; 210