1/* 2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> 3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> 4 * 5 * Based on: 6 * stm32f429.dtsi from Linux 7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This file is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "armv7-m.dtsi" 49#include <dt-bindings/pinctrl/stm32f746-pinfunc.h> 50#include <dt-bindings/clock/stm32fx-clock.h> 51#include <dt-bindings/mfd/stm32f7-rcc.h> 52 53/ { 54 clocks { 55 clk_hse: clk-hse { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <0>; 59 }; 60}; 61 62 soc { 63 u-boot,dm-pre-reloc; 64 mac: ethernet@40028000 { 65 compatible = "st,stm32-dwmac"; 66 reg = <0x40028000 0x8000>; 67 reg-names = "stmmaceth"; 68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, 69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, 70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; 71 interrupts = <61>, <62>; 72 interrupt-names = "macirq", "eth_wake_irq"; 73 snps,pbl = <8>; 74 snps,mixed-burst; 75 dma-ranges; 76 status = "disabled"; 77 }; 78 79 fmc: fmc@A0000000 { 80 compatible = "st,stm32-fmc"; 81 reg = <0xA0000000 0x1000>; 82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; 83 u-boot,dm-pre-reloc; 84 }; 85 86 qspi: quadspi@A0001000 { 87 compatible = "st,stm32-qspi"; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 91 reg-names = "QuadSPI", "QuadSPI-memory"; 92 interrupts = <92>; 93 spi-max-frequency = <108000000>; 94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; 95 status = "disabled"; 96 }; 97 usart1: serial@40011000 { 98 compatible = "st,stm32f7-usart", "st,stm32f7-uart"; 99 reg = <0x40011000 0x400>; 100 interrupts = <37>; 101 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; 102 status = "disabled"; 103 u-boot,dm-pre-reloc; 104 }; 105 106 pwrcfg: power-config@58024800 { 107 compatible = "syscon"; 108 reg = <0x40007000 0x400>; 109 }; 110 111 rcc: rcc@40023810 { 112 #reset-cells = <1>; 113 #clock-cells = <2>; 114 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 115 reg = <0x40023800 0x400>; 116 clocks = <&clk_hse>; 117 st,syscfg = <&pwrcfg>; 118 u-boot,dm-pre-reloc; 119 }; 120 121 pinctrl: pin-controller { 122 #address-cells = <1>; 123 #size-cells = <1>; 124 compatible = "st,stm32f746-pinctrl"; 125 ranges = <0 0x40020000 0x3000>; 126 u-boot,dm-pre-reloc; 127 pins-are-numbered; 128 129 gpioa: gpio@40020000 { 130 gpio-controller; 131 #gpio-cells = <2>; 132 compatible = "st,stm32-gpio"; 133 reg = <0x0 0x400>; 134 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; 135 st,bank-name = "GPIOA"; 136 u-boot,dm-pre-reloc; 137 }; 138 139 gpiob: gpio@40020400 { 140 gpio-controller; 141 #gpio-cells = <2>; 142 compatible = "st,stm32-gpio"; 143 reg = <0x400 0x400>; 144 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; 145 st,bank-name = "GPIOB"; 146 u-boot,dm-pre-reloc; 147 }; 148 149 150 gpioc: gpio@40020800 { 151 gpio-controller; 152 #gpio-cells = <2>; 153 compatible = "st,stm32-gpio"; 154 reg = <0x800 0x400>; 155 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; 156 st,bank-name = "GPIOC"; 157 u-boot,dm-pre-reloc; 158 }; 159 160 gpiod: gpio@40020c00 { 161 gpio-controller; 162 #gpio-cells = <2>; 163 compatible = "st,stm32-gpio"; 164 reg = <0xc00 0x400>; 165 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; 166 st,bank-name = "GPIOD"; 167 u-boot,dm-pre-reloc; 168 }; 169 170 gpioe: gpio@40021000 { 171 gpio-controller; 172 #gpio-cells = <2>; 173 compatible = "st,stm32-gpio"; 174 reg = <0x1000 0x400>; 175 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; 176 st,bank-name = "GPIOE"; 177 u-boot,dm-pre-reloc; 178 }; 179 180 gpiof: gpio@40021400 { 181 gpio-controller; 182 #gpio-cells = <2>; 183 compatible = "st,stm32-gpio"; 184 reg = <0x1400 0x400>; 185 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; 186 st,bank-name = "GPIOF"; 187 u-boot,dm-pre-reloc; 188 }; 189 190 gpiog: gpio@40021800 { 191 gpio-controller; 192 #gpio-cells = <2>; 193 compatible = "st,stm32-gpio"; 194 reg = <0x1800 0x400>; 195 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; 196 st,bank-name = "GPIOG"; 197 u-boot,dm-pre-reloc; 198 }; 199 200 gpioh: gpio@40021c00 { 201 gpio-controller; 202 #gpio-cells = <2>; 203 compatible = "st,stm32-gpio"; 204 reg = <0x1c00 0x400>; 205 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; 206 st,bank-name = "GPIOH"; 207 u-boot,dm-pre-reloc; 208 }; 209 210 gpioi: gpio@40022000 { 211 gpio-controller; 212 #gpio-cells = <2>; 213 compatible = "st,stm32-gpio"; 214 reg = <0x2000 0x400>; 215 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; 216 st,bank-name = "GPIOI"; 217 u-boot,dm-pre-reloc; 218 }; 219 220 gpioj: gpio@40022400 { 221 gpio-controller; 222 #gpio-cells = <2>; 223 compatible = "st,stm32-gpio"; 224 reg = <0x2400 0x400>; 225 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; 226 st,bank-name = "GPIOJ"; 227 u-boot,dm-pre-reloc; 228 }; 229 230 gpiok: gpio@40022800 { 231 gpio-controller; 232 #gpio-cells = <2>; 233 compatible = "st,stm32-gpio"; 234 reg = <0x2800 0x400>; 235 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; 236 st,bank-name = "GPIOK"; 237 u-boot,dm-pre-reloc; 238 }; 239 240 sdio_pins: sdio_pins@0 { 241 pins { 242 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, 243 <STM32F746_PC9_FUNC_SDMMC1_D1>, 244 <STM32F746_PC10_FUNC_SDMMC1_D2>, 245 <STM32F746_PC11_FUNC_SDMMC1_D3>, 246 <STM32F746_PC12_FUNC_SDMMC1_CK>, 247 <STM32F746_PD2_FUNC_SDMMC1_CMD>; 248 drive-push-pull; 249 slew-rate = <2>; 250 }; 251 }; 252 253 sdio_pins_od: sdio_pins_od@0 { 254 pins1 { 255 pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>, 256 <STM32F746_PC9_FUNC_SDMMC1_D1>, 257 <STM32F746_PC10_FUNC_SDMMC1_D2>, 258 <STM32F746_PC11_FUNC_SDMMC1_D3>, 259 <STM32F746_PC12_FUNC_SDMMC1_CK>; 260 drive-push-pull; 261 slew-rate = <2>; 262 }; 263 264 pins2 { 265 pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>; 266 drive-open-drain; 267 slew-rate = <2>; 268 }; 269 }; 270 271 sdio_pins_b: sdio_pins_b@0 { 272 pins { 273 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, 274 <STM32F769_PG10_FUNC_SDMMC2_D1>, 275 <STM32F769_PB3_FUNC_SDMMC2_D2>, 276 <STM32F769_PB4_FUNC_SDMMC2_D3>, 277 <STM32F769_PD6_FUNC_SDMMC2_CLK>, 278 <STM32F769_PD7_FUNC_SDMMC2_CMD>; 279 drive-push-pull; 280 slew-rate = <2>; 281 }; 282 }; 283 284 sdio_pins_od_b: sdio_pins_od_b@0 { 285 pins1 { 286 pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>, 287 <STM32F769_PG10_FUNC_SDMMC2_D1>, 288 <STM32F769_PB3_FUNC_SDMMC2_D2>, 289 <STM32F769_PB4_FUNC_SDMMC2_D3>, 290 <STM32F769_PD6_FUNC_SDMMC2_CLK>; 291 drive-push-pull; 292 slew-rate = <2>; 293 }; 294 295 pins2 { 296 pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>; 297 drive-open-drain; 298 slew-rate = <2>; 299 }; 300 }; 301 302 }; 303 sdio: sdio@40012c00 { 304 compatible = "st,stm32f4xx-sdio"; 305 reg = <0x40012c00 0x400>; 306 clocks = <&rcc 0 171>; 307 interrupts = <49>; 308 status = "disabled"; 309 pinctrl-0 = <&sdio_pins>; 310 pinctrl-1 = <&sdio_pins_od>; 311 pinctrl-names = "default", "opendrain"; 312 max-frequency = <48000000>; 313 }; 314 315 sdio2: sdio2@40011c00 { 316 compatible = "st,stm32f4xx-sdio"; 317 reg = <0x40011c00 0x400>; 318 clocks = <&rcc 0 167>; 319 interrupts = <103>; 320 status = "disabled"; 321 pinctrl-0 = <&sdio_pins_b>; 322 pinctrl-1 = <&sdio_pins_od_b>; 323 pinctrl-names = "default", "opendrain"; 324 max-frequency = <48000000>; 325 }; 326 327 timer5: timer@40000c00 { 328 compatible = "st,stm32-timer"; 329 reg = <0x40000c00 0x400>; 330 interrupts = <50>; 331 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 332 }; 333 334 ltdc: display-controller@40016800 { 335 compatible = "st,stm32-ltdc"; 336 reg = <0x40016800 0x200>; 337 resets = <&rcc STM32F7_APB2_RESET(LTDC)>; 338 clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; 339 u-boot,dm-pre-reloc; 340 status = "disabled"; 341 }; 342 }; 343}; 344 345&systick { 346 status = "okay"; 347}; 348