xref: /openbmc/u-boot/arch/arm/dts/stm32f746.dtsi (revision 57efeb04)
1/*
2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
4 *
5 * Based on:
6 * stm32f429.dtsi from Linux
7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 *  a) This file is free software; you can redistribute it and/or
15 *     modify it under the terms of the GNU General Public License as
16 *     published by the Free Software Foundation; either version 2 of the
17 *     License, or (at your option) any later version.
18 *
19 *     This file is distributed in the hope that it will be useful,
20 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22 *     GNU General Public License for more details.
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "armv7-m.dtsi"
49#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
50#include <dt-bindings/clock/stm32fx-clock.h>
51#include <dt-bindings/mfd/stm32f7-rcc.h>
52
53/ {
54	clocks {
55		clk_hse: clk-hse {
56			#clock-cells = <0>;
57			compatible = "fixed-clock";
58			clock-frequency = <0>;
59		};
60};
61
62	soc {
63		u-boot,dm-pre-reloc;
64		mac: ethernet@40028000 {
65			compatible = "st,stm32-dwmac";
66			reg = <0x40028000 0x8000>;
67			reg-names = "stmmaceth";
68			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
71			interrupts = <61>, <62>;
72			interrupt-names = "macirq", "eth_wake_irq";
73			snps,pbl = <8>;
74			snps,mixed-burst;
75			dma-ranges;
76			status = "disabled";
77		};
78
79		fmc: fmc@A0000000 {
80			compatible = "st,stm32-fmc";
81			reg = <0xA0000000 0x1000>;
82			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
83			u-boot,dm-pre-reloc;
84		};
85
86		qspi: quadspi@A0001000 {
87			compatible = "st,stm32-qspi";
88			#address-cells = <1>;
89			#size-cells = <0>;
90			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
91			reg-names = "qspi", "qspi_mm";
92			interrupts = <92>;
93			spi-max-frequency = <108000000>;
94			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
96			status = "disabled";
97		};
98		usart1: serial@40011000 {
99			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
100			reg = <0x40011000 0x400>;
101			interrupts = <37>;
102			clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
103			status = "disabled";
104			u-boot,dm-pre-reloc;
105		};
106
107		pwrcfg: power-config@58024800 {
108			compatible = "syscon";
109			reg = <0x40007000 0x400>;
110		};
111
112		rcc: rcc@40023810 {
113			#reset-cells = <1>;
114			#clock-cells = <2>;
115			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
116			reg = <0x40023800 0x400>;
117			clocks = <&clk_hse>;
118			st,syscfg = <&pwrcfg>;
119			u-boot,dm-pre-reloc;
120		};
121
122		pinctrl: pin-controller {
123			#address-cells = <1>;
124			#size-cells = <1>;
125			compatible = "st,stm32f746-pinctrl";
126			ranges = <0 0x40020000 0x3000>;
127			u-boot,dm-pre-reloc;
128			pins-are-numbered;
129
130			gpioa: gpio@40020000 {
131				gpio-controller;
132				#gpio-cells = <2>;
133				compatible = "st,stm32-gpio";
134				reg = <0x0 0x400>;
135				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
136				st,bank-name = "GPIOA";
137				u-boot,dm-pre-reloc;
138			};
139
140			gpiob: gpio@40020400 {
141				gpio-controller;
142				#gpio-cells = <2>;
143				compatible = "st,stm32-gpio";
144				reg = <0x400 0x400>;
145				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
146				st,bank-name = "GPIOB";
147				u-boot,dm-pre-reloc;
148			};
149
150
151			gpioc: gpio@40020800 {
152				gpio-controller;
153				#gpio-cells = <2>;
154				compatible = "st,stm32-gpio";
155				reg = <0x800 0x400>;
156				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
157				st,bank-name = "GPIOC";
158				u-boot,dm-pre-reloc;
159			};
160
161			gpiod: gpio@40020c00 {
162				gpio-controller;
163				#gpio-cells = <2>;
164				compatible = "st,stm32-gpio";
165				reg = <0xc00 0x400>;
166				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
167				st,bank-name = "GPIOD";
168				u-boot,dm-pre-reloc;
169			};
170
171			gpioe: gpio@40021000 {
172				gpio-controller;
173				#gpio-cells = <2>;
174				compatible = "st,stm32-gpio";
175				reg = <0x1000 0x400>;
176				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
177				st,bank-name = "GPIOE";
178				u-boot,dm-pre-reloc;
179			};
180
181			gpiof: gpio@40021400 {
182				gpio-controller;
183				#gpio-cells = <2>;
184				compatible = "st,stm32-gpio";
185				reg = <0x1400 0x400>;
186				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
187				st,bank-name = "GPIOF";
188				u-boot,dm-pre-reloc;
189			};
190
191			gpiog: gpio@40021800 {
192				gpio-controller;
193				#gpio-cells = <2>;
194				compatible = "st,stm32-gpio";
195				reg = <0x1800 0x400>;
196				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
197				st,bank-name = "GPIOG";
198				u-boot,dm-pre-reloc;
199			};
200
201			gpioh: gpio@40021c00 {
202				gpio-controller;
203				#gpio-cells = <2>;
204				compatible = "st,stm32-gpio";
205				reg = <0x1c00 0x400>;
206				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
207				st,bank-name = "GPIOH";
208				u-boot,dm-pre-reloc;
209			};
210
211			gpioi: gpio@40022000 {
212				gpio-controller;
213				#gpio-cells = <2>;
214				compatible = "st,stm32-gpio";
215				reg = <0x2000 0x400>;
216				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
217				st,bank-name = "GPIOI";
218				u-boot,dm-pre-reloc;
219			};
220
221			gpioj: gpio@40022400 {
222				gpio-controller;
223				#gpio-cells = <2>;
224				compatible = "st,stm32-gpio";
225				reg = <0x2400 0x400>;
226				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
227				st,bank-name = "GPIOJ";
228				u-boot,dm-pre-reloc;
229			};
230
231			gpiok: gpio@40022800 {
232				gpio-controller;
233				#gpio-cells = <2>;
234				compatible = "st,stm32-gpio";
235				reg = <0x2800 0x400>;
236				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
237				st,bank-name = "GPIOK";
238				u-boot,dm-pre-reloc;
239			};
240
241			sdio_pins: sdio_pins@0 {
242				pins {
243					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
244						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
245						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
246						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
247						 <STM32F746_PC12_FUNC_SDMMC1_CK>,
248						 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
249					drive-push-pull;
250					slew-rate = <2>;
251				};
252			};
253
254			sdio_pins_od: sdio_pins_od@0 {
255				pins1 {
256					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
257						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
258						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
259						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
260						 <STM32F746_PC12_FUNC_SDMMC1_CK>;
261					drive-push-pull;
262					slew-rate = <2>;
263				};
264
265				pins2 {
266					pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
267					drive-open-drain;
268					slew-rate = <2>;
269				};
270			};
271
272			sdio_pins_b: sdio_pins_b@0 {
273				pins {
274					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
275						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
276						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
277						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
278						 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
279						 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
280					drive-push-pull;
281					slew-rate = <2>;
282				};
283			};
284
285			sdio_pins_od_b: sdio_pins_od_b@0 {
286				pins1 {
287					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
288						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
289						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
290						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
291						 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
292					drive-push-pull;
293					slew-rate = <2>;
294				};
295
296				pins2 {
297					pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
298					drive-open-drain;
299					slew-rate = <2>;
300				};
301			};
302
303		};
304		sdio: sdio@40012c00 {
305			compatible = "st,stm32f4xx-sdio";
306			reg = <0x40012c00 0x400>;
307			clocks = <&rcc 0 171>;
308			interrupts = <49>;
309			status = "disabled";
310			pinctrl-0 = <&sdio_pins>;
311			pinctrl-1 = <&sdio_pins_od>;
312			pinctrl-names = "default", "opendrain";
313			max-frequency = <48000000>;
314		};
315
316		sdio2: sdio2@40011c00 {
317			compatible = "st,stm32f4xx-sdio";
318			reg = <0x40011c00 0x400>;
319			clocks = <&rcc 0 167>;
320			interrupts = <103>;
321			status = "disabled";
322			pinctrl-0 = <&sdio_pins_b>;
323			pinctrl-1 = <&sdio_pins_od_b>;
324			pinctrl-names = "default", "opendrain";
325			max-frequency = <48000000>;
326		};
327
328		timer5: timer@40000c00 {
329			compatible = "st,stm32-timer";
330			reg = <0x40000c00 0x400>;
331			interrupts = <50>;
332			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
333		};
334
335		ltdc: display-controller@40016800 {
336			compatible = "st,stm32-ltdc";
337			reg = <0x40016800 0x200>;
338			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
339			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
340			u-boot,dm-pre-reloc;
341			status = "disabled";
342		};
343	};
344};
345
346&systick {
347	status = "okay";
348};
349