1/*
2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
4 *
5 * Based on:
6 * stm32f469-disco.dts from Linux
7 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 *  a) This file is free software; you can redistribute it and/or
15 *     modify it under the terms of the GNU General Public License as
16 *     published by the Free Software Foundation; either version 2 of the
17 *     License, or (at your option) any later version.
18 *
19 *     This file is distributed in the hope that it will be useful,
20 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22 *     GNU General Public License for more details.
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "stm32f746.dtsi"
50#include <dt-bindings/memory/stm32-sdram.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54	model = "STMicroelectronics STM32F746-DISCO board";
55	compatible = "st,stm32f746-disco", "st,stm32f746";
56
57	chosen {
58		bootargs = "root=/dev/ram rdinit=/linuxrc";
59		stdout-path = "serial0:115200n8";
60	};
61
62	memory {
63		reg = <0xC0000000 0x800000>;
64	};
65
66	aliases {
67		serial0 = &usart1;
68		spi0 = &qspi;
69		mmc0 = &sdio;
70		/* Aliases for gpios so as to use sequence */
71		gpio0 = &gpioa;
72		gpio1 = &gpiob;
73		gpio2 = &gpioc;
74		gpio3 = &gpiod;
75		gpio4 = &gpioe;
76		gpio5 = &gpiof;
77		gpio6 = &gpiog;
78		gpio7 = &gpioh;
79		gpio8 = &gpioi;
80		gpio9 = &gpioj;
81		gpio10 = &gpiok;
82	};
83
84	led1 {
85		compatible = "st,led1";
86		led-gpio = <&gpioi 1 0>;
87	};
88
89	button1 {
90		compatible = "st,button1";
91		button-gpio = <&gpioi 11 0>;
92	};
93
94	backlight: backlight {
95		compatible = "gpio-backlight";
96		gpios = <&gpiok 3 0>;
97		status = "okay";
98	};
99
100	panel-rgb@0 {
101		compatible = "simple-panel";
102		backlight = <&backlight>;
103		enable-gpios = <&gpioi 12 0>;
104		status = "okay";
105
106		display-timings {
107			timing@0 {
108				clock-frequency = <9000000>;
109				hactive = <480>;
110				vactive = <272>;
111				hfront-porch = <2>;
112				hback-porch = <2>;
113				hsync-len = <41>;
114				vfront-porch = <2>;
115				vback-porch = <2>;
116				vsync-len = <10>;
117				hsync-active = <0>;
118				vsync-active = <0>;
119				de-active = <0>;
120				pixelclk-active = <1>;
121			};
122		};
123	};
124};
125
126&clk_hse {
127	clock-frequency = <25000000>;
128};
129
130&pinctrl {
131	usart1_pins_a: usart1@0	{
132		pins1 {
133		       pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
134				bias-disable;
135				drive-push-pull;
136				slew-rate = <2>;
137		};
138		pins2 {
139			pinmux = <STM32F746_PB7_FUNC_USART1_RX>;
140			bias-disable;
141		};
142	};
143
144	ethernet_mii: mii@0 {
145	      pins {
146		      pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
147			     <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
148			     <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
149			     <STM32F746_PA2_FUNC_ETH_MDIO>,
150			     <STM32F746_PC1_FUNC_ETH_MDC>,
151			     <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
152			     <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
153			     <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
154			     <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
155		      slew-rate = <2>;
156	      };
157	};
158
159	qspi_pins: qspi@0 {
160		pins {
161			pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
162			       <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
163			       <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>,
164			       <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>,
165			       <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
166			       <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
167			slew-rate = <2>;
168		};
169	};
170
171	fmc_pins: fmc@0 {
172		pins {
173			pinmux = <STM32F746_PD10_FUNC_FMC_D15>,
174				 <STM32F746_PD9_FUNC_FMC_D14>,
175				 <STM32F746_PD8_FUNC_FMC_D13>,
176				 <STM32F746_PE15_FUNC_FMC_D12>,
177				 <STM32F746_PE14_FUNC_FMC_D11>,
178				 <STM32F746_PE13_FUNC_FMC_D10>,
179				 <STM32F746_PE12_FUNC_FMC_D9>,
180				 <STM32F746_PE11_FUNC_FMC_D8>,
181				 <STM32F746_PE10_FUNC_FMC_D7>,
182				 <STM32F746_PE9_FUNC_FMC_D6>,
183				 <STM32F746_PE8_FUNC_FMC_D5>,
184				 <STM32F746_PE7_FUNC_FMC_D4>,
185				 <STM32F746_PD1_FUNC_FMC_D3>,
186				 <STM32F746_PD0_FUNC_FMC_D2>,
187				 <STM32F746_PD15_FUNC_FMC_D1>,
188				 <STM32F746_PD14_FUNC_FMC_D0>,
189
190				 <STM32F746_PE1_FUNC_FMC_NBL1>,
191				 <STM32F746_PE0_FUNC_FMC_NBL0>,
192
193				 <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
194				 <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
195
196				 <STM32F746_PG1_FUNC_FMC_A11>,
197				 <STM32F746_PG0_FUNC_FMC_A10>,
198				 <STM32F746_PF15_FUNC_FMC_A9>,
199				 <STM32F746_PF14_FUNC_FMC_A8>,
200				 <STM32F746_PF13_FUNC_FMC_A7>,
201				 <STM32F746_PF12_FUNC_FMC_A6>,
202				 <STM32F746_PF5_FUNC_FMC_A5>,
203				 <STM32F746_PF4_FUNC_FMC_A4>,
204				 <STM32F746_PF3_FUNC_FMC_A3>,
205				 <STM32F746_PF2_FUNC_FMC_A2>,
206				 <STM32F746_PF1_FUNC_FMC_A1>,
207				 <STM32F746_PF0_FUNC_FMC_A0>,
208
209				 <STM32F746_PH3_FUNC_FMC_SDNE0>,
210				 <STM32F746_PH5_FUNC_FMC_SDNWE>,
211				 <STM32F746_PF11_FUNC_FMC_SDNRAS>,
212				 <STM32F746_PG15_FUNC_FMC_SDNCAS>,
213				 <STM32F746_PC3_FUNC_FMC_SDCKE0>,
214				 <STM32F746_PG8_FUNC_FMC_SDCLK>;
215			  slew-rate = <2>;
216		};
217	};
218
219	ltdc_pins: ltdc@0 {
220		pins {
221			pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
222			       <STM32F746_PG12_FUNC_LCD_B4>,
223			       <STM32F746_PI9_FUNC_LCD_VSYNC>,
224			       <STM32F746_PI10_FUNC_LCD_HSYNC>,
225			       <STM32F746_PI14_FUNC_LCD_CLK>,
226			       <STM32F746_PI15_FUNC_LCD_R0>,
227			       <STM32F746_PJ0_FUNC_LCD_R1>,
228			       <STM32F746_PJ1_FUNC_LCD_R2>,
229			       <STM32F746_PJ2_FUNC_LCD_R3>,
230			       <STM32F746_PJ3_FUNC_LCD_R4>,
231			       <STM32F746_PJ4_FUNC_LCD_R5>,
232			       <STM32F746_PJ5_FUNC_LCD_R6>,
233			       <STM32F746_PJ6_FUNC_LCD_R7>,
234			       <STM32F746_PJ7_FUNC_LCD_G0>,
235			       <STM32F746_PJ8_FUNC_LCD_G1>,
236			       <STM32F746_PJ9_FUNC_LCD_G2>,
237			       <STM32F746_PJ10_FUNC_LCD_G3>,
238			       <STM32F746_PJ11_FUNC_LCD_G4>,
239			       <STM32F746_PJ13_FUNC_LCD_B1>,
240			       <STM32F746_PJ14_FUNC_LCD_B2>,
241			       <STM32F746_PJ15_FUNC_LCD_B3>,
242			       <STM32F746_PK0_FUNC_LCD_G5>,
243			       <STM32F746_PK1_FUNC_LCD_G6>,
244			       <STM32F746_PK2_FUNC_LCD_G7>,
245			       <STM32F746_PK4_FUNC_LCD_B5>,
246			       <STM32F746_PK5_FUNC_LCD_B6>,
247			       <STM32F746_PK6_FUNC_LCD_B7>,
248			       <STM32F746_PK7_FUNC_LCD_DE>;
249			slew-rate = <2>;
250		};
251	};
252};
253
254&usart1 {
255	pinctrl-0 = <&usart1_pins_a>;
256	pinctrl-names = "default";
257	status = "okay";
258};
259
260&fmc {
261	pinctrl-0 = <&fmc_pins>;
262	pinctrl-names = "default";
263	status = "okay";
264
265	/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
266	bank1: bank@0 {
267	       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
268	       				    CAS_3 SDCLK_2 RD_BURST_EN
269					    RD_PIPE_DL_0>;
270	       st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
271	       				   TRP_2 TRCD_2>;
272		/* refcount = (64msec/total_row_sdram)*freq - 20 */
273	       st,sdram-refcount = < 1542 >;
274       };
275};
276
277&mac {
278	status = "okay";
279	pinctrl-0 = <&ethernet_mii>;
280	phy-mode = "rmii";
281	phy-handle = <&phy0>;
282
283	mdio0 {
284		#address-cells = <1>;
285		#size-cells = <0>;
286		compatible = "snps,dwmac-mdio";
287		phy0: ethernet-phy@0 {
288			reg = <0>;
289		};
290	};
291};
292
293&qspi {
294	pinctrl-0 = <&qspi_pins>;
295	status = "okay";
296
297	qflash0: n25q128a {
298			#address-cells = <1>;
299			#size-cells = <1>;
300			compatible = "micron,n25q128a13", "spi-flash";
301			spi-max-frequency = <108000000>;
302			spi-tx-bus-width = <1>;
303			spi-rx-bus-width = <1>;
304			memory-map = <0x90000000 0x1000000>;
305			reg = <0>;
306	};
307};
308
309&sdio {
310	status = "okay";
311	cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
312	pinctrl-names = "default", "opendrain";
313	pinctrl-0 = <&sdio_pins>;
314	pinctrl-1 = <&sdio_pins_od>;
315	bus-width = <4>;
316	max-frequency = <25000000>;
317};
318
319&ltdc {
320	status = "okay";
321	pinctrl-0 = <&ltdc_pins>;
322};
323