1/* 2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved 3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics. 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include "skeleton.dtsi" 45#include "armv7-m.dtsi" 46#include <dt-bindings/clock/stm32fx-clock.h> 47#include <dt-bindings/mfd/stm32f4-rcc.h> 48 49/ { 50 clocks { 51 clk_hse: clk-hse { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <0>; 55 }; 56 57 clk_lse: clk-lse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 clk_lsi: clk-lsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32000>; 67 }; 68 69 clk_i2s_ckin: i2s-ckin { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <0>; 73 }; 74 }; 75 76 soc { 77 timer2: timer@40000000 { 78 compatible = "st,stm32-timer"; 79 reg = <0x40000000 0x400>; 80 interrupts = <28>; 81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 82 status = "disabled"; 83 }; 84 85 timers2: timers@40000000 { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 compatible = "st,stm32-timers"; 89 reg = <0x40000000 0x400>; 90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 91 clock-names = "int"; 92 status = "disabled"; 93 94 pwm { 95 compatible = "st,stm32-pwm"; 96 status = "disabled"; 97 }; 98 99 timer@1 { 100 compatible = "st,stm32-timer-trigger"; 101 reg = <1>; 102 status = "disabled"; 103 }; 104 }; 105 106 timer3: timer@40000400 { 107 compatible = "st,stm32-timer"; 108 reg = <0x40000400 0x400>; 109 interrupts = <29>; 110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 111 status = "disabled"; 112 }; 113 114 timers3: timers@40000400 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 compatible = "st,stm32-timers"; 118 reg = <0x40000400 0x400>; 119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 120 clock-names = "int"; 121 status = "disabled"; 122 123 pwm { 124 compatible = "st,stm32-pwm"; 125 status = "disabled"; 126 }; 127 128 timer@2 { 129 compatible = "st,stm32-timer-trigger"; 130 reg = <2>; 131 status = "disabled"; 132 }; 133 }; 134 135 timer4: timer@40000800 { 136 compatible = "st,stm32-timer"; 137 reg = <0x40000800 0x400>; 138 interrupts = <30>; 139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 140 status = "disabled"; 141 }; 142 143 timers4: timers@40000800 { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 compatible = "st,stm32-timers"; 147 reg = <0x40000800 0x400>; 148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 149 clock-names = "int"; 150 status = "disabled"; 151 152 pwm { 153 compatible = "st,stm32-pwm"; 154 status = "disabled"; 155 }; 156 157 timer@3 { 158 compatible = "st,stm32-timer-trigger"; 159 reg = <3>; 160 status = "disabled"; 161 }; 162 }; 163 164 timer5: timer@40000c00 { 165 compatible = "st,stm32-timer"; 166 reg = <0x40000c00 0x400>; 167 interrupts = <50>; 168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 169 }; 170 171 timers5: timers@40000c00 { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 compatible = "st,stm32-timers"; 175 reg = <0x40000C00 0x400>; 176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 177 clock-names = "int"; 178 status = "disabled"; 179 180 pwm { 181 compatible = "st,stm32-pwm"; 182 status = "disabled"; 183 }; 184 185 timer@4 { 186 compatible = "st,stm32-timer-trigger"; 187 reg = <4>; 188 status = "disabled"; 189 }; 190 }; 191 192 timer6: timer@40001000 { 193 compatible = "st,stm32-timer"; 194 reg = <0x40001000 0x400>; 195 interrupts = <54>; 196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 197 status = "disabled"; 198 }; 199 200 timers6: timers@40001000 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "st,stm32-timers"; 204 reg = <0x40001000 0x400>; 205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 206 clock-names = "int"; 207 status = "disabled"; 208 209 timer@5 { 210 compatible = "st,stm32-timer-trigger"; 211 reg = <5>; 212 status = "disabled"; 213 }; 214 }; 215 216 timer7: timer@40001400 { 217 compatible = "st,stm32-timer"; 218 reg = <0x40001400 0x400>; 219 interrupts = <55>; 220 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 221 status = "disabled"; 222 }; 223 224 timers7: timers@40001400 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "st,stm32-timers"; 228 reg = <0x40001400 0x400>; 229 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 230 clock-names = "int"; 231 status = "disabled"; 232 233 timer@6 { 234 compatible = "st,stm32-timer-trigger"; 235 reg = <6>; 236 status = "disabled"; 237 }; 238 }; 239 240 timers12: timers@40001800 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "st,stm32-timers"; 244 reg = <0x40001800 0x400>; 245 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; 246 clock-names = "int"; 247 status = "disabled"; 248 249 pwm { 250 compatible = "st,stm32-pwm"; 251 status = "disabled"; 252 }; 253 254 timer@11 { 255 compatible = "st,stm32-timer-trigger"; 256 reg = <11>; 257 status = "disabled"; 258 }; 259 }; 260 261 timers13: timers@40001c00 { 262 #size-cells = <0>; 263 compatible = "st,stm32-timers"; 264 reg = <0x40001C00 0x400>; 265 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; 266 clock-names = "int"; 267 status = "disabled"; 268 269 pwm { 270 compatible = "st,stm32-pwm"; 271 status = "disabled"; 272 }; 273 }; 274 275 timers14: timers@40002000 { 276 #size-cells = <0>; 277 compatible = "st,stm32-timers"; 278 reg = <0x40002000 0x400>; 279 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; 280 clock-names = "int"; 281 status = "disabled"; 282 283 pwm { 284 compatible = "st,stm32-pwm"; 285 status = "disabled"; 286 }; 287 }; 288 289 rtc: rtc@40002800 { 290 compatible = "st,stm32-rtc"; 291 reg = <0x40002800 0x400>; 292 clocks = <&rcc 1 CLK_RTC>; 293 clock-names = "ck_rtc"; 294 assigned-clocks = <&rcc 1 CLK_RTC>; 295 assigned-clock-parents = <&rcc 1 CLK_LSE>; 296 interrupt-parent = <&exti>; 297 interrupts = <17 1>; 298 interrupt-names = "alarm"; 299 st,syscfg = <&pwrcfg>; 300 status = "disabled"; 301 }; 302 303 iwdg: watchdog@40003000 { 304 compatible = "st,stm32-iwdg"; 305 reg = <0x40003000 0x400>; 306 clocks = <&clk_lsi>; 307 status = "disabled"; 308 }; 309 310 usart2: serial@40004400 { 311 compatible = "st,stm32-uart"; 312 reg = <0x40004400 0x400>; 313 interrupts = <38>; 314 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; 315 status = "disabled"; 316 }; 317 318 usart3: serial@40004800 { 319 compatible = "st,stm32-uart"; 320 reg = <0x40004800 0x400>; 321 interrupts = <39>; 322 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; 323 status = "disabled"; 324 dmas = <&dma1 1 4 0x400 0x0>, 325 <&dma1 3 4 0x400 0x0>; 326 dma-names = "rx", "tx"; 327 }; 328 329 usart4: serial@40004c00 { 330 compatible = "st,stm32-uart"; 331 reg = <0x40004c00 0x400>; 332 interrupts = <52>; 333 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; 334 status = "disabled"; 335 }; 336 337 usart5: serial@40005000 { 338 compatible = "st,stm32-uart"; 339 reg = <0x40005000 0x400>; 340 interrupts = <53>; 341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; 342 status = "disabled"; 343 }; 344 345 i2c1: i2c@40005400 { 346 compatible = "st,stm32f4-i2c"; 347 reg = <0x40005400 0x400>; 348 interrupts = <31>, 349 <32>; 350 resets = <&rcc STM32F4_APB1_RESET(I2C1)>; 351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 dac: dac@40007400 { 358 compatible = "st,stm32f4-dac-core"; 359 reg = <0x40007400 0x400>; 360 resets = <&rcc STM32F4_APB1_RESET(DAC)>; 361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; 362 clock-names = "pclk"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 status = "disabled"; 366 367 dac1: dac@1 { 368 compatible = "st,stm32-dac"; 369 #io-channels-cells = <1>; 370 reg = <1>; 371 status = "disabled"; 372 }; 373 374 dac2: dac@2 { 375 compatible = "st,stm32-dac"; 376 #io-channels-cells = <1>; 377 reg = <2>; 378 status = "disabled"; 379 }; 380 }; 381 382 usart7: serial@40007800 { 383 compatible = "st,stm32-uart"; 384 reg = <0x40007800 0x400>; 385 interrupts = <82>; 386 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; 387 status = "disabled"; 388 }; 389 390 usart8: serial@40007c00 { 391 compatible = "st,stm32-uart"; 392 reg = <0x40007c00 0x400>; 393 interrupts = <83>; 394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; 395 status = "disabled"; 396 }; 397 398 timers1: timers@40010000 { 399 #address-cells = <1>; 400 #size-cells = <0>; 401 compatible = "st,stm32-timers"; 402 reg = <0x40010000 0x400>; 403 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; 404 clock-names = "int"; 405 status = "disabled"; 406 407 pwm { 408 compatible = "st,stm32-pwm"; 409 status = "disabled"; 410 }; 411 412 timer@0 { 413 compatible = "st,stm32-timer-trigger"; 414 reg = <0>; 415 status = "disabled"; 416 }; 417 }; 418 419 timers8: timers@40010400 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 compatible = "st,stm32-timers"; 423 reg = <0x40010400 0x400>; 424 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; 425 clock-names = "int"; 426 status = "disabled"; 427 428 pwm { 429 compatible = "st,stm32-pwm"; 430 status = "disabled"; 431 }; 432 433 timer@7 { 434 compatible = "st,stm32-timer-trigger"; 435 reg = <7>; 436 status = "disabled"; 437 }; 438 }; 439 440 usart1: serial@40011000 { 441 compatible = "st,stm32-uart"; 442 reg = <0x40011000 0x400>; 443 interrupts = <37>; 444 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; 445 status = "disabled"; 446 dmas = <&dma2 2 4 0x400 0x0>, 447 <&dma2 7 4 0x400 0x0>; 448 dma-names = "rx", "tx"; 449 }; 450 451 usart6: serial@40011400 { 452 compatible = "st,stm32-uart"; 453 reg = <0x40011400 0x400>; 454 interrupts = <71>; 455 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; 456 status = "disabled"; 457 }; 458 459 adc: adc@40012000 { 460 compatible = "st,stm32f4-adc-core"; 461 reg = <0x40012000 0x400>; 462 interrupts = <18>; 463 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 464 clock-names = "adc"; 465 interrupt-controller; 466 #interrupt-cells = <1>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 471 adc1: adc@0 { 472 compatible = "st,stm32f4-adc"; 473 #io-channel-cells = <1>; 474 reg = <0x0>; 475 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 476 interrupt-parent = <&adc>; 477 interrupts = <0>; 478 dmas = <&dma2 0 0 0x400 0x0>; 479 dma-names = "rx"; 480 status = "disabled"; 481 }; 482 483 adc2: adc@100 { 484 compatible = "st,stm32f4-adc"; 485 #io-channel-cells = <1>; 486 reg = <0x100>; 487 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; 488 interrupt-parent = <&adc>; 489 interrupts = <1>; 490 dmas = <&dma2 3 1 0x400 0x0>; 491 dma-names = "rx"; 492 status = "disabled"; 493 }; 494 495 adc3: adc@200 { 496 compatible = "st,stm32f4-adc"; 497 #io-channel-cells = <1>; 498 reg = <0x200>; 499 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; 500 interrupt-parent = <&adc>; 501 interrupts = <2>; 502 dmas = <&dma2 1 2 0x400 0x0>; 503 dma-names = "rx"; 504 status = "disabled"; 505 }; 506 }; 507 508 syscfg: system-config@40013800 { 509 compatible = "syscon"; 510 reg = <0x40013800 0x400>; 511 }; 512 513 exti: interrupt-controller@40013c00 { 514 compatible = "st,stm32-exti"; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 reg = <0x40013C00 0x400>; 518 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 519 }; 520 521 timers9: timers@40014000 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 compatible = "st,stm32-timers"; 525 reg = <0x40014000 0x400>; 526 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; 527 clock-names = "int"; 528 status = "disabled"; 529 530 pwm { 531 compatible = "st,stm32-pwm"; 532 status = "disabled"; 533 }; 534 535 timer@8 { 536 compatible = "st,stm32-timer-trigger"; 537 reg = <8>; 538 status = "disabled"; 539 }; 540 }; 541 542 timers10: timers@40014400 { 543 #size-cells = <0>; 544 compatible = "st,stm32-timers"; 545 reg = <0x40014400 0x400>; 546 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; 547 clock-names = "int"; 548 status = "disabled"; 549 550 pwm { 551 compatible = "st,stm32-pwm"; 552 status = "disabled"; 553 }; 554 }; 555 556 timers11: timers@40014800 { 557 #size-cells = <0>; 558 compatible = "st,stm32-timers"; 559 reg = <0x40014800 0x400>; 560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; 561 clock-names = "int"; 562 status = "disabled"; 563 564 pwm { 565 compatible = "st,stm32-pwm"; 566 status = "disabled"; 567 }; 568 }; 569 570 pwrcfg: power-config@40007000 { 571 compatible = "syscon"; 572 reg = <0x40007000 0x400>; 573 }; 574 575 sdio: sdio@40012c00 { 576 compatible = "st,stm32f4xx-sdio"; 577 reg = <0x40012c00 0x400>; 578 clocks = <&rcc 0 171>; 579 interrupts = <49>; 580 status = "disabled"; 581 pinctrl-0 = <&sdio_pins>; 582 pinctrl-1 = <&sdio_pins_od>; 583 pinctrl-names = "default", "opendrain"; 584 max-frequency = <48000000>; 585 }; 586 587 ltdc: display-controller@40016800 { 588 compatible = "st,stm32-ltdc"; 589 reg = <0x40016800 0x200>; 590 interrupts = <88>, <89>; 591 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 592 clocks = <&rcc 1 CLK_LCD>; 593 clock-names = "lcd"; 594 status = "disabled"; 595 }; 596 597 crc: crc@40023000 { 598 compatible = "st,stm32f4-crc"; 599 reg = <0x40023000 0x400>; 600 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; 601 status = "disabled"; 602 }; 603 604 rcc: rcc@40023810 { 605 #reset-cells = <1>; 606 #clock-cells = <2>; 607 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 608 reg = <0x40023800 0x400>; 609 clocks = <&clk_hse>, <&clk_i2s_ckin>; 610 st,syscfg = <&pwrcfg>; 611 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 612 assigned-clock-rates = <1000000>; 613 }; 614 615 dma1: dma-controller@40026000 { 616 compatible = "st,stm32-dma"; 617 reg = <0x40026000 0x400>; 618 interrupts = <11>, 619 <12>, 620 <13>, 621 <14>, 622 <15>, 623 <16>, 624 <17>, 625 <47>; 626 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; 627 #dma-cells = <4>; 628 }; 629 630 dma2: dma-controller@40026400 { 631 compatible = "st,stm32-dma"; 632 reg = <0x40026400 0x400>; 633 interrupts = <56>, 634 <57>, 635 <58>, 636 <59>, 637 <60>, 638 <68>, 639 <69>, 640 <70>; 641 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; 642 #dma-cells = <4>; 643 st,mem2mem; 644 }; 645 646 mac: ethernet@40028000 { 647 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; 648 reg = <0x40028000 0x8000>; 649 reg-names = "stmmaceth"; 650 interrupts = <61>; 651 interrupt-names = "macirq"; 652 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 653 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, 654 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, 655 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; 656 st,syscon = <&syscfg 0x4>; 657 snps,pbl = <8>; 658 snps,mixed-burst; 659 status = "disabled"; 660 }; 661 662 usbotg_hs: usb@40040000 { 663 compatible = "snps,dwc2"; 664 reg = <0x40040000 0x40000>; 665 interrupts = <77>; 666 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; 667 clock-names = "otg"; 668 status = "disabled"; 669 }; 670 671 usbotg_fs: usb@50000000 { 672 compatible = "st,stm32f4x9-fsotg"; 673 reg = <0x50000000 0x40000>; 674 interrupts = <67>; 675 clocks = <&rcc 0 39>; 676 clock-names = "otg"; 677 status = "disabled"; 678 }; 679 680 dcmi: dcmi@50050000 { 681 compatible = "st,stm32-dcmi"; 682 reg = <0x50050000 0x400>; 683 interrupts = <78>; 684 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; 685 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; 686 clock-names = "mclk"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&dcmi_pins>; 689 dmas = <&dma2 1 1 0x414 0x3>; 690 dma-names = "tx"; 691 status = "disabled"; 692 }; 693 694 rng: rng@50060800 { 695 compatible = "st,stm32-rng"; 696 reg = <0x50060800 0x400>; 697 interrupts = <80>; 698 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; 699 700 }; 701 }; 702}; 703 704&systick { 705 clocks = <&rcc 1 SYSTICK>; 706 status = "okay"; 707}; 708